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| author | maxims@google.com <maxims@google.com> | 2017-01-30 11:35:04 -0800 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2017-02-08 15:56:30 -0500 |
| commit | d5ce3574619d6814ea095a798702e342d45203d4 (patch) | |
| tree | 29505cad383e11e624d7fa6c94350344d29f3307 | |
| parent | e163a931af34ba06d11b98707b69b8819e353257 (diff) | |
| download | u-boot-d5ce3574619d6814ea095a798702e342d45203d4.tar.gz u-boot-d5ce3574619d6814ea095a798702e342d45203d4.tar.bz2 u-boot-d5ce3574619d6814ea095a798702e342d45203d4.zip | |
aspeed: ast2500: Fix H-PLL and M-PLL clock rate calculation
Fix H-PLL and M-PLL rate calculation in ast2500 clock driver.
Without this fix, valid setting can lead to division by zero
when requesting the rate of H-PLL or M-PLL clocks.
Signed-off-by: Maxim Sloyko <maxims@google.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
| -rw-r--r-- | drivers/clk/aspeed/clk_ast2500.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/clk/aspeed/clk_ast2500.c b/drivers/clk/aspeed/clk_ast2500.c index af369cc4c8..26a5e58221 100644 --- a/drivers/clk/aspeed/clk_ast2500.c +++ b/drivers/clk/aspeed/clk_ast2500.c @@ -35,7 +35,7 @@ static ulong ast2500_get_mpll_rate(ulong clkin, u32 mpll_reg) const ulong post_div = (mpll_reg >> SCU_MPLL_POST_SHIFT) & SCU_MPLL_POST_MASK; - return (clkin * ((num + 1) / (denum + 1))) / post_div; + return (clkin * ((num + 1) / (denum + 1))) / (post_div + 1); } /* @@ -50,7 +50,7 @@ static ulong ast2500_get_hpll_rate(ulong clkin, u32 hpll_reg) const ulong post_div = (hpll_reg >> SCU_HPLL_POST_SHIFT) & SCU_HPLL_POST_MASK; - return (clkin * ((num + 1) / (denum + 1))) / post_div; + return (clkin * ((num + 1) / (denum + 1))) / (post_div + 1); } static ulong ast2500_get_clkin(struct ast2500_scu *scu) |