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| author | Xiaowei Bao <xiaowei.bao@nxp.com> | 2020-07-09 23:31:38 +0800 |
|---|---|---|
| committer | Priyanka Jain <priyanka.jain@nxp.com> | 2020-07-27 14:24:15 +0530 |
| commit | 78c56b29fc908b1fc573f7b1be53cf58a8546e0b (patch) | |
| tree | dab1a9837a09f2dabc23416501f04ea70040863a | |
| parent | 15ce1fadf7f00a93021b8d013147b4bcd23099f2 (diff) | |
| download | u-boot-78c56b29fc908b1fc573f7b1be53cf58a8546e0b.tar.gz u-boot-78c56b29fc908b1fc573f7b1be53cf58a8546e0b.tar.bz2 u-boot-78c56b29fc908b1fc573f7b1be53cf58a8546e0b.zip | |
pci_ep: layerscape: Add Support for ls2085a and ls2080a EP mode
Due to the ls2085a and ls2080a use different way to set the BAR size,
so add the BAR size init code here.
Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| -rw-r--r-- | drivers/pci/pcie_layerscape_ep.c | 18 |
1 files changed, 13 insertions, 5 deletions
diff --git a/drivers/pci/pcie_layerscape_ep.c b/drivers/pci/pcie_layerscape_ep.c index 3f22c5ef7a..20de056b8a 100644 --- a/drivers/pci/pcie_layerscape_ep.c +++ b/drivers/pci/pcie_layerscape_ep.c @@ -173,17 +173,25 @@ static void ls_pcie_setup_ep(struct ls_pcie_ep *pcie_ep) */ writel(0, pcie->dbi + PCIE_MISC_CONTROL_1_OFF); + bar_base = pcie->dbi + + PCIE_MASK_OFFSET(pcie_ep->cfg2_flag, pf); + if (pcie_ep->cfg2_flag) { - for (vf = 0; vf <= PCIE_VF_NUM; vf++) { + ctrl_writel(pcie, + PCIE_LCTRL0_VAL(pf, 0), + PCIE_PF_VF_CTRL); + ls_pcie_ep_setup_bars(bar_base); + + for (vf = 1; vf <= PCIE_VF_NUM; vf++) { ctrl_writel(pcie, PCIE_LCTRL0_VAL(pf, vf), PCIE_PF_VF_CTRL); + ls_pcie_ep_setup_vf_bars(bar_base); } + } else { + ls_pcie_ep_setup_bars(bar_base); + ls_pcie_ep_setup_vf_bars(bar_base); } - bar_base = pcie->dbi + - PCIE_MASK_OFFSET(pcie_ep->cfg2_flag, pf); - ls_pcie_ep_setup_bars(bar_base); - ls_pcie_ep_setup_vf_bars(bar_base); ls_pcie_ep_setup_atu(pcie_ep, pf); } |