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| author | Weijie Gao <weijie.gao@mediatek.com> | 2019-09-25 17:45:28 +0800 |
|---|---|---|
| committer | Daniel Schwierzeck <daniel.schwierzeck@gmail.com> | 2019-10-25 17:20:44 +0200 |
| commit | 123ffd467903502fbd878ad73a1c19f5f65523d8 (patch) | |
| tree | 3680fc09f2f4adaf44493bebdbf8fad8bd304fda | |
| parent | fdf92df285084ec8ec994677f2ec1e5665e66eb2 (diff) | |
| download | u-boot-123ffd467903502fbd878ad73a1c19f5f65523d8.tar.gz u-boot-123ffd467903502fbd878ad73a1c19f5f65523d8.tar.bz2 u-boot-123ffd467903502fbd878ad73a1c19f5f65523d8.zip | |
dts: mtmips: add default pinctrl for uart nodes
This patch adds default pinctrl for uart nodes
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
| -rw-r--r-- | arch/mips/dts/mt7628a.dtsi | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/arch/mips/dts/mt7628a.dtsi b/arch/mips/dts/mt7628a.dtsi index 8afea1865d..44fbbd5b25 100644 --- a/arch/mips/dts/mt7628a.dtsi +++ b/arch/mips/dts/mt7628a.dtsi @@ -286,6 +286,9 @@ compatible = "mediatek,hsuart", "ns16550a"; reg = <0xc00 0x100>; + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; + clocks = <&clkctrl CLK_UART0>; resets = <&resetc 12>; @@ -301,6 +304,9 @@ compatible = "mediatek,hsuart", "ns16550a"; reg = <0xd00 0x100>; + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; + clocks = <&clkctrl CLK_UART1>; resets = <&resetc 19>; @@ -316,6 +322,9 @@ compatible = "mediatek,hsuart", "ns16550a"; reg = <0xe00 0x100>; + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; + clocks = <&clkctrl CLK_UART2>; resets = <&resetc 20>; |