diff options
| author | Michal Wilczynski <m.wilczynski@samsung.com> | 2023-09-12 15:25:10 +0800 |
|---|---|---|
| committer | Michal Wilczynski <m.wilczynski@samsung.com> | 2024-08-12 17:18:09 +0200 |
| commit | 955216a8578864eaa5f722deec0b3c4f3160416f (patch) | |
| tree | d8378cb2802153b7ebbd3859613f7f5c2b2969f9 | |
| parent | a12033607119b2a5ab38d419811f2a127a749faa (diff) | |
| download | linux-thead-955216a8578864eaa5f722deec0b3c4f3160416f.tar.gz linux-thead-955216a8578864eaa5f722deec0b3c4f3160416f.tar.bz2 linux-thead-955216a8578864eaa5f722deec0b3c4f3160416f.zip | |
riscv: mm: update T-Head memory type definitions
Update T-Head memory type definitions according to C910 doc [1]
For NC and IO, SH property isn't configurable, hardcoded as SH,
so set SH for NOCACHE and IO.
And also set bit[61](Bufferable) for NOCACHE according to the
table 6.1 in the doc [1].
Link: https://github.com/T-head-Semi/openc910 [1]
Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
Reviewed-by: Guo Ren <guoren@kernel.org>
Tested-by: Drew Fustini <dfustini@baylibre.com>
Link: https://lore.kernel.org/r/20230912072510.2510-1-jszhang@kernel.org
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
[ need this commit for GPU to work as the GPU driver is manually setting
page properties ]
Signed-off-by: Michal Wilczynski <m.wilczynski@samsung.com>
Change-Id: I62a5af81620466024fdf5bf9c3f322aadddf6366
| -rw-r--r-- | arch/riscv/include/asm/pgtable-64.h | 14 |
1 files changed, 9 insertions, 5 deletions
diff --git a/arch/riscv/include/asm/pgtable-64.h b/arch/riscv/include/asm/pgtable-64.h index 7a5097202e15..9a2c780a11e9 100644 --- a/arch/riscv/include/asm/pgtable-64.h +++ b/arch/riscv/include/asm/pgtable-64.h @@ -126,14 +126,18 @@ enum napot_cont_order { /* * [63:59] T-Head Memory Type definitions: - * - * 00000 - NC Weakly-ordered, Non-cacheable, Non-bufferable, Non-shareable, Non-trustable + * bit[63] SO - Strong Order + * bit[62] C - Cacheable + * bit[61] B - Bufferable + * bit[60] SH - Shareable + * bit[59] Sec - Trustable + * 00110 - NC Weakly-ordered, Non-cacheable, Bufferable, Shareable, Non-trustable * 01110 - PMA Weakly-ordered, Cacheable, Bufferable, Shareable, Non-trustable - * 10000 - IO Strongly-ordered, Non-cacheable, Non-bufferable, Non-shareable, Non-trustable + * 10010 - IO Strongly-ordered, Non-cacheable, Non-bufferable, Shareable, Non-trustable */ #define _PAGE_PMA_THEAD ((1UL << 62) | (1UL << 61) | (1UL << 60)) -#define _PAGE_NOCACHE_THEAD 0UL -#define _PAGE_IO_THEAD (1UL << 63) +#define _PAGE_NOCACHE_THEAD ((1UL < 61) | (1UL << 60)) +#define _PAGE_IO_THEAD ((1UL << 63) | (1UL << 60)) #define _PAGE_MTMASK_THEAD (_PAGE_PMA_THEAD | _PAGE_IO_THEAD | (1UL << 59)) static inline u64 riscv_page_mtmask(void) |