diff options
| author | Zhang Rui <rui.zhang@intel.com> | 2020-08-11 23:31:49 +0800 |
|---|---|---|
| committer | Ingo Molnar <mingo@kernel.org> | 2020-08-14 12:35:12 +0200 |
| commit | bcfd218b66790243ef303c1b35ce59f786ded225 (patch) | |
| tree | 949e7bae35d62ee8a200c9a5cb7873b71cc9bf45 /arch | |
| parent | 74f41adab0f4a61857833e1b6fa8e9ad12c251b6 (diff) | |
| download | linux-starfive-bcfd218b66790243ef303c1b35ce59f786ded225.tar.gz linux-starfive-bcfd218b66790243ef303c1b35ce59f786ded225.tar.bz2 linux-starfive-bcfd218b66790243ef303c1b35ce59f786ded225.zip | |
perf/x86/rapl: Add support for Intel SPR platform
Intel SPR platform uses fixed 16 bit energy unit for DRAM RAPL domain,
and fixed 0 bit energy unit for Psys RAPL domain.
After this, on SPR platform the energy counters appear in perf list.
Signed-off-by: Zhang Rui <rui.zhang@intel.com>
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Reviewed-by: Kan Liang <kan.liang@linux.intel.com>
Acked-by: Len Brown <len.brown@intel.com>
Link: https://lore.kernel.org/r/20200811153149.12242-4-rui.zhang@intel.com
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/x86/events/rapl.c | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/arch/x86/events/rapl.c b/arch/x86/events/rapl.c index d0002eb971b7..67b411f7e8c4 100644 --- a/arch/x86/events/rapl.c +++ b/arch/x86/events/rapl.c @@ -133,6 +133,7 @@ struct rapl_pmus { enum rapl_unit_quirk { RAPL_UNIT_QUIRK_NONE, RAPL_UNIT_QUIRK_INTEL_HSW, + RAPL_UNIT_QUIRK_INTEL_SPR, }; struct rapl_model { @@ -627,6 +628,14 @@ static int rapl_check_hw_unit(struct rapl_model *rm) case RAPL_UNIT_QUIRK_INTEL_HSW: rapl_hw_unit[PERF_RAPL_RAM] = 16; break; + /* + * SPR shares the same DRAM domain energy unit as HSW, plus it + * also has a fixed energy unit for Psys domain. + */ + case RAPL_UNIT_QUIRK_INTEL_SPR: + rapl_hw_unit[PERF_RAPL_RAM] = 16; + rapl_hw_unit[PERF_RAPL_PSYS] = 0; + break; default: break; } @@ -757,6 +766,16 @@ static struct rapl_model model_skl = { .rapl_msrs = intel_rapl_msrs, }; +static struct rapl_model model_spr = { + .events = BIT(PERF_RAPL_PP0) | + BIT(PERF_RAPL_PKG) | + BIT(PERF_RAPL_RAM) | + BIT(PERF_RAPL_PSYS), + .unit_quirk = RAPL_UNIT_QUIRK_INTEL_SPR, + .msr_power_unit = MSR_RAPL_POWER_UNIT, + .rapl_msrs = intel_rapl_msrs, +}; + static struct rapl_model model_amd_fam17h = { .events = BIT(PERF_RAPL_PKG), .msr_power_unit = MSR_AMD_RAPL_POWER_UNIT, @@ -793,6 +812,7 @@ static const struct x86_cpu_id rapl_model_match[] __initconst = { X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_X, &model_hsx), X86_MATCH_INTEL_FAM6_MODEL(COMETLAKE_L, &model_skl), X86_MATCH_INTEL_FAM6_MODEL(COMETLAKE, &model_skl), + X86_MATCH_INTEL_FAM6_MODEL(SAPPHIRERAPIDS_X, &model_spr), X86_MATCH_VENDOR_FAM(AMD, 0x17, &model_amd_fam17h), X86_MATCH_VENDOR_FAM(HYGON, 0x18, &model_amd_fam17h), {}, |