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| author | andy.hu <andy.hu@starfivetech.com> | 2022-10-14 07:34:12 +0000 |
|---|---|---|
| committer | andy.hu <andy.hu@starfivetech.com> | 2022-10-14 07:34:12 +0000 |
| commit | 2577c2b760ff5b7c394ece88e947229803cf9dff (patch) | |
| tree | f7d1fc5b8cb02351d3487b065c92d6307d48a4d2 /arch | |
| parent | d153a0eaf64c465cc118c4891a2db6d888bbbb57 (diff) | |
| parent | 055d9ee5607e01a026868ac09c542d6496e39d24 (diff) | |
| download | linux-starfive-2577c2b760ff5b7c394ece88e947229803cf9dff.tar.gz linux-starfive-2577c2b760ff5b7c394ece88e947229803cf9dff.tar.bz2 linux-starfive-2577c2b760ff5b7c394ece88e947229803cf9dff.zip | |
Merge branch 'CR_2285_SEC_jiajie.ho' into 'jh7110-5.15.y-devel'
Cr 2285 sec jiajie.ho
See merge request sdk/linux!533
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/riscv/boot/dts/starfive/jh7110.dtsi | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi index 21af51def983..99db7b0cafd4 100644 --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi @@ -712,13 +712,14 @@ }; sec_dma: sec_dma@16008000 { - compatible = "starfive,jh7110-pl080", "arm,pl080"; + compatible = "arm,pl080", "arm,primecell"; + arm,primecell-periphid = <0x00041080>; reg = <0x0 0x16008000 0x0 0x4000>; reg-names = "sec_dma"; interrupts = <29>; clocks = <&clkgen JH7110_SEC_HCLK>, <&clkgen JH7110_SEC_MISCAHB_CLK>; - clock-names = "sec_hclk","sec_ahb"; + clock-names = "sec_hclk","apb_pclk"; resets = <&rstgen RSTN_U0_SEC_TOP_HRESETN>; reset-names = "sec_hre"; lli-bus-interface-ahb1; |