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| author | Jayachandran C <jchandra@broadcom.com> | 2013-12-21 16:52:23 +0530 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2014-01-24 22:39:48 +0100 |
| commit | 861c056953dc4354414881a5e1d382297ef4ea53 (patch) | |
| tree | 9bfdf545e1335f0dbf41bfd081bfebb72f759460 /arch/mips/include | |
| parent | d150cef4e8cc723d90226e503ef6aff2ca9fc57c (diff) | |
| download | linux-stable-861c056953dc4354414881a5e1d382297ef4ea53.tar.gz linux-stable-861c056953dc4354414881a5e1d382297ef4ea53.tar.bz2 linux-stable-861c056953dc4354414881a5e1d382297ef4ea53.zip | |
MIPS: Netlogic: SYS block updates of XLP9XX
Add the SYS block registers for XLP9XX, most of them have changed.
The wakeup sequence has been updated to set the coherent mode from
the main thread rather than the woken up thread.
Signed-off-by: Jayachandran C <jchandra@broadcom.com>
Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6280/
Diffstat (limited to 'arch/mips/include')
| -rw-r--r-- | arch/mips/include/asm/netlogic/xlp-hal/sys.h | 18 |
1 files changed, 17 insertions, 1 deletions
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/sys.h b/arch/mips/include/asm/netlogic/xlp-hal/sys.h index fcf2833c16ca..d9b107ffca93 100644 --- a/arch/mips/include/asm/netlogic/xlp-hal/sys.h +++ b/arch/mips/include/asm/netlogic/xlp-hal/sys.h @@ -147,13 +147,29 @@ #define SYS_SYS_PLL_MEM_REQ 0x2a3 #define SYS_PLL_MEM_STAT 0x2a4 +/* Registers changed on 9XX */ +#define SYS_9XX_POWER_ON_RESET_CFG 0x00 +#define SYS_9XX_CHIP_RESET 0x01 +#define SYS_9XX_CPU_RESET 0x02 +#define SYS_9XX_CPU_NONCOHERENT_MODE 0x03 + +/* XLP 9XX fuse block registers */ +#define FUSE_9XX_DEVCFG6 0xc6 + #ifndef __ASSEMBLY__ #define nlm_read_sys_reg(b, r) nlm_read_reg(b, r) #define nlm_write_sys_reg(b, r, v) nlm_write_reg(b, r, v) -#define nlm_get_sys_pcibase(node) nlm_pcicfg_base(XLP_IO_SYS_OFFSET(node)) +#define nlm_get_sys_pcibase(node) nlm_pcicfg_base(cpu_is_xlp9xx() ? \ + XLP9XX_IO_SYS_OFFSET(node) : XLP_IO_SYS_OFFSET(node)) #define nlm_get_sys_regbase(node) (nlm_get_sys_pcibase(node) + XLP_IO_PCI_HDRSZ) +/* XLP9XX fuse block */ +#define nlm_get_fuse_pcibase(node) \ + nlm_pcicfg_base(XLP9XX_IO_FUSE_OFFSET(node)) +#define nlm_get_fuse_regbase(node) \ + (nlm_get_fuse_pcibase(node) + XLP_IO_PCI_HDRSZ) + unsigned int nlm_get_pic_frequency(int node); #endif #endif |