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| author | Catalin Marinas <catalin.marinas@arm.com> | 2018-05-11 13:33:12 +0100 |
|---|---|---|
| committer | Catalin Marinas <catalin.marinas@arm.com> | 2018-05-15 13:29:55 +0100 |
| commit | ebc7e21e0fa28c46b938baed292c77e2d3ef8165 (patch) | |
| tree | fa415205a2ea1ff232aee0b7a6c4e998837b77ef /arch/arm64/mm | |
| parent | d93277b9839b0bde06238a7a7f644114edb2ad4a (diff) | |
| download | linux-rpi3-ebc7e21e0fa28c46b938baed292c77e2d3ef8165.tar.gz linux-rpi3-ebc7e21e0fa28c46b938baed292c77e2d3ef8165.tar.bz2 linux-rpi3-ebc7e21e0fa28c46b938baed292c77e2d3ef8165.zip | |
arm64: Increase ARCH_DMA_MINALIGN to 128
This patch increases the ARCH_DMA_MINALIGN to 128 so that it covers the
currently known Cache Writeback Granule (CTR_EL0.CWG) on arm64 and moves
the fallback in cache_line_size() from L1_CACHE_BYTES to this constant.
In addition, it warns (and taints) if the CWG is larger than
ARCH_DMA_MINALIGN as this is not safe with non-coherent DMA.
Cc: Will Deacon <will.deacon@arm.com>
Cc: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Diffstat (limited to 'arch/arm64/mm')
| -rw-r--r-- | arch/arm64/mm/dma-mapping.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/arm64/mm/dma-mapping.c b/arch/arm64/mm/dma-mapping.c index a96ec0181818..ed84432264de 100644 --- a/arch/arm64/mm/dma-mapping.c +++ b/arch/arm64/mm/dma-mapping.c @@ -504,6 +504,11 @@ static int __init arm64_dma_init(void) max_pfn > (arm64_dma_phys_limit >> PAGE_SHIFT)) swiotlb = 1; + WARN_TAINT(ARCH_DMA_MINALIGN < cache_line_size(), + TAINT_CPU_OUT_OF_SPEC, + "ARCH_DMA_MINALIGN smaller than CTR_EL0.CWG (%d < %d)", + ARCH_DMA_MINALIGN, cache_line_size()); + return atomic_pool_init(); } arch_initcall(arm64_dma_init); |