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| author | Eric Anholt <eric@anholt.net> | 2017-06-27 12:58:32 -0700 |
|---|---|---|
| committer | Inki Dae <inki.dae@samsung.com> | 2017-09-08 14:04:43 +0900 |
| commit | 2ac76646b3af0ce080f3c3797108411ee40b5471 (patch) | |
| tree | 13a88ae3531317f03b6359e0044cccfc64a5962d | |
| parent | 4974ffe4a4e3fd2c907fc00e258ae60a33869f22 (diff) | |
| download | linux-rpi3-2ac76646b3af0ce080f3c3797108411ee40b5471.tar.gz linux-rpi3-2ac76646b3af0ce080f3c3797108411ee40b5471.tar.bz2 linux-rpi3-2ac76646b3af0ce080f3c3797108411ee40b5471.zip | |
drm/vc4: Fix DSI T_INIT timing.
The DPHY spec requires a much larger T_INIT than I was specifying
before. In the absence of clear specs from the slave of what their
timing is, just use the value that the firmware was using.
Signed-off-by: Eric Anholt <eric@anholt.net>
Link: http://patchwork.freedesktop.org/patch/msgid/20170627195839.3338-2-eric@anholt.net
Reviewed-by: Andrzej Hajda <a.hajda@samsung.com>
(cherry picked from commit e65d51126f89a0d67ee6c5df58363730b1410ab5)
[inki.dae: apply from rpi3-4.9.y]
Signed-off-by: Inki Dae <inki.dae@samsung.com>
Change-Id: Ice356806cba9d0bb5a786e58d8835f79527d404a
| -rw-r--r-- | drivers/gpu/drm/vc4/vc4_dsi.c | 12 |
1 files changed, 11 insertions, 1 deletions
diff --git a/drivers/gpu/drm/vc4/vc4_dsi.c b/drivers/gpu/drm/vc4/vc4_dsi.c index 284f486ed9db..5dcd03724c4a 100644 --- a/drivers/gpu/drm/vc4/vc4_dsi.c +++ b/drivers/gpu/drm/vc4/vc4_dsi.c @@ -1102,7 +1102,17 @@ static void vc4_dsi_encoder_enable(struct drm_encoder *encoder) DSI_HS_DLT4_TRAIL) | VC4_SET_FIELD(0, DSI_HS_DLT4_ANLAT)); - DSI_PORT_WRITE(HS_DLT5, VC4_SET_FIELD(dsi_hs_timing(ui_ns, 1000, 5000), + /* T_INIT is how long STOP is driven after power-up to + * indicate to the slave (also coming out of power-up) that + * master init is complete, and should be greater than the + * maximum of two value: T_INIT,MASTER and T_INIT,SLAVE. The + * D-PHY spec gives a minimum 100us for T_INIT,MASTER and + * T_INIT,SLAVE, while allowing protocols on top of it to give + * greater minimums. The vc4 firmware uses an extremely + * conservative 5ms, and we maintain that here. + */ + DSI_PORT_WRITE(HS_DLT5, VC4_SET_FIELD(dsi_hs_timing(ui_ns, + 5 * 1000 * 1000, 0), DSI_HS_DLT5_INIT)); DSI_PORT_WRITE(HS_DLT6, |