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| author | Olof Johansson <olof@lixom.net> | 2018-06-23 10:17:38 -0700 |
|---|---|---|
| committer | Olof Johansson <olof@lixom.net> | 2018-06-23 10:17:38 -0700 |
| commit | 652caf4ab1e6ab9106c62a7b3b411cd67b72902f (patch) | |
| tree | 5d15e5fc477d9a4c062a696cf0ecac8e2ee9ac1e /drivers/soc | |
| parent | cb04a7944505a0d4c8097ca7279555a8ce35000f (diff) | |
| parent | 1bcfe0564044be578841744faea1c2f46adc8178 (diff) | |
| download | linux-rpi-652caf4ab1e6ab9106c62a7b3b411cd67b72902f.tar.gz linux-rpi-652caf4ab1e6ab9106c62a7b3b411cd67b72902f.tar.bz2 linux-rpi-652caf4ab1e6ab9106c62a7b3b411cd67b72902f.zip | |
Merge tag 'imx-fixes-4.18' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into fixes
i.MX fixes for 4.18:
- Fix i.MX6SX PCIe MSI interrupt number, so that MSI IRQs can be
properly propagated to the upstream interrupt controller.
- Fix GPCv2 MIPI/PCIe/USB_HSIC's PGC offset. The values in Reference
Manual are incorrect.
- Correct SDMA setting for i.MX6Q SPI5 device to fix the issue, that
the SPI controller RX FIFO was not empty after a DMA transfer, and
the driver gets stuck in the next PIO transfer when reading one word
more than expected.
* tag 'imx-fixes-4.18' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
ARM: dts: imx6sx: fix irq for pcie bridge
soc: imx: gpcv2: correct PGC offset
ARM: dts: imx6q: Use correct SDMA script for SPI5 core
Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat (limited to 'drivers/soc')
| -rw-r--r-- | drivers/soc/imx/gpcv2.c | 13 |
1 files changed, 9 insertions, 4 deletions
diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c index f4e3bd40c72e..6ef18cf8f243 100644 --- a/drivers/soc/imx/gpcv2.c +++ b/drivers/soc/imx/gpcv2.c @@ -39,10 +39,15 @@ #define GPC_M4_PU_PDN_FLG 0x1bc - -#define PGC_MIPI 4 -#define PGC_PCIE 5 -#define PGC_USB_HSIC 8 +/* + * The PGC offset values in Reference Manual + * (Rev. 1, 01/2018 and the older ones) GPC chapter's + * GPC_PGC memory map are incorrect, below offset + * values are from design RTL. + */ +#define PGC_MIPI 16 +#define PGC_PCIE 17 +#define PGC_USB_HSIC 20 #define GPC_PGC_CTRL(n) (0x800 + (n) * 0x40) #define GPC_PGC_SR(n) (GPC_PGC_CTRL(n) + 0xc) |