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| author | Hannes Reinecke <hare@suse.de> | 2014-11-24 15:37:27 +0100 |
|---|---|---|
| committer | Christoph Hellwig <hch@lst.de> | 2014-11-24 16:13:16 +0100 |
| commit | eeea2f9c2f2ecc5f3217edcacc95817047b143c2 (patch) | |
| tree | 30ae59b8af6754aca843d83a334f040459f1a031 /drivers/scsi/esp_scsi.h | |
| parent | 6df388f2d549d3a2a7ad58b632d2ecd25fc0ff3f (diff) | |
| download | linux-rpi-eeea2f9c2f2ecc5f3217edcacc95817047b143c2.tar.gz linux-rpi-eeea2f9c2f2ecc5f3217edcacc95817047b143c2.tar.bz2 linux-rpi-eeea2f9c2f2ecc5f3217edcacc95817047b143c2.zip | |
esp_scsi: correctly detect am53c974
The am53c974 returns the same ID as the FAS236, but implements
things slightly differently. So detect the am53c974 by checking
for ESP_CONFIG4 register.
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Hannes Reinecke <hare@suse.de>
Signed-off-by: Christoph Hellwig <hch@lst.de>
Diffstat (limited to 'drivers/scsi/esp_scsi.h')
| -rw-r--r-- | drivers/scsi/esp_scsi.h | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/drivers/scsi/esp_scsi.h b/drivers/scsi/esp_scsi.h index 5fa456cc5e8b..84dcbe4a6268 100644 --- a/drivers/scsi/esp_scsi.h +++ b/drivers/scsi/esp_scsi.h @@ -25,6 +25,7 @@ #define ESP_CTEST 0x0aUL /* wo Chip test register 0x28 */ #define ESP_CFG2 0x0bUL /* rw Second cfg register 0x2c */ #define ESP_CFG3 0x0cUL /* rw Third cfg register 0x30 */ +#define ESP_CFG4 0x0dUL /* rw Fourth cfg register 0x34 */ #define ESP_TCHI 0x0eUL /* rw High bits transf count 0x38 */ #define ESP_UID ESP_TCHI /* ro Unique ID code 0x38 */ #define FAS_RLO ESP_TCHI /* rw HME extended counter 0x38 */ @@ -76,6 +77,18 @@ #define ESP_CONFIG3_IMS 0x80 /* ID msg chk'ng (esp/fas236) */ #define ESP_CONFIG3_OBPUSH 0x80 /* Push odd-byte to dma (hme) */ +/* ESP config register 4 read-write, found only on am53c974 chips */ +#define ESP_CONFIG4_RADE 0x04 /* Active negation */ +#define ESP_CONFIG4_RAE 0x08 /* Active negation on REQ and ACK */ +#define ESP_CONFIG4_PWD 0x20 /* Reduced power feature */ +#define ESP_CONFIG4_GE0 0x40 /* Glitch eater bit 0 */ +#define ESP_CONFIG4_GE1 0x80 /* Glitch eater bit 1 */ + +#define ESP_CONFIG_GE_12NS (0) +#define ESP_CONFIG_GE_25NS (ESP_CONFIG_GE1) +#define ESP_CONFIG_GE_35NS (ESP_CONFIG_GE0) +#define ESP_CONFIG_GE_0NS (ESP_CONFIG_GE0 | ESP_CONFIG_GE1) + /* ESP command register read-write */ /* Group 1 commands: These may be sent at any point in time to the ESP * chip. None of them can generate interrupts 'cept @@ -254,6 +267,7 @@ enum esp_rev { FAS100A = 0x04, FAST = 0x05, FASHME = 0x06, + PCSCSI = 0x07, /* AM53c974 */ }; struct esp_cmd_entry { @@ -466,6 +480,7 @@ struct esp { u8 bursts; u8 config1; u8 config2; + u8 config4; u8 scsi_id; u32 scsi_id_mask; |