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| author | H Hartley Sweeten <hartleys@visionengravers.com> | 2011-09-19 18:51:39 -0700 |
|---|---|---|
| committer | Mark Brown <broonie@opensource.wolfsonmicro.com> | 2011-10-09 12:05:27 +0100 |
| commit | e3efe6669bf9c3cbd955b5a2976c70d79e8fd745 (patch) | |
| tree | 9e99e9b654cb5887fe0aa3f055dff0fb0b175fed /drivers/regulator/tps65023-regulator.c | |
| parent | c3035a232e87f42b81d8ece1980abd0a2f26d792 (diff) | |
| download | linux-rpi-e3efe6669bf9c3cbd955b5a2976c70d79e8fd745.tar.gz linux-rpi-e3efe6669bf9c3cbd955b5a2976c70d79e8fd745.tar.bz2 linux-rpi-e3efe6669bf9c3cbd955b5a2976c70d79e8fd745.zip | |
regulator: remove duplicate REG_CTRL2 defines in tps65023
There are two sets of defines for the REG_CTRL2 bitfields and one
of them has TPS65023_REG_CTRL2_DCDC1 defined incorrectly. Remove
the duplicates and leave the correct one for TPS65023_REG_CTRL2_DCDC1.
This fixes the following sparse warnings:
drivers/regulator/tps65023-regulator.c:77:9: warning: preprocessor token TPS65023_REG_CTRL2_DCDC1 redefined
drivers/regulator/tps65023-regulator.c:70:9: this was the original definition
Signed-off-by: H Hartley Sweeten <hsweeten@visionengravers.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Diffstat (limited to 'drivers/regulator/tps65023-regulator.c')
| -rw-r--r-- | drivers/regulator/tps65023-regulator.c | 7 |
1 files changed, 0 insertions, 7 deletions
diff --git a/drivers/regulator/tps65023-regulator.c b/drivers/regulator/tps65023-regulator.c index b02c67086353..9fb4c7b81753 100644 --- a/drivers/regulator/tps65023-regulator.c +++ b/drivers/regulator/tps65023-regulator.c @@ -67,13 +67,6 @@ #define TPS65023_REG_CTRL2_GO BIT(7) #define TPS65023_REG_CTRL2_CORE_ADJ BIT(6) #define TPS65023_REG_CTRL2_DCDC2 BIT(2) -#define TPS65023_REG_CTRL2_DCDC1 BIT(2) -#define TPS65023_REG_CTRL2_DCDC3 BIT(0) - -/* REG_CTRL2 bitfields */ -#define TPS65023_REG_CTRL2_GO BIT(7) -#define TPS65023_REG_CTRL2_CORE_ADJ BIT(6) -#define TPS65023_REG_CTRL2_DCDC2 BIT(2) #define TPS65023_REG_CTRL2_DCDC1 BIT(1) #define TPS65023_REG_CTRL2_DCDC3 BIT(0) |