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| author | Dan Williams <dan.j.williams@intel.com> | 2022-01-23 16:29:42 -0800 |
|---|---|---|
| committer | Dan Williams <dan.j.williams@intel.com> | 2022-02-08 22:57:28 -0800 |
| commit | d621bc2e7282f9955033a6359877fd4ac4be60e1 (patch) | |
| tree | bc19c02cb9b3e0327c8fa3ae459334bd06381625 /drivers/cxl | |
| parent | d54c1bbe2d34e301382968d8b05bd8162e8f60fb (diff) | |
| download | linux-rpi-d621bc2e7282f9955033a6359877fd4ac4be60e1.tar.gz linux-rpi-d621bc2e7282f9955033a6359877fd4ac4be60e1.tar.bz2 linux-rpi-d621bc2e7282f9955033a6359877fd4ac4be60e1.zip | |
cxl/core: Fix cxl_probe_component_regs() error message
Fix a '\n' vs '/n' typo.
Fixes: 08422378c4ad ("cxl/pci: Add HDM decoder capabilities")
Acked-by: Ben Widawsky <ben.widawsky@intel.com
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Link: https://lore.kernel.org/r/164298418268.3018233.17790073375430834911.stgit@dwillia2-desk3.amr.corp.intel.com
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Diffstat (limited to 'drivers/cxl')
| -rw-r--r-- | drivers/cxl/core/regs.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/cxl/core/regs.c b/drivers/cxl/core/regs.c index 0d63758e2605..12a6cbddf110 100644 --- a/drivers/cxl/core/regs.c +++ b/drivers/cxl/core/regs.c @@ -50,7 +50,7 @@ void cxl_probe_component_regs(struct device *dev, void __iomem *base, if (FIELD_GET(CXL_CM_CAP_HDR_ID_MASK, cap_array) != CM_CAP_HDR_CAP_ID) { dev_err(dev, - "Couldn't locate the CXL.cache and CXL.mem capability array header./n"); + "Couldn't locate the CXL.cache and CXL.mem capability array header.\n"); return; } |