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| author | Martin Schwidefsky <schwidefsky@de.ibm.com> | 2015-03-01 06:56:45 -0800 |
|---|---|---|
| committer | Martin Schwidefsky <schwidefsky@de.ibm.com> | 2015-03-02 11:35:57 -0800 |
| commit | 691d5264158e58004904f285417fefaf8650ffe6 (patch) | |
| tree | 2a225e091af5d5ffb934ee4994db91ae0ad181aa /arch | |
| parent | a9ca8eb7afb4f1c90d8e43092e94c4e86785efbc (diff) | |
| download | linux-rpi-691d5264158e58004904f285417fefaf8650ffe6.tar.gz linux-rpi-691d5264158e58004904f285417fefaf8650ffe6.tar.bz2 linux-rpi-691d5264158e58004904f285417fefaf8650ffe6.zip | |
s390/mm: fix incorrect ASCE after crst_table_downgrade
The switch_mm function does nothing in case the prev and next mm
are the same. It can happen that a crst_table_downgrade has changed
the top-level pgd in the meantime on a different CPU. Always store
the new ASCE to be picked up in entry.S.
[heiko.carstens@de.ibm.com]: Bug was introduced with git commit
53e857f30867 ("s390/mm,tlb: race of lazy TLB flush vs. recreation
of TLB entries") and causes random crashes due to broken page tables
being used.
Reported-by: Dominik Vogt <vogt@linux.vnet.ibm.com>
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
Signed-off-by: Heiko Carstens <heiko.carstens@de.ibm.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/s390/include/asm/mmu_context.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/s390/include/asm/mmu_context.h b/arch/s390/include/asm/mmu_context.h index f49b71954654..8fb3802f8fad 100644 --- a/arch/s390/include/asm/mmu_context.h +++ b/arch/s390/include/asm/mmu_context.h @@ -62,6 +62,7 @@ static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next, { int cpu = smp_processor_id(); + S390_lowcore.user_asce = next->context.asce_bits | __pa(next->pgd); if (prev == next) return; if (MACHINE_HAS_TLB_LC) @@ -73,7 +74,6 @@ static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next, atomic_dec(&prev->context.attach_count); if (MACHINE_HAS_TLB_LC) cpumask_clear_cpu(cpu, &prev->context.cpu_attach_mask); - S390_lowcore.user_asce = next->context.asce_bits | __pa(next->pgd); } #define finish_arch_post_lock_switch finish_arch_post_lock_switch |