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| author | Dmitry Torokhov <dmitry.torokhov@gmail.com> | 2022-11-18 08:43:47 -0800 |
|---|---|---|
| committer | Thomas Bogendoerfer <tsbogend@alpha.franken.de> | 2022-11-21 17:56:19 +0100 |
| commit | ca637c0ece144ce62ec8ef75dc127bcccd4f442a (patch) | |
| tree | dd4e0f522e831e095130990622fc1732fead4d77 /arch/mips | |
| parent | 094226ad94f471a9f19e8f8e7140a09c2625abaa (diff) | |
| download | linux-rpi-ca637c0ece144ce62ec8ef75dc127bcccd4f442a.tar.gz linux-rpi-ca637c0ece144ce62ec8ef75dc127bcccd4f442a.tar.bz2 linux-rpi-ca637c0ece144ce62ec8ef75dc127bcccd4f442a.zip | |
MIPS: DTS: CI20: fix reset line polarity of the ethernet controller
The reset line is called PWRST#, annotated as "active low" in the
binding documentation, and is driven low and then high by the driver to
reset the chip. However in device tree for CI20 board it was incorrectly
marked as "active high". Fix it.
Because (as far as I know) the ci20.dts is always built in the kernel I
elected not to also add a quirk to gpiolib to force the polarity there.
Fixes: db49ca38579d ("net: davicom: dm9000: switch to using gpiod API")
Reported-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
Acked-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Diffstat (limited to 'arch/mips')
| -rw-r--r-- | arch/mips/boot/dts/ingenic/ci20.dts | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/mips/boot/dts/ingenic/ci20.dts b/arch/mips/boot/dts/ingenic/ci20.dts index 37c46720c719..f38c39572a9e 100644 --- a/arch/mips/boot/dts/ingenic/ci20.dts +++ b/arch/mips/boot/dts/ingenic/ci20.dts @@ -438,7 +438,7 @@ ingenic,nemc-tAW = <50>; ingenic,nemc-tSTRV = <100>; - reset-gpios = <&gpf 12 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpf 12 GPIO_ACTIVE_LOW>; vcc-supply = <ð0_power>; interrupt-parent = <&gpe>; |