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| author | Michal Wilczynski <m.wilczynski@samsung.com> | 2024-08-22 10:55:13 +0200 |
|---|---|---|
| committer | Michal Wilczynski <m.wilczynski@samsung.com> | 2024-08-22 13:53:59 +0200 |
| commit | 9375ed2f8b2a370e557d89c6dbd3f3ee597cd7a0 (patch) | |
| tree | 2c6c65af25e8660247480d12b67045ca2440ff4b | |
| parent | 333d6c739b8a7777e1056771aa6d3ddd2f8c04da (diff) | |
| download | linux-riscv-9375ed2f8b2a370e557d89c6dbd3f3ee597cd7a0.tar.gz linux-riscv-9375ed2f8b2a370e557d89c6dbd3f3ee597cd7a0.tar.bz2 linux-riscv-9375ed2f8b2a370e557d89c6dbd3f3ee597cd7a0.zip | |
riscv: dts: spacemit: Add separate dtsi with pinctrl configuration
In the vendor kernel there is a separate file with pinctrl
configurations. Port it [1].
[1] - https://github.com/BPI-SINOVOIP/pi-linux.git
Change-Id: I83fadfb582a2fb47f24c91469ca857b6408a42ae
Signed-off-by: Michal Wilczynski <m.wilczynski@samsung.com>
| -rw-r--r-- | arch/riscv/boot/dts/spacemit/k1-x_pinctrl.dtsi | 1151 |
1 files changed, 1151 insertions, 0 deletions
diff --git a/arch/riscv/boot/dts/spacemit/k1-x_pinctrl.dtsi b/arch/riscv/boot/dts/spacemit/k1-x_pinctrl.dtsi new file mode 100644 index 000000000000..f736975f963a --- /dev/null +++ b/arch/riscv/boot/dts/spacemit/k1-x_pinctrl.dtsi @@ -0,0 +1,1151 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* Copyright (c) 2022 Spacemit, Inc */ + +#include <dt-bindings/pinctrl/k1-x-pinctrl.h> +/* Pin Configuration Node: */ +/* Format: <pin_id muxsel edge/st/ds/pull> */ +&pinctrl { + pinctrl_uart0_0: uart0_0_grp { + pinctrl-single,pins = < + K1X_PADCONF(MMC1_DAT3, MUX_MODE3, (EDGE_NONE | PULL_UP | PAD_3V_DS4)) /* uart0_txd */ + K1X_PADCONF(MMC1_DAT2, MUX_MODE3, (EDGE_NONE | PULL_UP | PAD_3V_DS4)) /* uart0_rxd */ + >; + }; + + pinctrl_uart0_1: uart0_1_grp { + pinctrl-single,pins = < + K1X_PADCONF(MMC1_CMD, MUX_MODE1, (EDGE_NONE | PULL_UP | PAD_3V_DS4)) /* uart0_txd */ + K1X_PADCONF(GPIO_80, MUX_MODE3, (EDGE_NONE | PULL_DOWN | PAD_3V_DS4)) /* uart0_rxd */ + >; + }; + + pinctrl_uart0_2: uart0_2_grp { + pinctrl-single,pins = < + K1X_PADCONF(GPIO_68, MUX_MODE2, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* uart0_txd */ + K1X_PADCONF(GPIO_69, MUX_MODE2, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* uart0_rxd */ + >; + }; + + pinctrl_uart2: uart2_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_21, MUX_MODE1, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS0)) /* uart2_txd */ + K1X_PADCONF(GPIO_22, MUX_MODE1, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS0)) /* uart2_rxd */ + K1X_PADCONF(GPIO_23, MUX_MODE1, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS0)) /* uart2_cts_n */ + K1X_PADCONF(GPIO_24, MUX_MODE1, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS0)) /* uart2_rts_n */ + >; + }; + + pinctrl_uart3_0: uart3_0_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_81, MUX_MODE2, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* uart3_txd */ + K1X_PADCONF(GPIO_82, MUX_MODE2, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* uart3_rxd */ + K1X_PADCONF(GPIO_83, MUX_MODE2, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* uart3_cts_n */ + K1X_PADCONF(GPIO_84, MUX_MODE2, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* uart3_rts_n */ + >; + }; + + pinctrl_uart3_1: uart3_1_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_18, MUX_MODE2, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* uart3_txd */ + K1X_PADCONF(GPIO_19, MUX_MODE2, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* uart3_rxd */ + K1X_PADCONF(GPIO_20, MUX_MODE2, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* uart3_cts_n */ + K1X_PADCONF(GPIO_21, MUX_MODE2, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* uart3_rts_n */ + >; + }; + + pinctrl_uart3_2: uart3_2_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_53, MUX_MODE4, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* uart3_txd */ + K1X_PADCONF(GPIO_54, MUX_MODE4, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* uart3_rxd */ + K1X_PADCONF(GPIO_55, MUX_MODE4, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* uart3_cts_n */ + K1X_PADCONF(GPIO_56, MUX_MODE4, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* uart3_rts_n */ + >; + }; + + pinctrl_uart4_0: uart4_0_grp { + pinctrl-single,pins = < + K1X_PADCONF(QSPI_DAT1, MUX_MODE4, (EDGE_NONE | PULL_DOWN | PAD_3V_DS4)) /* uart4_txd */ + K1X_PADCONF(QSPI_DAT0, MUX_MODE4, (EDGE_NONE | PULL_DOWN | PAD_3V_DS4)) /* uart4_rxd */ + >; + }; + + pinctrl_uart4_1: uart4_1_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_81, MUX_MODE3, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* uart4_cts_n */ + K1X_PADCONF(GPIO_82, MUX_MODE3, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* uart4_rts_n */ + K1X_PADCONF(GPIO_83, MUX_MODE3, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* uart4_txd */ + K1X_PADCONF(GPIO_84, MUX_MODE3, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* uart4_rxd */ + >; + }; + + pinctrl_uart4_2: uart4_2_grp { + pinctrl-single,pins = < + K1X_PADCONF(GPIO_23, MUX_MODE2, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* uart4_txd */ + K1X_PADCONF(GPIO_24, MUX_MODE2, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* uart4_rxd */ + >; + }; + + pinctrl_uart4_3: uart4_3_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_33, MUX_MODE2, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* uart4_txd */ + K1X_PADCONF(GPIO_34, MUX_MODE2, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* uart4_rxd */ + K1X_PADCONF(GPIO_35, MUX_MODE2, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* uart4_cts_n */ + K1X_PADCONF(GPIO_36, MUX_MODE2, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* uart4_rts_n */ + >; + }; + + pinctrl_uart4_4: uart4_4_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_111, MUX_MODE4, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* uart4_txd */ + K1X_PADCONF(GPIO_112, MUX_MODE4, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* uart4_rxd */ + K1X_PADCONF(GPIO_113, MUX_MODE4, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* uart4_cts_n */ + K1X_PADCONF(GPIO_114, MUX_MODE4, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* uart4_rts_n */ + >; + }; + + pinctrl_uart5_0: uart5_0_grp { + pinctrl-single,pins = < + K1X_PADCONF(QSPI_CLK, MUX_MODE3, (EDGE_NONE | PULL_DOWN | PAD_3V_DS4)) /* uart5_txd */ + K1X_PADCONF(QSPI_CSI, MUX_MODE3, (EDGE_NONE | PULL_DOWN | PAD_3V_DS4)) /* uart5_rxd */ + >; + }; + + pinctrl_uart5_1: uart5_1_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_25, MUX_MODE2, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* uart5_txd */ + K1X_PADCONF(GPIO_26, MUX_MODE2, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* uart5_rxd */ + K1X_PADCONF(GPIO_27, MUX_MODE2, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* uart5_cts_n */ + K1X_PADCONF(GPIO_28, MUX_MODE2, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* uart5_rts_n */ + >; + }; + + pinctrl_uart5_2: uart5_2_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_42, MUX_MODE2, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* uart5_txd */ + K1X_PADCONF(GPIO_43, MUX_MODE2, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* uart5_rxd */ + K1X_PADCONF(GPIO_44, MUX_MODE2, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* uart5_cts_n */ + K1X_PADCONF(GPIO_45, MUX_MODE2, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* uart5_rts_n */ + >; + }; + + pinctrl_uart5_3: uart5_3_grp { + pinctrl-single,pins =< + K1X_PADCONF(PRI_TDI, MUX_MODE4, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* uart5_txd */ + K1X_PADCONF(PRI_TMS, MUX_MODE4, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* uart5_rxd */ + K1X_PADCONF(PRI_TCK, MUX_MODE4, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* uart5_cts_n */ + K1X_PADCONF(PRI_TDO, MUX_MODE4, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* uart5_rts_n */ + >; + }; + + pinctrl_uart6_0: uart6_0_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_85, MUX_MODE2, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* uart6_cts_n */ + K1X_PADCONF(GPIO_86, MUX_MODE2, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* uart6_txd */ + K1X_PADCONF(GPIO_87, MUX_MODE2, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* uart6_rxd */ + K1X_PADCONF(GPIO_90, MUX_MODE2, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* uart6_rts_n */ + >; + }; + + pinctrl_uart6_1: uart6_1_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_00, MUX_MODE2, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* uart6_txd */ + K1X_PADCONF(GPIO_01, MUX_MODE2, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* uart6_rxd */ + K1X_PADCONF(GPIO_02, MUX_MODE2, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* uart6_cts_n */ + K1X_PADCONF(GPIO_03, MUX_MODE2, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* uart6_rts_n */ + >; + }; + + pinctrl_uart6_2: uart6_2_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_56, MUX_MODE2, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* uart6_txd */ + K1X_PADCONF(GPIO_57, MUX_MODE2, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* uart6_rxd */ + >; + }; + + pinctrl_uart7_0: uart7_0_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_88, MUX_MODE2, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* uart7_txd */ + K1X_PADCONF(GPIO_89, MUX_MODE2, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* uart7_rxd */ + >; + }; + + pinctrl_uart7_1: uart7_1_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_04, MUX_MODE2, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* uart7_txd */ + K1X_PADCONF(GPIO_05, MUX_MODE2, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* uart7_rxd */ + K1X_PADCONF(GPIO_06, MUX_MODE2, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* uart7_cts_n */ + K1X_PADCONF(GPIO_07, MUX_MODE2, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* uart7_rts_n */ + >; + }; + + pinctrl_uart8_0: uart8_0_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_82, MUX_MODE4, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* uart8_txd */ + K1X_PADCONF(GPIO_83, MUX_MODE4, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* uart8_rxd */ + >; + }; + + pinctrl_uart8_1: uart8_1_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_08, MUX_MODE2, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* uart8_txd */ + K1X_PADCONF(GPIO_09, MUX_MODE2, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* uart8_rxd */ + K1X_PADCONF(GPIO_10, MUX_MODE2, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* uart8_cts_n */ + K1X_PADCONF(GPIO_11, MUX_MODE2, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* uart8_rts_n */ + >; + }; + + pinctrl_uart8_2: uart8_2_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_75, MUX_MODE4, (EDGE_NONE | PULL_UP | PAD_3V_DS4)) /* uart8_txd */ + K1X_PADCONF(GPIO_76, MUX_MODE4, (EDGE_NONE | PULL_UP | PAD_3V_DS4)) /* uart8_rxd */ + K1X_PADCONF(GPIO_77, MUX_MODE4, (EDGE_NONE | PULL_UP | PAD_3V_DS4)) /* uart8_cts_n */ + K1X_PADCONF(GPIO_78, MUX_MODE4, (EDGE_NONE | PULL_UP | PAD_3V_DS4)) /* uart8_rts_n */ + >; + }; + + pinctrl_uart9_0: uart9_0_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_12, MUX_MODE2, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* uart9_txd */ + K1X_PADCONF(GPIO_13, MUX_MODE2, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* uart9_rxd */ + >; + }; + + pinctrl_uart9_1: uart9_1_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_110, MUX_MODE3, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* uart9_cts_n */ + K1X_PADCONF(GPIO_115, MUX_MODE3, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* uart9_rts_n */ + K1X_PADCONF(GPIO_116, MUX_MODE3, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* uart9_txd */ + K1X_PADCONF(GPIO_117, MUX_MODE3, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* uart9_rxd */ + >; + }; + + pinctrl_uart9_2: uart9_2_grp { + pinctrl-single,pins =< + K1X_PADCONF(PRI_TCK, MUX_MODE2, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* uart9_txd */ + K1X_PADCONF(PRI_TDO, MUX_MODE2, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* uart9_rxd */ + >; + }; + + pinctrl_i2c0: i2c0_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_54, MUX_MODE1, (EDGE_NONE | PULL_UP | PAD_1V8_DS0)) /* i2c0_scl */ + K1X_PADCONF(GPIO_55, MUX_MODE1, (EDGE_NONE | PULL_UP | PAD_1V8_DS0)) /* i2c0_sda */ + >; + }; + + pinctrl_i2c1: i2c1_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_56, MUX_MODE1, (EDGE_NONE | PULL_UP | PAD_1V8_DS0)) /* i2c1_scl */ + K1X_PADCONF(GPIO_57, MUX_MODE1, (EDGE_NONE | PULL_UP | PAD_1V8_DS0)) /* i2c1_sda */ + >; + }; + + pinctrl_i2c2_0: i2c2_0_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_84, MUX_MODE4, (EDGE_NONE | PULL_UP | PAD_1V8_DS0)) /* i2c2_scl */ + K1X_PADCONF(GPIO_85, MUX_MODE4, (EDGE_NONE | PULL_UP | PAD_1V8_DS0)) /* i2c2_sda */ + >; + }; + + pinctrl_i2c2_1: i2c2_1_grp { + pinctrl-single,pins =< + K1X_PADCONF(PRI_TDI, MUX_MODE2, (EDGE_NONE | PULL_UP | PAD_1V8_DS0)) /* i2c2_scl */ + K1X_PADCONF(PRI_TMS, MUX_MODE2, (EDGE_NONE | PULL_UP | PAD_1V8_DS0)) /* i2c2_sda */ + >; + }; + + pinctrl_i2c2_2: i2c2_2_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_68, MUX_MODE3, (EDGE_NONE | PULL_UP | PAD_1V8_DS0)) /* i2c2_scl */ + K1X_PADCONF(GPIO_69, MUX_MODE3, (EDGE_NONE | PULL_UP | PAD_1V8_DS0)) /* i2c2_sda */ + >; + }; + + pinctrl_i2c3_0: i2c3_0_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_38, MUX_MODE2, (EDGE_NONE | PULL_UP | PAD_1V8_DS0)) /* i2c3_scl */ + K1X_PADCONF(GPIO_39, MUX_MODE2, (EDGE_NONE | PULL_UP | PAD_1V8_DS0)) /* i2c3_sda */ + >; + }; + + pinctrl_i2c3_1: i2c3_1_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_47, MUX_MODE4, (EDGE_NONE | PULL_UP | PAD_1V8_DS0)) /* i2c3_scl */ + K1X_PADCONF(GPIO_48, MUX_MODE4, (EDGE_NONE | PULL_UP | PAD_1V8_DS0)) /* i2c3_sda */ + >; + }; + + pinctrl_i2c3_2: i2c3_2_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_77, MUX_MODE3, (EDGE_NONE | PULL_UP | PAD_1V8_DS0)) /* i2c3_scl */ + K1X_PADCONF(GPIO_78, MUX_MODE3, (EDGE_NONE | PULL_UP | PAD_1V8_DS0)) /* i2c3_sda */ + >; + }; + + pinctrl_i2c4_0: i2c4_0_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_40, MUX_MODE2, (EDGE_NONE | PULL_UP | PAD_1V8_DS0)) /* i2c4_scl */ + K1X_PADCONF(GPIO_41, MUX_MODE2, (EDGE_NONE | PULL_UP | PAD_1V8_DS0)) /* i2c4_sda */ + >; + }; + + pinctrl_i2c4_1: i2c4_1_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_75, MUX_MODE5, (EDGE_NONE | PULL_UP | PAD_3V_DS0)) /* i2c4_scl */ + K1X_PADCONF(GPIO_76, MUX_MODE5, (EDGE_NONE | PULL_UP | PAD_3V_DS0)) /* i2c4_sda */ + >; + }; + + pinctrl_i2c4_2: i2c4_2_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_51, MUX_MODE4, (EDGE_NONE | PULL_UP | PAD_3V_DS0)) /* i2c4_scl */ + K1X_PADCONF(GPIO_52, MUX_MODE4, (EDGE_NONE | PULL_UP | PAD_3V_DS0)) /* i2c4_sda */ + >; + }; + + pinctrl_i2c5_0: i2c5_0_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_81, MUX_MODE5, (EDGE_NONE | PULL_UP | PAD_1V8_DS0)) /* i2c5_scl */ + K1X_PADCONF(GPIO_82, MUX_MODE5, (EDGE_NONE | PULL_UP | PAD_1V8_DS0)) /* i2c5_sda */ + >; + }; + + pinctrl_i2c5_1: i2c5_1_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_54, MUX_MODE5, (EDGE_NONE | PULL_UP | PAD_1V8_DS0)) /* i2c5_scl */ + K1X_PADCONF(GPIO_55, MUX_MODE5, (EDGE_NONE | PULL_UP | PAD_1V8_DS0)) /* i2c5_sda */ + >; + }; + + pinctrl_i2c6_0: i2c6_0_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_83, MUX_MODE5, (EDGE_NONE | PULL_UP | PAD_1V8_DS0)) /* i2c6_scl */ + K1X_PADCONF(GPIO_90, MUX_MODE5, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS0)) /* i2c6_sda */ + >; + }; + + pinctrl_i2c6_1: i2c6_1_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_118, MUX_MODE2, (EDGE_NONE | PULL_UP | PAD_1V8_DS0)) /* i2c6_scl */ + K1X_PADCONF(GPIO_119, MUX_MODE2, (EDGE_NONE | PULL_UP | PAD_1V8_DS0)) /* i2c6_sda */ + >; + }; + + pinctrl_i2c6_2: i2c6_2_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_56, MUX_MODE5, (EDGE_NONE | PULL_UP | PAD_1V8_DS0)) /* i2c6_scl */ + K1X_PADCONF(GPIO_57, MUX_MODE5, (EDGE_NONE | PULL_UP | PAD_1V8_DS0)) /* i2c6_sda */ + >; + }; + + pinctrl_i2c7: i2c7_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_118, MUX_MODE1, (EDGE_NONE | PULL_UP | PAD_1V8_DS0)) /* i2c6_scl */ + K1X_PADCONF(GPIO_119, MUX_MODE1, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS0)) /* i2c6_sda */ + >; + }; + + pinctrl_i2c8: i2c8_grp { + pinctrl-single,pins =< + K1X_PADCONF(PWR_SCL, MUX_MODE0, (EDGE_NONE | PULL_UP | PAD_1V8_DS0)) /* pwr_scl */ + K1X_PADCONF(PWR_SDA, MUX_MODE0, (EDGE_NONE | PULL_UP | PAD_1V8_DS0)) /* pwr_sda */ + >; + }; + + pinctrl_one_wire_0: one_wire_0_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_110, MUX_MODE5, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* one_wire */ + >; + }; + + pinctrl_one_wire_1: one_wire_1_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_47, MUX_MODE5, (EDGE_NONE | PULL_DOWN | PAD_3V_DS4)) /* one_wire */ + >; + }; + + pinctrl_ir_rx_0: ir_rx_0_grp { + pinctrl-single,pins = < + K1X_PADCONF(DVL1, MUX_MODE2, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* ir_rx */ + >; + }; + + pinctrl_ir_rx_1: ir_rx_1_grp { + pinctrl-single,pins = < + K1X_PADCONF(GPIO_79, MUX_MODE1, (EDGE_NONE | PULL_DOWN | PAD_3V_DS4)) /* ir_rx */ + >; + }; + + pinctrl_ir_rx_2: ir_rx_2_grp { + pinctrl-single,pins = < + K1X_PADCONF(GPIO_58, MUX_MODE4, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* ir_rx */ + >; + }; + + pinctrl_pwm0_0: pwm0_0_grp { + pinctrl-single,pins = < + K1X_PADCONF(MMC1_DAT3, MUX_MODE5, (EDGE_NONE | PULL_UP | PAD_3V_DS4)) /* pwm0 */ + >; + }; + + pinctrl_pwm0_1: pwm0_1_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_14, MUX_MODE3, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* pwm0 */ + >; + }; + + pinctrl_pwm0_2: pwm0_2_grp { + pinctrl-single,pins = < + K1X_PADCONF(GPIO_22, MUX_MODE4, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* pwm0 */ + >; + }; + + pinctrl_pwm1_0: pwm1_0_grp { + pinctrl-single,pins = < + K1X_PADCONF(MMC1_DAT2, MUX_MODE5, (EDGE_NONE | PULL_UP | PAD_3V_DS4)) /* pwm1 */ + >; + }; + + pinctrl_pwm1_1: pwm1_1_grp { + pinctrl-single,pins = < + K1X_PADCONF(GPIO_29, MUX_MODE3, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* pwm1 */ + >; + }; + + pinctrl_pwm1_2: pwm1_2_grp { + pinctrl-single,pins = < + K1X_PADCONF(GPIO_23, MUX_MODE4, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* pwm1 */ + >; + }; + + pinctrl_pwm2_0: pwm2_0_grp { + pinctrl-single,pins = < + K1X_PADCONF(MMC1_DAT1, MUX_MODE5, (EDGE_NONE | PULL_UP | PAD_3V_DS4)) /* pwm2 */ + >; + }; + + pinctrl_pwm2_1: pwm2_1_grp { + pinctrl-single,pins = < + K1X_PADCONF(GPIO_22, MUX_MODE2, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* pwm2 */ + >; + }; + + pinctrl_pwm2_2: pwm2_2_grp { + pinctrl-single,pins = < + K1X_PADCONF(GPIO_30, MUX_MODE3, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* pwm2 */ + >; + }; + + pinctrl_pwm2_3: pwm2_3_grp { + pinctrl-single,pins = < + K1X_PADCONF(GPIO_24, MUX_MODE4, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* pwm2 */ + >; + }; + + pinctrl_pwm3_0: pwm3_0_grp { + pinctrl-single,pins = < + K1X_PADCONF(MMC1_DAT0, MUX_MODE5, (EDGE_NONE | PULL_UP | PAD_3V_DS4)) /* pwm3 */ + >; + }; + + pinctrl_pwm3_1: pwm3_1_grp { + pinctrl-single,pins = < + K1X_PADCONF(GPIO_33, MUX_MODE3, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* pwm3 */ + >; + }; + + pinctrl_pwm3_2: pwm3_2_grp { + pinctrl-single,pins = < + K1X_PADCONF(GPIO_25, MUX_MODE4, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* pwm3 */ + >; + }; + + pinctrl_pwm4_0: pwm4_0_grp { + pinctrl-single,pins = < + K1X_PADCONF(MMC1_CMD, MUX_MODE5, (EDGE_NONE | PULL_UP | PAD_3V_DS4)) /* pwm4 */ + >; + }; + + pinctrl_pwm4_1: pwm4_1_grp { + pinctrl-single,pins = < + K1X_PADCONF(GPIO_34, MUX_MODE3, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* pwm4 */ + >; + }; + + pinctrl_pwm5_0: pwm5_0_grp { + pinctrl-single,pins = < + K1X_PADCONF(MMC1_CLK, MUX_MODE5, (EDGE_NONE | PULL_UP | PAD_3V_DS4)) /* pwm5 */ + >; + }; + + pinctrl_pwm5_1: pwm5_1_grp { + pinctrl-single,pins = < + K1X_PADCONF(GPIO_35, MUX_MODE3, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* pwm5 */ + >; + }; + + pinctrl_pwm6_0: pwm6_0_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_88, MUX_MODE4, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* pwm6 */ + >; + }; + + pinctrl_pwm6_1: pwm6_1_grp { + pinctrl-single,pins = < + K1X_PADCONF(GPIO_36, MUX_MODE3, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* pwm6 */ + >; + }; + + pinctrl_pwm7_0: pwm7_0_grp { + pinctrl-single,pins = < + K1X_PADCONF(GPIO_92, MUX_MODE2, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* pwm7 */ + >; + }; + + pinctrl_pwm7_1: pwm7_1_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_37, MUX_MODE2, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* pwm7 */ + >; + }; + + pinctrl_pwm8_0: pwm8_0_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_00, MUX_MODE3, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* pwm8 */ + >; + }; + + pinctrl_pwm8_1: pwm8_1_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_38, MUX_MODE4, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* pwm8 */ + >; + }; + + pinctrl_pwm9_0: pwm9_0_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_01, MUX_MODE3, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* pwm9 */ + >; + }; + + pinctrl_pwm9_1: pwm9_1_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_39, MUX_MODE4, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* pwm9 */ + >; + }; + + pinctrl_pwm9_2: pwm9_2_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_74, MUX_MODE2, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* pwm9 */ + >; + }; + + pinctrl_pwm10_0: pwm10_0_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_02, MUX_MODE3, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* pwm10 */ + >; + }; + + pinctrl_pwm10_1: pwm10_1_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_40, MUX_MODE4, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* pwm10 */ + >; + }; + + pinctrl_pwm11_0: pwm11_0_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_03, MUX_MODE3, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* pwm11 */ + >; + }; + + pinctrl_pwm11_1: pwm11_1_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_41, MUX_MODE4, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* pwm11 */ + >; + }; + + pinctrl_pwm12_0: pwm12_0_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_04, MUX_MODE3, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* pwm12 */ + >; + }; + + pinctrl_pwm12_1: pwm12_1_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_42, MUX_MODE4, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* pwm12 */ + >; + }; + + pinctrl_pwm13_0: pwm13_0_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_05, MUX_MODE3, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* pwm13 */ + >; + }; + + pinctrl_pwm13_1: pwm13_1_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_43, MUX_MODE4, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* pwm13 */ + >; + }; + + pinctrl_pwm14_0: pwm14_0_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_06, MUX_MODE3, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* pwm14 */ + >; + }; + + pinctrl_pwm14_1: pwm14_1_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_44, MUX_MODE4, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* pwm14 */ + >; + }; + + pinctrl_pwm15_0: pwm15_0_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_07, MUX_MODE3, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* pwm15 */ + >; + }; + + pinctrl_pwm15_1: pwm15_1_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_45, MUX_MODE4, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* pwm15 */ + >; + }; + + pinctrl_pwm16_0: pwm16_0_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_09, MUX_MODE3, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* pwm16 */ + >; + }; + + pinctrl_pwm16_1: pwm16_1_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_46, MUX_MODE4, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* pwm16 */ + >; + }; + + pinctrl_pwm17_0: pwm17_0_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_10, MUX_MODE3, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* pwm17 */ + >; + }; + + pinctrl_pwm17_1: pwm17_1_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_53, MUX_MODE2, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* pwm17 */ + >; + }; + + pinctrl_pwm18_0: pwm18_0_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_11, MUX_MODE3, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* pwm18 */ + >; + }; + + pinctrl_pwm18_1: pwm18_1_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_57, MUX_MODE4, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* pwm18 */ + >; + }; + + pinctrl_pwm19_0: pwm19_0_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_13, MUX_MODE3, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* pwm19 */ + >; + }; + + pinctrl_pwm19_1: pwm19_1_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_63, MUX_MODE4, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* pwm19 */ + >; + }; + + pinctrl_sspa0_0: sspa0_0_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_118, MUX_MODE3, (EDGE_NONE | PULL_UP | PAD_1V8_DS0)) /* sspa0_clk */ + K1X_PADCONF(GPIO_119, MUX_MODE3, (EDGE_NONE | PULL_UP | PAD_1V8_DS0)) /* sspa0_frm */ + K1X_PADCONF(GPIO_120, MUX_MODE3, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS0)) /* sspa0_txd */ + K1X_PADCONF(GPIO_121, MUX_MODE3, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS0)) /* sspa0_rxd */ + K1X_PADCONF(GPIO_122, MUX_MODE3, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS0)) /* sspa0_sysclk */ + >; + }; + + pinctrl_sspa0_1: sspa0_1_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_58, MUX_MODE2, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS0)) /* sspa0_sysclk */ + K1X_PADCONF(GPIO_111, MUX_MODE2, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS0)) /* sspa0_clk */ + K1X_PADCONF(GPIO_112, MUX_MODE2, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS0)) /* sspa0_frm */ + K1X_PADCONF(GPIO_113, MUX_MODE2, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS0)) /* sspa0_txd */ + K1X_PADCONF(GPIO_114, MUX_MODE2, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS0)) /* sspa0_rxd */ + >; + }; + + pinctrl_sspa1: sspa1_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_24, MUX_MODE3, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS0)) /* sspa1_sysclk */ + K1X_PADCONF(GPIO_25, MUX_MODE1, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS0)) /* sspa1_sclk */ + K1X_PADCONF(GPIO_26, MUX_MODE1, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS0)) /* sspa1_frm */ + K1X_PADCONF(GPIO_27, MUX_MODE1, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS0)) /* sspa1_txd */ + K1X_PADCONF(GPIO_28, MUX_MODE1, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS0)) /* sspa1_rxd */ + >; + }; + + pinctrl_ssp2_0: ssp2_0_grp { + pinctrl-single,pins = < + K1X_PADCONF(GPIO_75, MUX_MODE1, (EDGE_NONE | PULL_UP | PAD_3V_DS4)) /* ssp2_sclk */ + K1X_PADCONF(GPIO_76, MUX_MODE1, (EDGE_NONE | PULL_UP | PAD_3V_DS4)) /* ssp2_frm */ + K1X_PADCONF(GPIO_77, MUX_MODE1, (EDGE_NONE | PULL_UP | PAD_3V_DS4)) /* ssp2_txd */ + K1X_PADCONF(GPIO_78, MUX_MODE1, (EDGE_NONE | PULL_UP | PAD_3V_DS4)) /* ssp2_rxd */ + >; + }; + + pinctrl_ssp2_1: ssp2_1_grp { + pinctrl-single,pins = < + K1X_PADCONF(GPIO_64, MUX_MODE3, (EDGE_NONE | PULL_UP | PAD_3V_DS4)) /* ssp2_sclk */ + K1X_PADCONF(GPIO_65, MUX_MODE3, (EDGE_NONE | PULL_UP | PAD_3V_DS4)) /* ssp2_frm */ + K1X_PADCONF(GPIO_66, MUX_MODE3, (EDGE_NONE | PULL_UP | PAD_3V_DS4)) /* ssp2_txd */ + K1X_PADCONF(GPIO_67, MUX_MODE3, (EDGE_NONE | PULL_UP | PAD_3V_DS4)) /* ssp2_rxd */ + >; + }; + + pinctrl_ssp3_0: ssp3_0_grp { + pinctrl-single,pins = < + K1X_PADCONF(GPIO_75, MUX_MODE2, (EDGE_NONE | PULL_UP | PAD_3V_DS4)) /* ssp3_sclk */ + K1X_PADCONF(GPIO_76, MUX_MODE2, (EDGE_NONE | PULL_UP | PAD_3V_DS4)) /* ssp3_frm */ + K1X_PADCONF(GPIO_77, MUX_MODE2, (EDGE_NONE | PULL_UP | PAD_3V_DS4)) /* ssp3_txd */ + K1X_PADCONF(GPIO_78, MUX_MODE2, (EDGE_NONE | PULL_UP | PAD_3V_DS4)) /* ssp3_rxd */ + >; + }; + + pinctrl_ssp3_1: ssp3_1_grp { + pinctrl-single,pins = < + K1X_PADCONF(GPIO_59, MUX_MODE2, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* ssp3_sclk */ + K1X_PADCONF(GPIO_60, MUX_MODE2, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* ssp3_frm */ + K1X_PADCONF(GPIO_61, MUX_MODE2, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* ssp3_txd */ + K1X_PADCONF(GPIO_62, MUX_MODE2, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* ssp3_rxd */ + >; + }; + + pinctrl_qspi: qspi_grp { + pinctrl-single,pins = < + K1X_PADCONF(QSPI_DAT3, MUX_MODE0, (EDGE_NONE | PULL_DOWN | PAD_3V_DS4)) /* qspi_d3 */ + K1X_PADCONF(QSPI_DAT2, MUX_MODE0, (EDGE_NONE | PULL_DOWN | PAD_3V_DS4)) /* qspi_d2 */ + K1X_PADCONF(QSPI_DAT1, MUX_MODE0, (EDGE_NONE | PULL_DOWN | PAD_3V_DS4)) /* qspi_d1 */ + K1X_PADCONF(QSPI_DAT0, MUX_MODE0, (EDGE_NONE | PULL_DOWN | PAD_3V_DS4)) /* qspi_d1 */ + K1X_PADCONF(QSPI_CLK, MUX_MODE0, (EDGE_NONE | PULL_DOWN | PAD_3V_DS4)) /* qspi_clk */ + K1X_PADCONF(QSPI_CSI, MUX_MODE0, (EDGE_NONE | PULL_UP | PAD_3V_DS4)) /* qspi_csi */ + >; + }; + + pinctrl_mmc1: mmc1_grp { + pinctrl-single,pins = < + K1X_PADCONF(MMC1_DAT3, MUX_MODE0, (EDGE_NONE | PULL_UP | PAD_3V_DS4)) /* mmc1_d3 */ + K1X_PADCONF(MMC1_DAT2, MUX_MODE0, (EDGE_NONE | PULL_UP | PAD_3V_DS4)) /* mmc1_d2 */ + K1X_PADCONF(MMC1_DAT1, MUX_MODE0, (EDGE_NONE | PULL_UP | PAD_3V_DS4)) /* mmc1_d1 */ + K1X_PADCONF(MMC1_DAT0, MUX_MODE0, (EDGE_NONE | PULL_UP | PAD_3V_DS4)) /* mmc1_d0 */ + K1X_PADCONF(MMC1_CMD, MUX_MODE0, (EDGE_NONE | PULL_UP | PAD_3V_DS4)) /* mmc1_cmd */ + K1X_PADCONF(MMC1_CLK, MUX_MODE0, (EDGE_NONE | PULL_DOWN | PAD_3V_DS4)) /* mmc1_clk */ + >; + }; + + pinctrl_mmc1_fast: mmc1_fast_grp { + pinctrl-single,pins = < + K1X_PADCONF(MMC1_DAT3, MUX_MODE0, (EDGE_NONE | PULL_UP | PAD_1V8_DS3)) /* mmc1_d3 */ + K1X_PADCONF(MMC1_DAT2, MUX_MODE0, (EDGE_NONE | PULL_UP | PAD_1V8_DS3)) /* mmc1_d2 */ + K1X_PADCONF(MMC1_DAT1, MUX_MODE0, (EDGE_NONE | PULL_UP | PAD_1V8_DS3)) /* mmc1_d1 */ + K1X_PADCONF(MMC1_DAT0, MUX_MODE0, (EDGE_NONE | PULL_UP | PAD_1V8_DS3)) /* mmc1_d0 */ + K1X_PADCONF(MMC1_CMD, MUX_MODE0, (EDGE_NONE | PULL_UP | PAD_1V8_DS3)) /* mmc1_cmd */ + K1X_PADCONF(MMC1_CLK, MUX_MODE0, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS3)) /* mmc1_clk */ + >; + }; + + pinctrl_mmc2: mmc2_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_15, MUX_MODE1, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* mmc2_data3 */ + K1X_PADCONF(GPIO_16, MUX_MODE1, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* mmc2_data2 */ + K1X_PADCONF(GPIO_17, MUX_MODE1, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* mmc2_data1 */ + K1X_PADCONF(GPIO_18, MUX_MODE1, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* mmc2_data0 */ + K1X_PADCONF(GPIO_19, MUX_MODE1, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* mmc2_cmd */ + K1X_PADCONF(GPIO_20, MUX_MODE1, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* mmc2_clk */ + >; + }; + + pinctrl_usb0_0: usb0_0_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_125, MUX_MODE1, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* vbus_on0 */ + K1X_PADCONF(GPIO_126, MUX_MODE1, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* usb_id0 */ + K1X_PADCONF(GPIO_127, MUX_MODE1, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* drive_vbus0_iso */ + >; + }; + + pinctrl_usb0_1: usb0_1_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_64, MUX_MODE1, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* vbus_on0 */ + K1X_PADCONF(GPIO_65, MUX_MODE1, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* usb_id0 */ + K1X_PADCONF(GPIO_63, MUX_MODE1, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* drive_vbus0_iso */ + >; + }; + + pinctrl_usb1_0: usb1_0_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_124, MUX_MODE1, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* drive_vbus1_iso */ + >; + }; + + pinctrl_usb1_1: usb1_1_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_66, MUX_MODE1, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* drive_vbus1_iso */ + >; + }; + + pinctrl_usb2_0: usb2_0_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_121, MUX_MODE2, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* vbus_on2 */ + K1X_PADCONF(GPIO_122, MUX_MODE2, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* usb_id2 */ + K1X_PADCONF(GPIO_123, MUX_MODE1, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* drive_vbus2_iso */ + >; + }; + + pinctrl_usb2_1: usb2_1_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_68, MUX_MODE1, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* vbus_on2 */ + K1X_PADCONF(GPIO_69, MUX_MODE1, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* usb_id2 */ + K1X_PADCONF(GPIO_67, MUX_MODE1, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* drive_vbus2_iso */ + >; + }; + + pinctrl_pcie0_0: pcie0_0_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_15, MUX_MODE2, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* PCIe0_perstn */ + K1X_PADCONF(GPIO_16, MUX_MODE2, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* PCIe0_waken */ + K1X_PADCONF(GPIO_17, MUX_MODE2, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* PCIe0_clkreqn */ + >; + }; + + pinctrl_pcie0_1: pcie0_1_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_29, MUX_MODE4, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* PCIe0_perstn */ + K1X_PADCONF(GPIO_30, MUX_MODE4, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* PCIe0_waken */ + K1X_PADCONF(GPIO_31, MUX_MODE4, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* PCIe0_clkreqn */ + >; + }; + + pinctrl_pcie0_2: pcie0_2_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_110, MUX_MODE4, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* PCIe0_perstn */ + K1X_PADCONF(GPIO_115, MUX_MODE4, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* PCIe0_waken */ + K1X_PADCONF(GPIO_116, MUX_MODE4, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* PCIe0_clkreqn */ + >; + }; + + pinctrl_pcie0_3: pcie0_3_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_53, MUX_MODE3, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* PCIe0_perstn */ + K1X_PADCONF(GPIO_54, MUX_MODE3, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* PCIe0_waken */ + K1X_PADCONF(GPIO_55, MUX_MODE3, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* PCIe0_clkreqn */ + >; + }; + + pinctrl_pcie1_0: pcie1_0_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_15, MUX_MODE4, (EDGE_NONE | PULL_DIS | PAD_1V8_DS2)) /* PCIe1_perstn */ + K1X_PADCONF(GPIO_16, MUX_MODE4, (EDGE_NONE | PULL_DIS | PAD_1V8_DS2)) /* PCIe1_waken */ + K1X_PADCONF(GPIO_17, MUX_MODE4, (EDGE_NONE | PULL_DIS | PAD_1V8_DS2)) /* PCIe1_clkreqn */ + >; + }; + + pinctrl_pcie1_1: pcie1_1_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_32, MUX_MODE4, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* PCIe1_perstn */ + K1X_PADCONF(GPIO_33, MUX_MODE4, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* PCIe1_waken */ + K1X_PADCONF(GPIO_34, MUX_MODE4, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* PCIe1_clkreqn */ + >; + }; + + pinctrl_pcie1_2: pcie1_2_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_56, MUX_MODE3, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* PCIe1_perstn */ + K1X_PADCONF(GPIO_57, MUX_MODE3, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* PCIe1_waken */ + K1X_PADCONF(GPIO_58, MUX_MODE3, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* PCIe1_clkreqn */ + >; + }; + + pinctrl_pcie1_3: pcie1_3_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_59, MUX_MODE4, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* PCIe1_perstn */ + K1X_PADCONF(GPIO_60, MUX_MODE4, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* PCIe1_waken */ + K1X_PADCONF(GPIO_61, MUX_MODE4, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* PCIe1_clkreqn */ + >; + }; + + pinctrl_pcie2_0: pcie2_0_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_18, MUX_MODE4, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* PCIe2_perstn */ + K1X_PADCONF(GPIO_19, MUX_MODE4, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* PCIe2_waken */ + K1X_PADCONF(GPIO_20, MUX_MODE4, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* PCIe2_clkreqn */ + >; + }; + + pinctrl_pcie2_1: pcie2_1_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_35, MUX_MODE4, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* PCIe2_perstn */ + K1X_PADCONF(GPIO_36, MUX_MODE4, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* PCIe2_waken */ + K1X_PADCONF(GPIO_37, MUX_MODE4, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* PCIe2_clkreqn */ + >; + }; + + pinctrl_pcie2_2: pcie2_2_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_62, MUX_MODE4, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* PCIe2_perstn */ + K1X_PADCONF(GPIO_74, MUX_MODE4, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* PCIe2_waken */ + K1X_PADCONF(GPIO_117, MUX_MODE4, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* PCIe2_clkreqn */ + >; + }; + + pinctrl_pcie2_3: pcie2_3_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_111, MUX_MODE3, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* PCIe2_perstn */ + K1X_PADCONF(GPIO_112, MUX_MODE3, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* PCIe2_waken */ + K1X_PADCONF(GPIO_113, MUX_MODE3, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* PCIe2_clkreqn */ + >; + }; + + pinctrl_pcie2_4: pcie2_4_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_62, MUX_MODE4, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* PCIe2_perstn */ + K1X_PADCONF(GPIO_112, MUX_MODE3, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* PCIe2_waken */ + K1X_PADCONF(GPIO_117, MUX_MODE4, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* PCIe2_clkreqn */ + >; + }; + + pinctrl_gmac0: gmac0_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_00, MUX_MODE1, (EDGE_NONE | PULL_DIS | PAD_1V8_DS2)) /* gmac0_rxdv */ + K1X_PADCONF(GPIO_01, MUX_MODE1, (EDGE_NONE | PULL_DIS | PAD_1V8_DS2)) /* gmac0_rx_d0 */ + K1X_PADCONF(GPIO_02, MUX_MODE1, (EDGE_NONE | PULL_DIS | PAD_1V8_DS2)) /* gmac0_rx_d1 */ + K1X_PADCONF(GPIO_03, MUX_MODE1, (EDGE_NONE | PULL_DIS | PAD_1V8_DS2)) /* gmac0_rx_clk */ + K1X_PADCONF(GPIO_04, MUX_MODE1, (EDGE_NONE | PULL_DIS | PAD_1V8_DS2)) /* gmac0_rx_d2 */ + K1X_PADCONF(GPIO_05, MUX_MODE1, (EDGE_NONE | PULL_DIS | PAD_1V8_DS2)) /* gmac0_rx_d3 */ + K1X_PADCONF(GPIO_06, MUX_MODE1, (EDGE_NONE | PULL_DIS | PAD_1V8_DS2)) /* gmac0_tx_d0 */ + K1X_PADCONF(GPIO_07, MUX_MODE1, (EDGE_NONE | PULL_DIS | PAD_1V8_DS2)) /* gmac0_tx_d1 */ + K1X_PADCONF(GPIO_08, MUX_MODE1, (EDGE_NONE | PULL_DIS | PAD_1V8_DS2)) /* gmac0_tx */ + K1X_PADCONF(GPIO_09, MUX_MODE1, (EDGE_NONE | PULL_DIS | PAD_1V8_DS2)) /* gmac0_tx_d2 */ + K1X_PADCONF(GPIO_10, MUX_MODE1, (EDGE_NONE | PULL_DIS | PAD_1V8_DS2)) /* gmac0_tx_d3 */ + K1X_PADCONF(GPIO_11, MUX_MODE1, (EDGE_NONE | PULL_DIS | PAD_1V8_DS2)) /* gmac0_tx_en */ + K1X_PADCONF(GPIO_12, MUX_MODE1, (EDGE_NONE | PULL_DIS | PAD_1V8_DS2)) /* gmac0_mdc */ + K1X_PADCONF(GPIO_13, MUX_MODE1, (EDGE_NONE | PULL_DIS | PAD_1V8_DS2)) /* gmac0_mdio */ + K1X_PADCONF(GPIO_14, MUX_MODE1, (EDGE_NONE | PULL_DIS | PAD_1V8_DS2)) /* gmac0_int_n */ + K1X_PADCONF(GPIO_45, MUX_MODE1, (EDGE_NONE | PULL_DIS | PAD_1V8_DS2)) /* gmac0_clk_ref */ + >; + }; + + pinctrl_gmac1: gmac1_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_29, MUX_MODE1, (EDGE_NONE | PULL_DIS | PAD_1V8_DS2)) /* gmac1_rxdv */ + K1X_PADCONF(GPIO_30, MUX_MODE1, (EDGE_NONE | PULL_DIS | PAD_1V8_DS2)) /* gmac1_rx_d0 */ + K1X_PADCONF(GPIO_31, MUX_MODE1, (EDGE_NONE | PULL_DIS | PAD_1V8_DS2)) /* gmac1_rx_d1 */ + K1X_PADCONF(GPIO_32, MUX_MODE1, (EDGE_NONE | PULL_DIS | PAD_1V8_DS2)) /* gmac1_rx_clk */ + K1X_PADCONF(GPIO_33, MUX_MODE1, (EDGE_NONE | PULL_DIS | PAD_1V8_DS2)) /* gmac1_rx_d2 */ + K1X_PADCONF(GPIO_34, MUX_MODE1, (EDGE_NONE | PULL_DIS | PAD_1V8_DS2)) /* gmac1_rx_d3 */ + K1X_PADCONF(GPIO_35, MUX_MODE1, (EDGE_NONE | PULL_DIS | PAD_1V8_DS2)) /* gmac1_tx_d0 */ + K1X_PADCONF(GPIO_36, MUX_MODE1, (EDGE_NONE | PULL_DIS | PAD_1V8_DS2)) /* gmac1_tx_d1 */ + K1X_PADCONF(GPIO_37, MUX_MODE1, (EDGE_NONE | PULL_DIS | PAD_1V8_DS2)) /* gmac1_tx */ + K1X_PADCONF(GPIO_38, MUX_MODE1, (EDGE_NONE | PULL_DIS | PAD_1V8_DS2)) /* gmac1_tx_d2 */ + K1X_PADCONF(GPIO_39, MUX_MODE1, (EDGE_NONE | PULL_DIS | PAD_1V8_DS2)) /* gmac1_tx_d3 */ + K1X_PADCONF(GPIO_40, MUX_MODE1, (EDGE_NONE | PULL_DIS | PAD_1V8_DS2)) /* gmac1_tx_en */ + K1X_PADCONF(GPIO_41, MUX_MODE1, (EDGE_NONE | PULL_DIS | PAD_1V8_DS2)) /* gmac1_mdc */ + K1X_PADCONF(GPIO_42, MUX_MODE1, (EDGE_NONE | PULL_DIS | PAD_1V8_DS2)) /* gmac1_mdio */ + K1X_PADCONF(GPIO_43, MUX_MODE1, (EDGE_NONE | PULL_DIS | PAD_1V8_DS2)) /* gmac1_int_n */ + K1X_PADCONF(GPIO_46, MUX_MODE1, (EDGE_NONE | PULL_DIS | PAD_1V8_DS2)) /* gmac1_clk_ref */ + >; + }; + + pinctrl_can_0: can_0_grp { + pinctrl-single,pins = < + K1X_PADCONF(GPIO_75, MUX_MODE3, (EDGE_NONE | PULL_UP | PAD_3V_DS4)) /* can_tx0 */ + K1X_PADCONF(GPIO_76, MUX_MODE3, (EDGE_NONE | PULL_UP | PAD_3V_DS4)) /* can_rx0 */ + >; + }; + + pinctrl_can_1: can_1_grp { + pinctrl-single,pins = < + K1X_PADCONF(GPIO_54, MUX_MODE2, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* can_tx0 */ + K1X_PADCONF(GPIO_55, MUX_MODE2, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* can_rx0 */ + >; + }; + + pinctrl_hdmi_0: hdmi_0_grp { + pinctrl-single,pins = < + K1X_PADCONF(GPIO_86, MUX_MODE1, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* hdmi_tx_hscl */ + K1X_PADCONF(GPIO_87, MUX_MODE1, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* hdmi_tx_hsda */ + K1X_PADCONF(GPIO_88, MUX_MODE1, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* hdmi_tx_hcec */ + K1X_PADCONF(GPIO_89, MUX_MODE1, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* hdmi_tx_pdp */ + >; + }; + + pinctrl_hdmi_1: hdmi_1_grp { + pinctrl-single,pins = < + K1X_PADCONF(GPIO_59, MUX_MODE1, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* hdmi_tx_hscl */ + K1X_PADCONF(GPIO_60, MUX_MODE1, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* hdmi_tx_hsda */ + K1X_PADCONF(GPIO_61, MUX_MODE1, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* hdmi_tx_hcec */ + K1X_PADCONF(GPIO_62, MUX_MODE1, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* hdmi_tx_pdp */ + >; + }; + + pinctrl_spi_lcd_0: spi_lcd_0_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_86, MUX_MODE3, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* dclk */ + K1X_PADCONF(GPIO_87, MUX_MODE3, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* dcx */ + K1X_PADCONF(GPIO_88, MUX_MODE3, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* din */ + K1X_PADCONF(GPIO_89, MUX_MODE3, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* dout0 */ + K1X_PADCONF(GPIO_90, MUX_MODE3, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* dout1 */ + K1X_PADCONF(GPIO_91, MUX_MODE3, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* dsi_te */ + K1X_PADCONF(GPIO_92, MUX_MODE3, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* smpn_rstb */ + >; + }; + + pinctrl_spi_lcd_1: spi_lcd_1_grp { + pinctrl-single,pins =< + K1X_PADCONF(PRI_TDI, MUX_MODE3, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* dclk */ + K1X_PADCONF(PRI_TMS, MUX_MODE3, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* dcx */ + K1X_PADCONF(PRI_TCK, MUX_MODE3, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* din */ + K1X_PADCONF(PRI_TDO, MUX_MODE3, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* dout0 */ + K1X_PADCONF(GPIO_74, MUX_MODE3, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* dout1 */ + K1X_PADCONF(GPIO_114, MUX_MODE3, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* dsi_te */ + K1X_PADCONF(GPIO_63, MUX_MODE3, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* smpn_rstb */ + >; + }; + + pinctrl_camera0: camera0_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_53, MUX_MODE1, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* cam_mclk0 */ + >; + }; + + pinctrl_camera1: camera1_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_58, MUX_MODE1, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* cam_mclk1 */ + >; + }; + + pinctrl_camera2: camera2_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_120, MUX_MODE1, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* cam_mclk2 */ + >; + }; + + pinctrl_pmic: pmic_grp { + pinctrl-single,pins = < + K1X_PADCONF(VCXO_EN, MUX_MODE0, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* vcxo_en */ + K1X_PADCONF(DVL0, MUX_MODE0, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* dvl0 */ + K1X_PADCONF(DVL1, MUX_MODE0, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* dvl1 */ + >; + }; + + pinctrl_mn_clk_0: mn_clk_0_grp { + pinctrl-single,pins = < + K1X_PADCONF(GPIO_92, MUX_MODE1, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* mn_clk */ + >; + }; + + pinctrl_mn_clk_1: mn_clk_1_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_81, MUX_MODE4, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* mn_clk */ + >; + }; + + pinctrl_mn_clk_2: mn_clk_2_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_44, MUX_MODE1, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* mn_clk */ + >; + }; + + pinctrl_mn_clk_3: mn_clk_3_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_20, MUX_MODE3, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* mn_clk */ + >; + }; + + pinctrl_mn_clk_4: mn_clk_4_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_23, MUX_MODE3, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* mn_clk */ + >; + }; + + pinctrl_mn_clk_5: mn_clk_5_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_32, MUX_MODE3, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* mn_clk */ + >; + }; + + pinctrl_mn_clk2_0: mn_clk2_0_grp { + pinctrl-single,pins = < + K1X_PADCONF(GPIO_91, MUX_MODE1, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* mn_clk2 */ + >; + }; + + pinctrl_mn_clk2_1: mn_clk2_1_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_85, MUX_MODE3, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* mn_clk2 */ + >; + }; + + pinctrl_vcxo_0: vcxo_0_grp { + pinctrl-single,pins =< + K1X_PADCONF(DVL0, MUX_MODE3, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* vcxo_req */ + K1X_PADCONF(DVL1, MUX_MODE3, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* vcxo_out */ + >; + }; + + pinctrl_vcxo_1: vcxo_1_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_16, MUX_MODE3, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* vcxo_req */ + K1X_PADCONF(GPIO_17, MUX_MODE3, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* vcxo_out */ + >; + }; + + pinctrl_vcxo_2: vcxo_2_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_89, MUX_MODE4, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* vcxo_req */ + K1X_PADCONF(GPIO_90, MUX_MODE4, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* vcxo_out */ + >; + }; + + pinctrl_vcxo_out_0: vcxo_out_0_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_91, MUX_MODE2, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* vcxo_out_0 */ + >; + }; + + pinctrl_vcxo_out_1: vcxo_out_1_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_12, MUX_MODE3, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* vcxo_out */ + >; + }; + + pinctrl_32k_out_0: 32k_out_0_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_21, MUX_MODE3, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* 32k_out */ + >; + }; + + pinctrl_32k_out_1: 32k_out_1_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_31, MUX_MODE3, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* 32k_out */ + >; + }; + + pinctrl_32k_out_2: 32k_out_2_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_28, MUX_MODE4, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* 32k_out */ + >; + }; + + pinctrl_pri: pri_grp { + pinctrl-single,pins =< + K1X_PADCONF(PRI_TDI, MUX_MODE0, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* pri_tdi */ + K1X_PADCONF(PRI_TMS, MUX_MODE0, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* pri_tms */ + K1X_PADCONF(PRI_TCK, MUX_MODE0, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* pri_tck */ + K1X_PADCONF(PRI_TDO, MUX_MODE0, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* pri_tck */ + >; + }; +}; + |