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There is memory constraint that it should be within 128MB from
firmware address. But if IOMMU is supported, then this constraint
is meaningless and DMABUF importing can be used.
So this patch adds V4L2_MEMORY_DMABUF type support for both decoder
and encoder.
Change-Id: I2c893da31f906fcd3f26edeed67ad1e4667e6081
Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com>
Signed-off-by: Donghwa Lee <dh09.lee@samsung.com>
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This patch enables fuse config to support user file system.
Change-Id: I6543ace82673ab4108ea3154524cee5fb29a4760
Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com>
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Repeately turning on and off a layer, sometimes page fault occurs. This
problem seems to happen, because of H/W malfunction during turning on
the layer. But it can be solved by setting the framebuffer source size
by 0.
Kernel dump:
[ 24.646472] PAGE FAULT occurred at 0x23000000 by 14650000.sysmmu(Page table base: 0x6d924000)
[ 24.653515] Lv1 entry: 0x6e3b1001
[ 24.656945] ------------[ cut here ]------------
[ 24.661485] kernel BUG at drivers/iommu/exynos-iommu.c:358!
[ 24.667030] Internal error: Oops - BUG: 0 [#1] PREEMPT SMP ARM
[ 24.672836] Modules linked in:
[ 24.675872] CPU: 0 PID: 0 Comm: swapper/0 Not tainted 4.0.0-00007-g838e0df #136
[ 24.683145] Hardware name: SAMSUNG EXYNOS (Flattened Device Tree)
[ 24.689214] task: c0e1aff0 ti: c0e0c000 task.ti: c0e0c000
[ 24.694597] PC is at exynos_sysmmu_irq+0x1b8/0x2c4
[ 24.699358] LR is at vprintk_emit+0x2a0/0x550
[ 24.703684] pc : [<c036e530>] lr : [<c00705d0>] psr: 60070193
[ 24.703684] sp : c0e0dd90 ip : 00000000 fp : c0e0ddcc
[ 24.715121] r10: ee22e610 r9 : 00000000 r8 : ee22e628
[ 24.720321] r7 : ed875810 r6 : 23000000 r5 : ed924000 r4 : 00000000
[ 24.726820] r3 : c0e98098 r2 : 00000000 r1 : 00000000 r0 : ed6819c0
[ 24.733321] Flags: nZCv IRQs off FIQs on Mode SVC_32 ISA ARM Segment kernel
[ 24.740685] Control: 10c5387d Table: 6cb8c06a DAC: 00000015
[ 24.746403] Process swapper/0 (pid: 0, stack limit = 0xc0e0c210)
[ 24.752383] Stack: (0xc0e0dd90 to 0xc0e0e000)
[ 24.756718] dd80: c0e0dd9c c0932868 ffff28da 6d924000
[ 24.764864] dda0: ffff2990 ee22d8c0 ee22f060 00000049 c0e34e34 c0e0c000 00000000 00000000
[ 24.773009] ddc0: c0e0de14 c0e0ddd0 c0071fd8 c036e384 ffffffff 7fffffff c0e0ddf4 ee22f000
[ 24.781155] dde0: c0e95dfc c0e95de8 c0e0de14 ee22f000 ee22f060 ee22d8c0 c0e34e34 ee004670
[ 24.789300] de00: ee010800 c0e0df00 c0e0de34 c0e0de18 c007221c c0071f80 ee22f000 ee22f060
[ 24.797446] de20: 00000017 c0e34e34 c0e0de4c c0e0de38 c007520c c00721dc 00000049 ee0283c0
[ 24.805591] de40: c0e0de64 c0e0de50 c0071540 c0075144 0000001c ee0283c0 c0e0de8c c0e0de68
[ 24.813737] de60: c02fe7e8 c0071510 00000017 00000000 00000017 00000000 00000001 ee010800
[ 24.821882] de80: c0e0dea4 c0e0de90 c0071540 c02fe750 c0e08a1c 00000000 c0e0ded4 c0e0dea8
[ 24.830028] dea0: c0071880 c0071510 c0e0df00 f000200c 00000017 c0e140a8 c0e0df00 f0002000
[ 24.838173] dec0: c0e96374 c0936d0c c0e0defc c0e0ded8 c0008734 c0071800 c0010d88 60070013
[ 24.846319] dee0: ffffffff c0e0df34 00000001 c0e96374 c0e0df54 c0e0df00 c0014780 c0008700
[ 24.854464] df00: 00000001 00000000 00000000 c0020720 c0e0c000 c0e13530 00000000 00000000
[ 24.862610] df20: 00000001 c0e96374 c0936d0c c0e0df54 c0e0df58 c0e0df48 c0010d84 c0010d88
[ 24.870755] df40: 60070013 ffffffff c0e0df94 c0e0df58 c00626d8 c0010d4c 00000001 c0eb1f00
[ 24.878901] df60: c0e95ab0 c0e0df70 c0e1353c c0e0a580 00000002 c0e13e84 c0e09b88 c0e0df58
[ 24.887046] df80: c092e1b8 ffffffff c0e0dfac c0e0df98 c0928880 c00622fc c0e13e10 c0eb1f00
[ 24.895192] dfa0: c0e0dff4 c0e0dfb0 c0d57d2c c09287f8 ffffffff ffffffff c0d576ec 00000000
[ 24.903337] dfc0: 00000000 c0dc1420 00000000 c0eb22d4 c0e134c0 c0dc141c c0e1c20c 4000406a
[ 24.911483] dfe0: 410fc073 00000000 00000000 c0e0dff8 40008074 c0d57968 00000000 00000000
[ 24.919641] [<c036e530>] (exynos_sysmmu_irq) from [<c0071fd8>] (handle_irq_event_percpu+0x64/0x25c)
[ 24.928644] [<c0071fd8>] (handle_irq_event_percpu) from [<c007221c>] (handle_irq_event+0x4c/0x6c)
[ 24.937483] [<c007221c>] (handle_irq_event) from [<c007520c>] (handle_level_irq+0xd4/0x14c)
[ 24.945802] [<c007520c>] (handle_level_irq) from [<c0071540>] (generic_handle_irq+0x3c/0x4c)
[ 24.954209] [<c0071540>] (generic_handle_irq) from [<c02fe7e8>] (combiner_handle_cascade_irq+0xa4/0x110)
[ 24.963653] [<c02fe7e8>] (combiner_handle_cascade_irq) from [<c0071540>] (generic_handle_irq+0x3c/0x4c)
[ 24.973009] [<c0071540>] (generic_handle_irq) from [<c0071880>] (__handle_domain_irq+0x8c/0xfc)
[ 24.981676] [<c0071880>] (__handle_domain_irq) from [<c0008734>] (gic_handle_irq+0x40/0x78)
[ 24.989994] [<c0008734>] (gic_handle_irq) from [<c0014780>] (__irq_svc+0x40/0x74)
[ 24.997440] Exception stack(0xc0e0df00 to 0xc0e0df48)
[ 25.002469] df00: 00000001 00000000 00000000 c0020720 c0e0c000 c0e13530 00000000 00000000
[ 25.010616] df20: 00000001 c0e96374 c0936d0c c0e0df54 c0e0df58 c0e0df48 c0010d84 c0010d88
[ 25.018757] df40: 60070013 ffffffff
[ 25.022234] [<c0014780>] (__irq_svc) from [<c0010d88>] (arch_cpu_idle+0x48/0x4c)
[ 25.029595] [<c0010d88>] (arch_cpu_idle) from [<c00626d8>] (cpu_startup_entry+0x3e8/0x4bc)
[ 25.037837] [<c00626d8>] (cpu_startup_entry) from [<c0928880>] (rest_init+0x94/0x98)
[ 25.045544] [<c0928880>] (rest_init) from [<c0d57d2c>] (start_kernel+0x3d0/0x3dc)
[ 25.052992] Code: e34c30e9 e5932004 e3520000 ca000018 (e7f001f2)
[ 25.059058] ---[ end trace 91806a51727d6586 ]---
Change-Id: Ic134f206721e33335962d7e941741331ec72672b
Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com>
Signed-off-by: Hyungwon Hwang <human.hwang@samsung.com>
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FIMC & GSC driver can calculate the offset of planes. So there are
use cases which IPP receives just one GEM handle of an image with
multiple plane. This patch extends ipp_validate_mem_node() to validate
this case.
Change-Id: Ia7b4486f92c9d075f7f7d60dba183d55b5b5dfc9
Signed-off-by: Hyungwon Hwang <human.hwang@samsung.com>
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MFCINST_GOT_INST state is set to encoder context with set_format
only for catpure buffer. In queue_setup of encoder called during
reqbufs, it is checked MFCINST_GOT_INST state for both capture
and output buffer. So this patch fixes to encoder to check
MFCINST_GOT_INST state only for capture buffer from queue_setup.
Change-Id: I53997d92ebf8a9bda804d101f2daf8d9731e4a47
Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com>
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Config depends on the opreation. So it must be referenced by an
operation id, not a property id.
Change-Id: Id57a5e6d371125d85cde97cf03848ffbf0b8abfd
Signed-off-by: Hyungwon Hwang <human.hwang@samsung.com>
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Basically, gsc do not support ARGB color format.
However, when mfc decodes through OMX(openmax) which is standard API
for Media Library Portability, output format was shown as ARGB format.
For support it, this patch adds ARGB8888 format support for ipp gsc driver.
Change-Id: Ie5134592eca96acd133e2c098b6fd3c92c5e2605
Signed-off-by: Ingi Kim <ingi2.kim@samsung.com>
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When color format changes YUV to RGB by ipp gsc,
the color of output image seems to come out.
The alpha value should have ignored but bits
in the GSCALER_OUT_CON register do not set to 0xff(masking alpha value)
This patch masks alpha bits in the GSCALER_OUT_CON register
when the userspace decide to use XRGB8888.
Change-Id: I78bf2d8214cbdb10568b3bb4b9af6b9bf28752a5
Signed-off-by: Ingi Kim <ingi2.kim@samsung.com>
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Eliminate iommu fault during encoding by adjusting image size
used for buffer size computation and ensuring that the buffer is not
overrun.
Change-Id: I4837ef4cd518732af8110725b50e8f4e1bd313a9
Signed-off-by: Andrzej Pietrasiewicz <andrzej.p@samsung.com>
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As cannot use video layer, need lower layer than default layer. So make
higher graphic layer 0 priority then graphic layer 1 priority. This is
just workaround, may need to make a interface to change layer priority
for user later.
Change-Id: If63a2f3eef6c164b5b3c3a5c801f9090a6a0a341
Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com>
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Also disable CONFIG_BL_SWITCHER as any error when does stress test.
Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com>
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The new CPU clock type allows the use of generic arm_big_little_dt
cpufreq driver for Exynos5800.
Changes by Bartlomiej:
- split Exynos5800 support from the original patch
- disable cpufreq if big.LITTLE switcher support is enabled
Cc: Tomasz Figa <tomasz.figa@gmail.com>
Cc: Kukjin Kim <kgene.kim@samsung.com>
Cc: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
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Fix CPU operating points for Exynos5800 (it uses different
voltages than Exynos5420 and supports additional frequencies).
However don't use 2000MHz & 1900MHz OPPs (for A15 cores) and
1400MHz OPP (for A7 cores) until there is a separate DTS for
ODROID-XU3 Lite board (which doesn't support these higher
OPPs).
Based on Hardkernel's kernel for ODROID-XU3 board.
Cc: Kukjin Kim <kgene.kim@samsung.com>
Cc: Doug Anderson <dianders@chromium.org>
Cc: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Cc: Andreas Faerber <afaerber@suse.de>
Cc: Sachin Kamat <sachin.kamat@linaro.org>
Cc: Thomas Abraham <thomas.ab@samsung.com>
Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
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Fix cpu clock configuration data for Exynos5800 (it uses
higher PCLK_DBG divider values than Exynos5420 and supports
additional frequencies).
Based on Hardkernel's kernel for ODROID-XU3 board.
Cc: Tomasz Figa <tomasz.figa@gmail.com>
Cc: Mike Turquette <mturquette@linaro.org>
Cc: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Cc: Thomas Abraham <thomas.ab@samsung.com>
Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
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The new CPU clock type allows the use of generic arm_big_little_dt
cpufreq driver for Exynos5420.
Changes by Bartlomiej:
- split Exynos5420 support from the original patch
- disable cpufreq if big.LITTLE switcher support is enabled
Cc: Tomasz Figa <tomasz.figa@gmail.com>
Cc: Kukjin Kim <kgene.kim@samsung.com>
Cc: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
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For Exynos5420 platforms, add CPU operating points and CPU
regulator supply properties for migrating from Exynos specific
cpufreq driver to using generic cpufreq driver.
Changes by Bartlomiej:
- split Exynos5420 support from the original patch
Cc: Kukjin Kim <kgene.kim@samsung.com>
Cc: Doug Anderson <dianders@chromium.org>
Cc: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Cc: Andreas Faerber <afaerber@suse.de>
Cc: Sachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
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cpu clock
With the addition of the new Samsung specific cpu-clock type, the
arm clock can be represented as a cpu-clock type. Add the CPU clock
configuration data and instantiate the CPU clock type for Exynos5420.
Changes by Bartlomiej:
- split Exynos5420 support from the original patches
- moved E5420_[EGL,KFC]_DIV0() macros to clk-exynos5420.c
Cc: Tomasz Figa <tomasz.figa@gmail.com>
Cc: Mike Turquette <mturquette@linaro.org>
Cc: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
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Add cluster regulator supply properties as a preparation to
adding generic arm_big_little_dt cpufreq driver support for
Exynos5420 and Exynos5800 based boards.
Cc: Kukjin Kim <kgene.kim@samsung.com>
Cc: Doug Anderson <dianders@chromium.org>
Cc: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Cc: Andreas Faerber <afaerber@suse.de>
Cc: Sachin Kamat <sachin.kamat@linaro.org>
Cc: Thomas Abraham <thomas.ab@samsung.com>
Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
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Add cluster regulator support as a preparation to adding
generic arm_big_little_dt cpufreq_dt driver support for
ODROID-XU3 board. This allows arm_big_little[_dt] driver
to set not only the frequency but also the voltage (which
is obtained from operating point's voltage value) for CPU
clusters.
Cc: Kukjin Kim <kgene.kim@samsung.com>
Cc: Doug Anderson <dianders@chromium.org>
Cc: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Cc: Andreas Faerber <afaerber@suse.de>
Cc: Sachin Kamat <sachin.kamat@linaro.org>
Cc: Thomas Abraham <thomas.ab@samsung.com>
Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
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Exynos5250 based platforms have switched over to use generic
cpufreq driver for cpufreq functionality. So the Exynos
specific cpufreq support for these platforms can be removed.
The exynos-cpufreq driver itself is also removed as it is no
longer used/needed after Exynos5250 support removal.
Based on the earlier work by Thomas Abraham.
Cc: Viresh Kumar <viresh.kumar@linaro.org>
Cc: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Cc: Thomas Abraham <thomas.ab@samsung.com>
Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
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The new CPU clock type allows the use of generic CPUfreq driver.
Switch Exynos5250 to using generic cpufreq driver.
Changes by Bartlomiej:
- split Exynos5250 support from the original patch
Cc: Tomasz Figa <tomasz.figa@gmail.com>
Cc: Kukjin Kim <kgene.kim@samsung.com>
Cc: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
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For Exynos5250 platforms, add CPU operating points and CPU
regulator supply properties for migrating from Exynos specific
cpufreq driver to using generic cpufreq driver.
Changes by Bartlomiej:
- split Exynos5250 support from the original patch
- added CPU regulator supply property for Google Spring board
Cc: Kukjin Kim <kgene.kim@samsung.com>
Cc: Doug Anderson <dianders@chromium.org>
Cc: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Cc: Andreas Faerber <afaerber@suse.de>
Cc: Sachin Kamat <sachin.kamat@linaro.org>
Cc: Andreas Farber <afaerber@suse.de>
Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
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cpu clock
With the addition of the new Samsung specific cpu-clock type, the
arm clock can be represented as a cpu-clock type. Add the CPU clock
configuration data and instantiate the CPU clock type for Exynos5250.
Changes by Bartlomiej:
- split Exynos5250 support from the original patch
- moved E5250_CPU_DIV[0,1]() macros to clk-exynos5250.c
Cc: Tomasz Figa <tomasz.figa@gmail.com>
Cc: Mike Turquette <mturquette@linaro.org>
Cc: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
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Exynos4x12 based platforms have switched over to use generic
cpufreq driver for cpufreq functionality. So the Exynos
specific cpufreq support for these platforms can be removed.
Based on the earlier work by Thomas Abraham.
Cc: Viresh Kumar <viresh.kumar@linaro.org>
Cc: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Cc: Thomas Abraham <thomas.ab@samsung.com>
Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
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The new CPU clock type allows the use of generic CPUfreq driver.
Switch Exynos4x12 to using generic cpufreq driver.
This patch also takes care of making ARM_EXYNOS_CPU_FREQ_BOOST_SW
config option depend on cpufreq-dt driver instead of exynos-cpufreq
one and fixes the minor issue present with the old code (support
for 'boost' mode in the exynos-cpufreq driver was enabled for all
supported SoCs even though 'boost' frequency was provided only for
Exynos4x12 ones).
Cc: Tomasz Figa <tomasz.figa@gmail.com>
Cc: Kukjin Kim <kgene.kim@samsung.com>
Cc: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Cc: Thomas Abraham <thomas.ab@samsung.com>
Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
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For Exynos4x12 platforms, add CPU operating points and CPU
regulator supply properties for migrating from Exynos specific
cpufreq driver to using generic cpufreq driver.
Based on the earlier work by Thomas Abraham.
Cc: Kukjin Kim <kgene.kim@samsung.com>
Cc: Doug Anderson <dianders@chromium.org>
Cc: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Cc: Andreas Faerber <afaerber@suse.de>
Cc: Sachin Kamat <sachin.kamat@linaro.org>
Cc: Andreas Farber <afaerber@suse.de>
Cc: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Cc: Thomas Abraham <thomas.ab@samsung.com>
Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
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cpu clock
With the addition of the new Samsung specific cpu-clock type, the
arm clock can be represented as a cpu-clock type. Add the CPU clock
configuration data and instantiate the CPU clock type for Exynos4x12.
Based on the earlier work by Thomas Abraham.
Cc: Tomasz Figa <tomasz.figa@gmail.com>
Cc: Mike Turquette <mturquette@linaro.org>
Cc: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Cc: Thomas Abraham <thomas.ab@samsung.com>
Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
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Add 'boost' mode frequencies support:
- add boost-opps binding to cpufreq-dt driver bindings
- make cpufreq_init() adjust freq_table accordingly
- fix set_target() to handle boost frequencies
- add boost_supported field to struct cpufreq_dt_platform_data
- set dt_cpufreq_driver.boost_supported in dt_cpufreq_probe()
This patch makes cpufreq-dt driver aware of 'boost' mode frequencies
and prepares it for adding support for Exynos4x12 'boost' support.
boost-opps binding is currently limited to cpufreq-dt but once there is
a need for cpufreq wide and/or generic Linux device support for 'boost'
mode cpufreq-dt can be updated to handle the new code without changing
the binding itself.
The decision to make 'boost' mode support limited to cpufreq-dt driver
for now was taken because 'boost' mode is currently a niche feature and
code needed for parsing boost-opps binding is minimal and simple. More
generic (i.e. separate 'boost' OPPs list in struct device and generic
cpufreq convertion of them to freq_table format) support would need far
more code and effort to make it work. Doing it without a demonstrated
real need would be on overengineering IMHO.
Cc: Tomasz Figa <tomasz.figa@gmail.com>
Cc: Mike Turquette <mturquette@linaro.org>
Cc: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Cc: Thomas Abraham <thomas.ab@samsung.com>
Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
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Prefix dev_pm_opp_init_cpufreq_table() with "__" and add a wrapper
for it to keep current users unchanged. Then add an extra_opps
parameter to __dev_pm_opp_init_cpufreq_table() to allow allocation of
extra table entries in freq_table.
This patch is a preparation for adding 'boost' mode frequencies
support to cpufreq-dt driver.
Cc: Tomasz Figa <tomasz.figa@gmail.com>
Cc: Mike Turquette <mturquette@linaro.org>
Cc: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Cc: Thomas Abraham <thomas.ab@samsung.com>
Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
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Exynos4210 based platforms have switched over to use generic
cpufreq driver for cpufreq functionality. So the Exynos
specific cpufreq support for these platforms can be removed.
Changes by Bartlomiej:
- dropped Exynos5250 support removal for now
- updated exynos-cpufreq.[c,h]
Cc: Viresh Kumar <viresh.kumar@linaro.org>
Cc: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
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The new CPU clock type allows the use of generic CPUfreq driver.
Switch Exynos4210 to using generic cpufreq driver.
Changes by Bartlomiej:
- removed non-Exynos4210 support for now
Cc: Tomasz Figa <tomasz.figa@gmail.com>
Cc: Kukjin Kim <kgene.kim@samsung.com>
Cc: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
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For Exynos4210 platforms, add CPU operating points and CPU
regulator supply properties for migrating from Exynos specific
cpufreq driver to using generic cpufreq driver.
Changes by Bartlomiej:
- removed Exynos5250 and Exynos5420 support for now
Cc: Kukjin Kim <kgene.kim@samsung.com>
Cc: Doug Anderson <dianders@chromium.org>
Cc: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Cc: Andreas Faerber <afaerber@suse.de>
Cc: Sachin Kamat <sachin.kamat@linaro.org>
Cc: Andreas Farber <afaerber@suse.de>
Cc: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
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clock
With the addition of the new Samsung specific cpu-clock type, the
arm clock can be represented as a cpu-clock type. Add the CPU clock
configuration data and instantiate the CPU clock type for Exynos4210.
Changes by Bartlomiej:
- fixed issue with wrong dividers being setup by Common Clock Framework
(by an addition of CLK_RECALC_NEW_RATES clock flag to mout_apll clock,
without this change cpufreq-dt driver showed ~10 mA larger energy
consumption when compared to cpufreq-exynos one when "performance"
cpufreq governor was used on Exynos4210 SoC based Origen board), this
was probably meant to be workarounded by use of CLK_GET_RATE_NOCACHE
and CLK_DIVIDER_READ_ONLY clock flags in the original patchset (in
"[PATCH v12 6/6] clk: samsung: remove unused clock aliases and update
clock flags") but using these flags is not sufficient to fix the issue
observed
- removed Exynos5250 and Exynos5420 support for now
Cc: Tomasz Figa <tomasz.figa@gmail.com>
Cc: Mike Turquette <mturquette@linaro.org>
Cc: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
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The CPU clock provider supplies the clock to the CPU clock domain. The
composition and organization of the CPU clock provider could vary among
Exynos SoCs. A CPU clock provider can be composed of clock mux, dividers
and gates. This patch defines a new clock type for CPU clock provider and
adds infrastructure to register the CPU clock providers for Samsung
platforms.
Changes by Bartlomiej:
- fixed issue with setting lower dividers before the parent clock speed
was lowered (the issue resulted in lockup on Exynos4210 SoC based
Origen board when "ondemand" cpufreq governor was stress tested)
- fixed missing spin_unlock on error in exynos_cpuclk_post_rate_change()
problem by moving cfg_data search outside of the spin locked area
- removed leftover kfree() in exynos_register_cpu_clock() that could
result in dereferencing the NULL pointer on error
- moved spin_lock earlier in exynos_cpuclk_pre_rate_change() to cover
reading of E4210_SRC_CPU and E4210_DIV_CPU1 registers
- added missing "last chance" checks to wait_until_divider_stable() and
wait_until_mux_stable() (needed in case that IRQ handling took long
time to proceed and resulted in function printing incorrect error
message about timeout)
- moved E4210_CPU_DIV[0,1]() macros just before their only users,
this resulted in moving them from patch #2 to patch #3/6 ("clk:
samsung: exynos4: add cpu clock configuration data and instantiate
cpu clock")
- removed E5250_CPU_DIV[0,1](), E5420_EGL_DIV0() and E5420_KFC_DIV()
macros for now
- added my Copyrights to drivers/clk/samsung/clk-cpu.c
Cc: Tomasz Figa <tomasz.figa@gmail.com>
Cc: Mike Turquette <mturquette@linaro.org>
Cc: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
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This flag is needed to fix the issue with wrong dividers being setup
by Common Clock Framework when using the new Exynos cpu clock support.
The issue happens because clk_core_set_rate_nolock() calls
clk_calc_new_rates(clk, rate) before both pre/post clock notifiers have
a chance to run. In case of Exynos cpu clock support pre/post clock
notifiers are registered for mout_apll clock which is a parent of armclk
cpu clock and dividers are modified in both pre and post clock notifier.
This results in wrong dividers values being later programmed by
clk_change_rate(top). To workaround the problem CLK_RECALC_NEW_RATES
flag is added and it is set for mout_apll clock later so the correct
divider values are re-calculated after both pre and post clock notifiers
had run.
For example when using "performance" governor on Exynos4210 Origen board
the cpufreq-dt driver requests to change the frequency from 1000MHz to
1200MHz and after the change state of the relevant clocks is following:
Without use of CLK_GET_RATE_NOCACHE flag:
fout_apll rate: 1200000000
fout_apll_div_2 rate: 600000000
mout_clkout_cpu rate: 600000000
div_clkout_cpu rate: 600000000
clkout_cpu rate: 600000000
mout_apll rate: 1200000000
armclk rate: 1200000000
mout_hpm rate: 1200000000
div_copy rate: 300000000
div_hpm rate: 300000000
mout_core rate: 1200000000
div_core rate: 1200000000
div_core2 rate: 1200000000
arm_clk_div_2 rate: 600000000
div_corem0 rate: 300000000
div_corem1 rate: 150000000
div_periph rate: 300000000
div_atb rate: 300000000
div_pclk_dbg rate: 150000000
sclk_apll rate: 1200000000
sclk_apll_div_2 rate: 600000000
With use of CLK_GET_RATE_NOCACHE flag:
fout_apll rate: 1200000000
fout_apll_div_2 rate: 600000000
mout_clkout_cpu rate: 600000000
div_clkout_cpu rate: 600000000
clkout_cpu rate: 600000000
mout_apll rate: 1200000000
armclk rate: 1200000000
mout_hpm rate: 1200000000
div_copy rate: 200000000
div_hpm rate: 200000000
mout_core rate: 1200000000
div_core rate: 1200000000
div_core2 rate: 1200000000
arm_clk_div_2 rate: 600000000
div_corem0 rate: 300000000
div_corem1 rate: 150000000
div_periph rate: 300000000
div_atb rate: 240000000
div_pclk_dbg rate: 120000000
sclk_apll rate: 150000000
sclk_apll_div_2 rate: 75000000
Without this change cpufreq-dt driver showed ~10 mA larger energy
consumption when compared to cpufreq-exynos one when "performance"
cpufreq governor was used on Exynos4210 SoC based Origen board.
This issue was probably meant to be workarounded by use of
CLK_GET_RATE_NOCACHE and CLK_DIVIDER_READ_ONLY clock flags in
the original Exynos cpu clock patchset (in "[PATCH v12 6/6] clk:
samsung: remove unused clock aliases and update clock flags" patch)
but usage of these flags is not sufficient to fix the issue observed.
Cc: Thomas Abraham <thomas.ab@samsung.com>
Cc: Tomasz Figa <tomasz.figa@gmail.com>
Cc: Mike Turquette <mturquette@linaro.org>
Cc: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
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Commit 26ab1c62b6e1 ("cpufreq: exynos5250: Set APLL rate
using CCF API") removed the last user of ->need_apll_change
method. Remove it and then cleanup exynos_cpufreq_scale()
accordingly.
This patch was tested on Exynos4412 SoC based Trats2 board.
There should be no functional changes caused by this patch.
Cc: Sachin Kamat <sachin.kamat@linaro.org>
Cc: Lukasz Majewski <l.majewski@samsung.com>
Cc: Kukjin Kim <kgene@kernel.org>
Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
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This patch enables trace and debug configs to support user trace
request.
Change-Id: I7a63a7cf9d7bb5510434db8ff2fcc4ae8f7938bb
Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com>
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The dmabuf fd can be shared between processes via unix domain
socket. The file of dmabuf fd is came from anon_inode. The inode
has no set and get xattr operations, so it can not be shared
between processes with smack. This patch fixes just to ignore
private inode including anon_inode for smack_file_receive.
Change-Id: I1b5223ebf2fb1f810380c62096aa64a16b054057
Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com>
Acked-by: Casey Schaufler <casey@schaufler-ca.com>
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Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
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Testing showed that HW produces BGR32 rather then RGB32 as exposed
in the driver. The documentation seems to state the pixels are stored
in little endian order.
Change-Id: I0f7cdea461bd09ff2aac24cf6dfd001d0848b534
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Ingi Kim <ingi2.kim@samsung.com>
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JPEG HW can access buffer beyond the image data for images, which width
or height is not properly aligned. This patch adds RGB565 format to
workaround code to solve IOMMU page fault issue. The exact needed buffer
enlargement workaround need to be determined experimentally.
Reported-by: Inha Song <ideal.song@samsung.com>
Suggested-by: Andrzej Pietrasiewicz <andrzej.p@samsung.com>
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
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This patch change version to 4.0 from 4.0.0 because of upstream tag.
Change-Id: I6ef7dfedcf1decb07ca5ab6aaec5b5f462f084fa
Signed-off-by: Inha Song <ideal.song@samsung.com>
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Change-Id: Ib6eaf6e12ecc8f065b085253dbcc0c538caff511
Signed-off-by: Inha Song <ideal.song@samsung.com>
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This patch enables uinput config to support userland input driver.
Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com>
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On Exynos4412 boards (Trats2, Odroid U3) after enabling L2 cache in
56b60b8bce4a ("ARM: 8265/1: dts: exynos4: Add nodes for L2 cache
controller") the second suspend to RAM failed. First suspend worked fine
but the next one hang just after powering down of secondary CPUs (system
consumed energy as it would be running but was not responsive).
The issue was caused by enabling delayed reset assertion for CPU0 just
after issuing power down of cores. This was introduced for Exynos4 in
13cfa6c4f7fa ("ARM: EXYNOS: Fix CPU idle clock down after CPU off").
The whole behavior is not well documented but after checking with vendor
code this should be done like this (on Exynos4):
1. Enable delayed reset assertion when system is running (for all CPUs).
2. Disable delayed reset assertion before suspending the system.
This can be done after powering off secondary CPUs.
3. Re-enable the delayed reset assertion when system is resumed.
Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Fixes: 13cfa6c4f7fa ("ARM: EXYNOS: Fix CPU idle clock down after CPU off")
Cc: <stable@vger.kernel.org>
Tested-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Tested-by: Chanwoo Choi <cw00.choi@samsung.com>
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This patch add spec file to generate odroid-xu3 kernel-headers by GBS.
Signed-off-by: Inha Song <ideal.song@samsung.com>
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This patch updates odroid configs to Linux 4.0 for tizen.
Signed-off-by: Inha Song <ideal.song@samsung.com>
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This patch adds smack permissive mode.
Signed-off-by: Chanho Park <chanho61.park@samsung.com>
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Need only CLK_G3D gate clock for mali and use clk_mali name to control
the clock from mali core codes.
Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com>
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