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authorBastian Hecht <hechtb@googlemail.com>2012-05-14 14:14:42 +0200
committerDavid Woodhouse <David.Woodhouse@intel.com>2012-07-06 18:17:03 +0100
commitaa32d1f0601ac2f5f69520175b8d2cea42caa025 (patch)
tree1af0988ca731f7c669d636b37086ea1042553f7e /include/linux/mtd
parent3c7ea4eccfd2e209ba666d217a2993b8a084a429 (diff)
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mtd: sh_flctl: Use different OOB layout
The flctl hardware has changed and a new OOB layout must be adapted for 2KiB page size NAND chips when using hardware ECC. The related bit fields ECCPOS[0-2] are gone — the bits are marked as reserved now in the datasheet. As there are no official users of the hardware ECC so far, they are completely removed. Signed-off-by: Bastian Hecht <hechtb@gmail.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Diffstat (limited to 'include/linux/mtd')
-rw-r--r--include/linux/mtd/sh_flctl.h4
1 files changed, 0 insertions, 4 deletions
diff --git a/include/linux/mtd/sh_flctl.h b/include/linux/mtd/sh_flctl.h
index 2daa43e17039..3feaae062feb 100644
--- a/include/linux/mtd/sh_flctl.h
+++ b/include/linux/mtd/sh_flctl.h
@@ -49,7 +49,6 @@
#define FLERRADR(f) (f->reg + 0x98)
/* FLCMNCR control bits */
-#define ECCPOS2 (0x1 << 25)
#define _4ECCCNTEN (0x1 << 24)
#define _4ECCEN (0x1 << 23)
#define _4ECCCORRECT (0x1 << 22)
@@ -59,9 +58,6 @@
#define QTSEL_E (0x1 << 17)
#define ENDIAN (0x1 << 16) /* 1 = little endian */
#define FCKSEL_E (0x1 << 15)
-#define ECCPOS_00 (0x00 << 12)
-#define ECCPOS_01 (0x01 << 12)
-#define ECCPOS_02 (0x02 << 12)
#define ACM_SACCES_MODE (0x01 << 10)
#define NANWF_E (0x1 << 9)
#define SE_D (0x1 << 8) /* Spare area disable */