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| author | Hari Kanigeri <h-kanigeri2@ti.com> | 2010-08-20 13:50:18 +0000 |
|---|---|---|
| committer | Tony Lindgren <tony@atomide.com> | 2010-10-05 10:22:13 -0700 |
| commit | 0fa035e52373386381fcdfbd506e32eac0c662f0 (patch) | |
| tree | 54096bf2eaa7f9d9ffa55c05a63711ee7f063900 /arch/tile | |
| parent | 3c729087d4312a4a1fa1a8b674fd9c8050cfc3db (diff) | |
| download | linux-exynos-0fa035e52373386381fcdfbd506e32eac0c662f0.tar.gz linux-exynos-0fa035e52373386381fcdfbd506e32eac0c662f0.tar.bz2 linux-exynos-0fa035e52373386381fcdfbd506e32eac0c662f0.zip | |
omap: iommu-load cam register before flushing the entry
The flush_iotlb_page is not loading the cam register before flushing
the cam entry. This causes wrong entry to be flushed out from the TLB, and
if the entry happens to be a locked TLB entry it would lead to MMU faults.
The fix is to load the cam register with the address to be flushed before
flushing the TLB entry.
Signed-off-by: Hari Kanigeri <h-kanigeri2@ti.com>
Acked-by: Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch/tile')
0 files changed, 0 insertions, 0 deletions