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authorMarek Szyprowski <m.szyprowski@samsung.com>2019-05-15 12:58:27 +0200
committerMarek Szyprowski <m.szyprowski@samsung.com>2019-05-15 12:58:37 +0200
commit8d40f3e556f9473254b6ac1dc0c0f564f1cdcd08 (patch)
tree28a293a2463cfc7bee0e675abdcad522b77134e9 /arch/arm
parent493d0bdbcf660d92a31c4ca492beb6eabb5e47b1 (diff)
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ARM: defconfig: enable I-Cache line size workaround on Exynos systemssubmit/tizen/20190611.014400accepted/tizen/unified/20190611.110428
All Exynos big.LITTLE system suffer from I-Cache line size mismatch between CPU cores, so enable workaround for it in exynos_defconfig and tizen_odroid_defconfig. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Change-Id: I0f324a5832e1ef47999f7b8d4ddd4a29db0ee176
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/configs/exynos_defconfig1
-rw-r--r--arch/arm/configs/tizen_odroid_defconfig1
2 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm/configs/exynos_defconfig b/arch/arm/configs/exynos_defconfig
index 93c5182c91a9..24c619357249 100644
--- a/arch/arm/configs/exynos_defconfig
+++ b/arch/arm/configs/exynos_defconfig
@@ -10,6 +10,7 @@ CONFIG_PARTITION_ADVANCED=y
CONFIG_ARCH_EXYNOS=y
CONFIG_ARCH_EXYNOS3=y
CONFIG_EXYNOS5420_MCPM=y
+CONFIG_CPU_ICACHE_MISMATCH_WORKAROUND=y
CONFIG_SMP=y
CONFIG_BIG_LITTLE=y
CONFIG_NR_CPUS=8
diff --git a/arch/arm/configs/tizen_odroid_defconfig b/arch/arm/configs/tizen_odroid_defconfig
index 73e5a96b2dd2..17d76057ae12 100644
--- a/arch/arm/configs/tizen_odroid_defconfig
+++ b/arch/arm/configs/tizen_odroid_defconfig
@@ -22,6 +22,7 @@ CONFIG_ARCH_EXYNOS=y
CONFIG_ARCH_EXYNOS3=y
CONFIG_EXYNOS5420_MCPM=y
# CONFIG_ARM_ERRATA_643719 is not set
+CONFIG_CPU_ICACHE_MISMATCH_WORKAROUND=y
CONFIG_SMP=y
CONFIG_BIG_LITTLE=y
CONFIG_NR_CPUS=8