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| author | Robin Murphy <robin.murphy@arm.com> | 2016-04-13 18:12:59 +0100 |
|---|---|---|
| committer | Will Deacon <will.deacon@arm.com> | 2016-05-03 18:23:02 +0100 |
| commit | f0cfffc48cac516e37711786227f6808491913a5 (patch) | |
| tree | 889f2264c6e081e8778db9396b5a7c6adc4ebf37 /Documentation/arm64 | |
| parent | e086d912d4d78781652669618e7fb01a4d466703 (diff) | |
| download | linux-exynos-f0cfffc48cac516e37711786227f6808491913a5.tar.gz linux-exynos-f0cfffc48cac516e37711786227f6808491913a5.tar.bz2 linux-exynos-f0cfffc48cac516e37711786227f6808491913a5.zip | |
iommu/arm-smmu: Work around MMU-500 prefetch errata
MMU-500 erratum #841119 is tickled by a particular set of circumstances
interacting with the next-page prefetcher. Since said prefetcher is
quite dumb and actually detrimental to performance in some cases (by
causing unwanted TLB evictions for non-sequential access patterns), we
lose very little by turning it off, and what we gain is a guarantee that
the erratum is never hit.
As a bonus, the same workaround will also prevent erratum #826419 once
v7 short descriptor support is implemented.
CC: Catalin Marinas <catalin.marinas@arm.com>
CC: Will Deacon <will.deacon@arm.com>
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Diffstat (limited to 'Documentation/arm64')
| -rw-r--r-- | Documentation/arm64/silicon-errata.txt | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/Documentation/arm64/silicon-errata.txt b/Documentation/arm64/silicon-errata.txt index 806f91cdd45d..c6938e50e71f 100644 --- a/Documentation/arm64/silicon-errata.txt +++ b/Documentation/arm64/silicon-errata.txt @@ -53,6 +53,7 @@ stable kernels. | ARM | Cortex-A57 | #832075 | ARM64_ERRATUM_832075 | | ARM | Cortex-A57 | #852523 | N/A | | ARM | Cortex-A57 | #834220 | ARM64_ERRATUM_834220 | +| ARM | MMU-500 | #841119,#826419 | N/A | | | | | | | Cavium | ThunderX ITS | #22375, #24313 | CAVIUM_ERRATUM_22375 | | Cavium | ThunderX GICv3 | #23154 | CAVIUM_ERRATUM_23154 | |