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authorAndrzej Hajda <a.hajda@samsung.com>2016-11-18 10:14:19 +0100
committerInki Dae <inki.dae@samsung.com>2016-12-13 18:47:03 -0800
commitfa7185d4219ea85690c07de42e4b62e4bfd9d933 (patch)
tree6da435fcef3374da957a98777ea7ae048e22f913
parent86407312bd742693790476b0c64f0e523b953afc (diff)
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drm/bridge/sii8620: limit supported modes to MHL1/2 modes
MHL3 modes are unstable on MHL3 dongle working in compatibility mode. The patch denies them until full MHL3 mode is supported. Change-Id: I0e18ce16e6194c346dde8a67a864feb452cf7b12 Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
-rw-r--r--drivers/gpu/drm/bridge/sil-sii8620.c22
1 files changed, 5 insertions, 17 deletions
diff --git a/drivers/gpu/drm/bridge/sil-sii8620.c b/drivers/gpu/drm/bridge/sil-sii8620.c
index cb0de123fa16..1ef5924f75bf 100644
--- a/drivers/gpu/drm/bridge/sil-sii8620.c
+++ b/drivers/gpu/drm/bridge/sil-sii8620.c
@@ -29,7 +29,9 @@
#include "sil-sii8620.h"
-#define VAL_RX_HDMI_CTRL2_DEFVAL VAL_RX_HDMI_CTRL2_IDLE_CNT(3)
+#define VAL_RX_HDMI_CTRL2_DEFVAL VAL_RX_HDMI_CTRL2_IDLE_CNT(3)
+#define MHL1_MAX_CLOCK 74250
+#define MHL3_MAX_CLOCK 300000
enum sii8620_mode {
CM_DISCONNECTED,
@@ -1468,24 +1470,10 @@ bool sii8620_mode_fixup(struct drm_bridge *bridge,
const struct drm_display_mode *mode,
struct drm_display_mode *adjusted_mode)
{
- struct sii8620 *ctx = bridge_to_sii8620(bridge);
- bool ret = false;
- int max_clock = 74250;
-
- mutex_lock(&ctx->lock);
-
if (mode->flags & DRM_MODE_FLAG_INTERLACE)
- goto out;
-
- if (ctx->devcap[MHL_DCAP_VID_LINK_MODE] & MHL_DCAP_VID_LINK_PPIXEL)
- max_clock = 300000;
+ return false;
- ret = mode->clock <= max_clock;
-
-out:
- mutex_unlock(&ctx->lock);
-
- return ret;
+ return mode->clock <= MHL1_MAX_CLOCK;
}
static void sii8620_mhl_worker(struct work_struct *work)