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| author | Jaehoon Chung <jh80.chung@samsung.com> | 2016-12-16 10:34:06 +0900 |
|---|---|---|
| committer | Seung-Woo Kim <sw0312.kim@samsung.com> | 2017-03-08 02:47:10 -0800 |
| commit | 76e387140700ef93682ab989128c8ad90c0dfd54 (patch) | |
| tree | f5cd79dcd0813de6e71595d297b60265e53f0b31 | |
| parent | 1e5231c842b0733d63c9ae7d4e22b8de8aa63d02 (diff) | |
| download | linux-exynos-76e387140700ef93682ab989128c8ad90c0dfd54.tar.gz linux-exynos-76e387140700ef93682ab989128c8ad90c0dfd54.tar.bz2 linux-exynos-76e387140700ef93682ab989128c8ad90c0dfd54.zip | |
pci: exynos5433: use the bit name intead of magic number
It can be checked wether link is up or not with XMLH_LINKUP(bit[4]).
According to Designware PCI Expreess Reference Manual(v3.22a),
XMLH_LINK_UP bit is used "LTSSM reports PHY link up".
Change-Id: I85dc5258471b5976ecd429e273d1edb1be08e13a
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
| -rw-r--r-- | drivers/pci/host/pci-exynos5433.c | 10 |
1 files changed, 4 insertions, 6 deletions
diff --git a/drivers/pci/host/pci-exynos5433.c b/drivers/pci/host/pci-exynos5433.c index 196ae318c485..d684e11ecb9b 100644 --- a/drivers/pci/host/pci-exynos5433.c +++ b/drivers/pci/host/pci-exynos5433.c @@ -58,6 +58,7 @@ struct exynos_pcie { #define IRQ_MSI_ENABLE BIT(2) #define PCIE_IRQ_EN_SPECIAL 0x014 #define PCIE_SW_WAKE 0x018 +#define PCIE_BUS_EN BIT(1) #define PCIE_APP_INIT_RESET 0x028 #define PCIE_APP_LTSSM_ENABLE 0x02c #define PCIE_ELBI_LTSSM_DISABLE 0x0 @@ -66,6 +67,7 @@ struct exynos_pcie { #define PCIE_APP_REQ_EXIT_L1 0x040 #define PCIE_APPS_PM_XMT_TURNOFF 0x04c #define PCIE_ELBI_RDLH_LINKUP 0x074 +#define PCIE_ELBI_XMLH_LINKUP BIT(4) #define PCIE_AUX_PM_EN 0x0A4 #define AUX_PM_DISABLE 0x0 #define AUX_PM_ENABLE 0x1 @@ -266,7 +268,7 @@ static void exynos_pcie_assert_phy_reset(struct pcie_port *pp) val = exynos_pcie_readl(ep->elbi_base, PCIE_SW_WAKE); - val &= ~(0x1 << 1); + val &= ~PCIE_BUS_EN; exynos_pcie_writel(ep->elbi_base, val, PCIE_SW_WAKE); } @@ -353,12 +355,8 @@ static int exynos_pcie_link_up(struct pcie_port *pp) u32 val; val = exynos_pcie_readl(ep->elbi_base, PCIE_ELBI_RDLH_LINKUP); - val &= 0x1f; - if (val >= 0x0d && val <= 0x15) - return 1; - - return 0; + return (val & PCIE_ELBI_XMLH_LINKUP); } static int exynos_pcie_host_init(struct pcie_port *pp) |