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| author | Hoegeun Kwon <hoegeun.kwon@samsung.com> | 2016-08-17 15:54:51 +0900 |
|---|---|---|
| committer | Seung-Woo Kim <sw0312.kim@samsung.com> | 2016-08-19 20:05:45 -0700 |
| commit | 10ffe63eadb2d7c2148671ada183bb70d2b622a1 (patch) | |
| tree | a0cf091c06b85c85a2fae131cd22c378a3dcfe5a | |
| parent | 4764f911066e0b28b2d27d094a5cc5a4c8f0cc11 (diff) | |
| download | linux-exynos-10ffe63eadb2d7c2148671ada183bb70d2b622a1.tar.gz linux-exynos-10ffe63eadb2d7c2148671ada183bb70d2b622a1.tar.bz2 linux-exynos-10ffe63eadb2d7c2148671ada183bb70d2b622a1.zip | |
clk: samsung: set SPI0 ioclk and slck as ignore unused
There is no one who handles the ioclk and sclk for the SPI0 bus,
in order to be able to use the SPI 0 bus, set them as ignore
unused by using the CLK_IGNORE_UNUSED flag in the gate
declaration.
The Exynos5433 SoC needs to have all the clocks enabled, they get
all disabled even if one of them is disabled.
Change-Id: I57a625f20c40b4d76046da1a8caf5976454dda1b
Signed-off-by: Andi Shyti <andi.shyti@samsung.com>
Signed-off-by: Hoegeun Kwon <hoegeun.kwon@samsung.com>
| -rw-r--r-- | drivers/clk/samsung/clk-exynos5433.c | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/drivers/clk/samsung/clk-exynos5433.c b/drivers/clk/samsung/clk-exynos5433.c index 697bc914ee22..3151c5c13578 100644 --- a/drivers/clk/samsung/clk-exynos5433.c +++ b/drivers/clk/samsung/clk-exynos5433.c @@ -1785,7 +1785,8 @@ static struct samsung_gate_clock peric_gate_clks[] __initdata = { ENABLE_SCLK_PERIC, 12, CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0), GATE(CLK_SCLK_IOCLK_SPI0, "sclk_ioclk_spi0", "ioclk_spi0_clk_in", - ENABLE_SCLK_PERIC, 11, CLK_SET_RATE_PARENT, 0), + ENABLE_SCLK_PERIC, 11, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0), GATE(CLK_SCLK_IOCLK_I2S1_BCLK, "sclk_ioclk_i2s1_bclk", "ioclk_i2s1_bclk_in", ENABLE_SCLK_PERIC, 10, CLK_SET_RATE_PARENT, 0), @@ -1800,7 +1801,7 @@ static struct samsung_gate_clock peric_gate_clks[] __initdata = { GATE(CLK_SCLK_SPI1, "sclk_spi1", "sclk_spi1_peric", ENABLE_SCLK_PERIC, 4, CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0), GATE(CLK_SCLK_SPI0, "sclk_spi0", "sclk_spi0_peric", ENABLE_SCLK_PERIC, - 3, CLK_SET_RATE_PARENT, 0), + 3, CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0), GATE(CLK_SCLK_UART2, "sclk_uart2", "sclk_uart2_peric", ENABLE_SCLK_PERIC, 2, CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0), |