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From 143103659b069afb92881584f7f3d777a6d8ee6a Mon Sep 17 00:00:00 2001
From: Younghwan Joo <yhwan.joo@samsung.com>
Date: Thu, 15 Nov 2012 21:02:27 +0900
Subject: [PATCH 0052/1302] ARM: EXYNOS: change the value of
EXYNOS4X12_ISP_LOWPWR
This patch is to fix the value of EXYNOS4X12_ISP_LOWPWR register
to zero at AFTR mode. It ensure the sub selection mux of mcuisp400
and isp200 reset a default position after power down
Signed-off-by: Younghwan Joo <yhwan.joo@samsung.com>
Signed-off-by: JaeYong Shin <jy2.shin@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: MyungJoo Ham <myungjoo.ham@samsung.com>
---
arch/arm/mach-exynos/pmu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-exynos/pmu.c b/arch/arm/mach-exynos/pmu.c
index 97d6885..21cef18 100644
--- a/arch/arm/mach-exynos/pmu.c
+++ b/arch/arm/mach-exynos/pmu.c
@@ -140,7 +140,7 @@ static struct exynos_pmu_conf exynos4x12_pmu_config[] = {
{ S5P_CMU_RESET_MFC_LOWPWR, { 0x1, 0x0, 0x0 } },
{ S5P_CMU_RESET_G3D_LOWPWR, { 0x1, 0x0, 0x0 } },
{ S5P_CMU_RESET_LCD0_LOWPWR, { 0x1, 0x0, 0x0 } },
- { S5P_CMU_RESET_ISP_LOWPWR, { 0x1, 0x0, 0x0 } },
+ { S5P_CMU_RESET_ISP_LOWPWR, { 0x0, 0x0, 0x0 } },
{ S5P_CMU_RESET_MAUDIO_LOWPWR, { 0x1, 0x1, 0x0 } },
{ S5P_CMU_RESET_GPS_LOWPWR, { 0x1, 0x0, 0x0 } },
{ S5P_TOP_BUS_LOWPWR, { 0x3, 0x0, 0x0 } },
--
1.8.3.2
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