summaryrefslogtreecommitdiff
path: root/arch/arm/boot/dts/exynos4x12.dtsi
blob: 474a9fca111e17666acfd5e3634ed09a67ee17d4 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
/*
 * Samsung's Exynos4x12 SoCs device tree source
 *
 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
 *		http://www.samsung.com
 *
 * Samsung's Exynos4x12 SoCs device nodes are listed in this file. Exynos4x12
 * based board files can include this file and provide values for board specfic
 * bindings.
 *
 * Note: This file does not include device nodes for all the controllers in
 * Exynos4x12 SoC. As device tree coverage for Exynos4x12 increases, additional
 * nodes can be added to this file.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
*/

/include/ "exynos4.dtsi"
/include/ "exynos4x12-pinctrl.dtsi"

/ {
	aliases {
		pinctrl0 = &pinctrl_0;
		pinctrl1 = &pinctrl_1;
		pinctrl2 = &pinctrl_2;
		pinctrl3 = &pinctrl_3;
		fimc-lite0 = &fimc_lite_0;
		fimc-lite1 = &fimc_lite_1;
	};

	pd_isp: isp-power-domain@10023CA0 {
		compatible = "samsung,exynos4210-pd";
		reg = <0x10023CA0 0x20>;
	};

	combiner:interrupt-controller@10440000 {
		interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
			     <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
			     <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
			     <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>,
			     <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>;
	};

	cache-controller@0x10502000 {
		arm,data-latency = <1 2 0>;
	};

	clock: clock-controller@0x10030000 {
		compatible = "samsung,exynos4412-clock";
		reg = <0x10030000 0x20000>;
		#clock-cells = <1>;
	};

	pinctrl_0: pinctrl@11400000 {
		compatible = "samsung,exynos4x12-pinctrl";
		reg = <0x11400000 0x1000>;
		interrupts = <0 47 0>;
	};

	pinctrl_1: pinctrl@11000000 {
		compatible = "samsung,exynos4x12-pinctrl";
		reg = <0x11000000 0x1000>;
		interrupts = <0 46 0>;

		wakup_eint: wakeup-interrupt-controller {
			compatible = "samsung,exynos4210-wakeup-eint";
			interrupt-parent = <&gic>;
			interrupts = <0 32 0>;
		};
	};

	amba {
		mdma1: mdma@12850000 {
			clocks = <&clock 350>;
		};
	};

	mshc@12550000 {
		compatible = "samsung,exynos4412-dw-mshc";
		reg = <0x12550000 0x1000>;
		interrupts = <0 77 0>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&clock 301>, <&clock 149>;
		clock-names = "biu", "ciu";
	};

	pinctrl_2: pinctrl@03860000 {
		compatible = "samsung,exynos4x12-pinctrl";
		reg = <0x03860000 0x1000>;
		interrupt-parent = <&combiner>;
		interrupts = <10 0>;
	};

	pinctrl_3: pinctrl@106E0000 {
		compatible = "samsung,exynos4x12-pinctrl";
		reg = <0x106E0000 0x1000>;
		interrupts = <0 72 0>;
	};

	g2d: g2d@10800000 {
		compatible = "samsung,exynos4212-g2d";
		reg = <0x10800000 0x1000>;
		interrupts = <0 89 0>;
		clocks = <&clock 177>, <&clock 277>;
		clock-names = "sclk_fimg2d", "fimg2d";
		samsung,power-domain = <&pd_lcd0>;
		iommu = <&sysmmu_g2d>;
		status = "disabled";
	};

	sysmmu_g2d: sysmmu@10A40000{
		compatible = "samsung,exynos4210-sysmmu";
		reg = <0x10A40000 0x1000>;
		interrupt-parent = <&combiner>;
		interrupt-names = "sysmmu-g2d";
		interrupts = <4 7>;
		clocks = <&clock 280>, <&clock 277>;
		clock-names = "sysmmu", "master";
		status = "ok";
	};

	jpeg-codec@11840000 {
		compatible = "samsung,exynos4212-jpeg";
	};

	sysmmu_fimc_isp: sysmmu@12260000 {
		compatible = "samsung,exynos4210-sysmmu";
		reg = <0x12260000 0x1000>;
		interrupt-parent = <&combiner>;
		interrupt-names = "sysmmu-fimc_isp";
		interrupts = <16 2>;
		clock-names = "sysmmu";
		clocks = <&clock 362>;
		status = "ok";
	};

	sysmmu_fimc_drc: sysmmu@12270000 {
		compatible = "samsung,exynos4210-sysmmu";
		reg = <0x12270000 0x1000>;
		interrupt-parent = <&combiner>;
		interrupt-names = "sysmmu-fimc_drc";
		interrupts = <16 3>;
		clock-names = "sysmmu";
		clocks = <&clock 363>;
		status = "ok";
	};

	sysmmu_fimc_fd: sysmmu@122A0000 {
		compatible = "samsung,exynos4210-sysmmu";
		reg = <0x122A0000 0x1000>;
		interrupt-parent = <&combiner>;
		interrupt-names = "sysmmu-fimc_fd";
		interrupts = <16 4>;
		clock-names = "sysmmu";
		clocks = <&clock 364>;
		status = "ok";
	};

	sysmmu_fimc_mcuctl: sysmmu@122B0000 {
		compatible = "samsung,exynos4210-sysmmu";
		reg = <0x122B0000 0x1000>;
		interrupt-parent = <&combiner>;
		interrupt-names = "sysmmu-fimc_mcuctl";
		interrupts = <16 5>;
		clock-names = "sysmmu";
		clocks = <&clock 376>;
		status = "ok";
	};

	sysmmu_fimc_lite0: sysmmu@123B0000 {
		compatible = "samsung,exynos4210-sysmmu";
		reg = <0x123B0000 0x1000>;
		interrupt-parent = <&combiner>;
		interrupt-names = "sysmmu-fimc_lite0";
		interrupts = <16 0>;
		clock-names = "sysmmu", "master";
		clocks = <&clock 366>, <&clock 353>;
		samsung,power-domain = <&pd_isp>;
		status = "ok";
	};

	sysmmu_fimc_lite1: sysmmu@123C0000 {
		compatible = "samsung,exynos4210-sysmmu";
		reg = <0x123C0000 0x1000>;
		interrupt-parent = <&combiner>;
		interrupt-names = "sysmmu-fimc_lite1";
		interrupts = <16 1>;
		clock-names = "sysmmu", "master";
		clocks = <&clock 365>, <&clock 354>;
		samsung,power-domain = <&pd_isp>;
		status = "ok";
	};

	exynos-usbphy@125B0000 {
		compatible = "samsung,exynos4x12-usb2-phy";
		samsung,sysreg-phandle = <&sys_reg>;
	};

	camera {
		clocks = <&clock 132>, <&clock 133>, <&clock 351>, <&clock 352>,
		         <&clock 388>, <&clock 389>, <&clock 17>;
		clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0",
			    "pxl_async1", "mux_cam0", "mux_cam1", "parent";

		fimc_0: fimc@11800000 {
			compatible = "samsung,exynos4212-fimc";
			clocks = <&clock 256>, <&clock 128>, <&clock 384>, <&clock 17>;
			clock-names = "fimc", "sclk_fimc", "mux", "parent";
			samsung,pix-limits = <4224 8192 1920 4224>;
			samsung,mainscaler-ext;
			samsung,isp-wb;
			samsung,cam-if;
		};

		fimc_1: fimc@11810000 {
			compatible = "samsung,exynos4212-fimc";
			clocks = <&clock 257>, <&clock 129>, <&clock 385>, <&clock 17>;
			clock-names = "fimc", "sclk_fimc", "mux", "parent";
			samsung,pix-limits = <4224 8192 1920 4224>;
			samsung,mainscaler-ext;
			samsung,isp-wb;
			samsung,cam-if;
		};

		fimc_2: fimc@11820000 {
			compatible = "samsung,exynos4212-fimc";
			clocks = <&clock 258>, <&clock 130>, <&clock 386>, <&clock 17>;
			clock-names = "fimc", "sclk_fimc", "mux", "parent";
			samsung,pix-limits = <4224 8192 1920 4224>;
			samsung,mainscaler-ext;
			samsung,isp-wb;
			samsung,lcd-wb;
			samsung,cam-if;
		};

		fimc_3: fimc@11830000 {
			compatible = "samsung,exynos4212-fimc";
			clocks = <&clock 259>, <&clock 131>, <&clock 387>, <&clock 17>;
			clock-names = "fimc", "sclk_fimc", "mux", "parent";
			samsung,pix-limits = <1920 8192 1366 1920>;
			samsung,rotators = <0>;
			samsung,mainscaler-ext;
			samsung,isp-wb;
			samsung,lcd-wb;
		};

		csis_0: csis@11880000 {
			clocks = <&clock 260>, <&clock 134>, <&clock 390>, <&clock 17>;
			clock-names = "csis", "sclk_csis", "mux", "parent";
		};

		csis_1: csis@11890000 {
			clocks = <&clock 261>, <&clock 135>, <&clock 391>, <&clock 17>;
			clock-names = "csis", "sclk_csis", "mux", "parent";
		};

		fimc_is: fimc-is@12000000 {
			compatible = "samsung,exynos4212-fimc-is", "simple-bus";
			reg = <0x12000000 0x260000>;
			interrupts = <0 90 0>, <0 95 0>;
			samsung,power-domain = <&pd_isp>;
			clocks = <&clock 353>, <&clock 354>, <&clock 355>,
				<&clock 356>, <&clock 342>, <&clock 17>,
				<&clock 357>, <&clock 358>, <&clock 359>,
				<&clock 360>, <&clock 450>,<&clock 451>,
				<&clock 452>, <&clock 453>, <&clock 382>,
				<&clock 13>, <&clock 454>, <&clock 395>,
				<&clock 455>;
			clock-names = "lite0", "lite1", "ppmuispx",
				      "ppmuispmx", "sysreg", "mpll",
				      "isp", "drc", "fd",
				      "mcuisp", "ispdiv0", "ispdiv1",
				      "mcuispdiv0", "mcuispdiv1", "uart",
				      "aclk200", "div_aclk200", "aclk400mcuisp",
				      "div_aclk400mcuisp";

			status = "disabled";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;


			fimc_lite_0: fimc-lite@12390000 {
				compatible = "samsung,exynos4212-fimc-lite";
				reg = <0x12390000 0x1000>;
				interrupts = <0 105 0>;
				clocks = <&clock 353>;
				clock-names = "flite";
				status = "disabled";
				iommu = <&sysmmu_fimc_lite0>;
			};

			fimc_lite_1: fimc-lite@123A0000 {
				compatible = "samsung,exynos4212-fimc-lite";
				reg = <0x123A0000 0x1000>;
				interrupts = <0 106 0>;
				clocks = <&clock 354>;
				clock-names = "flite";
				status = "disabled";
				iommu = <&sysmmu_fimc_lite1>;
			};

			pmu {
				reg = <0x10020000 0x3000>;
			};

			i2c1_isp: i2c-isp@12140000 {
				compatible = "samsung,exynos4212-i2c-isp";
				reg = <0x12130000 0x100>;
				clocks = <&clock 370>;
				clock-names = "i2c_isp";
				#address-cells = <1>;
				#size-cells = <0>;
			};
		};
	};

	gpu@13000000 {
		compatible = "samsung,exynos4x12-g3d";
		reg = <0x13001000 0x200>,
			<0x13000000 0x100>, <0x13003000 0x100>,
			<0x13008000 0x1100>, <0x13004000 0x100>,
			<0x1300a000 0x1100>, <0x13005000 0x100>,
			<0x1300c000 0x1100>, <0x13006000 0x100>,
			<0x1300e000 0x1100>, <0x13007000 0x100>;
		interrupts = <0 127 0>, <0 122 0>, <0 123 0>, <0 118 0>,
				<0 124 0>, <0 119 0>, <0 125 0>, <0 120 0>,
				<0 126 0>, <0 121 0>;
		clock-names = "sclk_vpll", "mout_g3d1", "mout_g3d", "sclk_g3d";
		clocks = <&clock 11>, <&clock 393>, <&clock 394>, <&clock 172>;
		samsung,power-domain = <&pd_g3d>;
		status = "disabled";
	};

	cpufreq {
		compatible = "samsung,exynos-cpufreq";
		clocks = <&clock 12>, <&clock 19>, <&clock 18>, <&clock 20>;
		clock-names = "arm_clk", "mout_core", "mout_mpll_user_c",
								"mout_apll";
		status = "disabled";
	};

	tmu@100C0000 {
		compatible = "samsung,exynos4412-tmu";
		interrupt-parent = <&combiner>;
		reg = <0x100C0000 0x100>;
		interrupts = <2 4>;
		clocks = <&clock 383>;
		clock-names = "tmu_apbif";
		status = "disabled";
	};

	rotator@12810000 {
		compatible = "samsung,exynos4212-rotator";
	};

	busfreq@0 {
		compatible = "samsung,exynos4x12-busfreq";
		reg = <0x106A0000 0x2000>, <0x106B0000 0x2000>,
		clocks = <&clock 414>, <&clock 415>;
		clock-names = "ppmudmc0", "ppmudmc1";
		status = "disabled";
	};
};