1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
|
/*
* Samsung's Exynos4210 SoC device tree source
*
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com
* Copyright (c) 2010-2011 Linaro Ltd.
* www.linaro.org
*
* Samsung's Exynos4210 SoC device nodes are listed in this file. Exynos4210
* based board files can include this file and provide values for board specfic
* bindings.
*
* Note: This file does not include device nodes for all the controllers in
* Exynos4210 SoC. As device tree coverage for Exynos4210 increases, additional
* nodes can be added to this file.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/include/ "exynos4.dtsi"
/include/ "exynos4210-pinctrl.dtsi"
/ {
compatible = "samsung,exynos4210";
aliases {
pinctrl0 = &pinctrl_0;
pinctrl1 = &pinctrl_1;
pinctrl2 = &pinctrl_2;
};
pd_lcd1: lcd1-power-domain@10023CA0 {
compatible = "samsung,exynos4210-pd";
reg = <0x10023CA0 0x20>;
};
gic:interrupt-controller@10490000 {
cpu-offset = <0x8000>;
};
combiner:interrupt-controller@10440000 {
samsung,combiner-nr = <16>;
interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
<0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
<0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
<0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>;
};
cache-controller@0x10502000 {
arm,data-latency = <1 1 0>;
};
mct@10050000 {
compatible = "samsung,exynos4210-mct";
reg = <0x10050000 0x800>;
interrupt-controller;
#interrups-cells = <2>;
interrupt-parent = <&mct_map>;
interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
<4 0>, <5 0>;
clocks = <&clock 3>, <&clock 344>;
clock-names = "fin_pll", "mct";
mct_map: mct-map {
#interrupt-cells = <2>;
#address-cells = <0>;
#size-cells = <0>;
interrupt-map = <0x0 0 &gic 0 57 0>,
<0x1 0 &gic 0 69 0>,
<0x2 0 &combiner 12 6>,
<0x3 0 &combiner 12 7>,
<0x4 0 &gic 0 42 0>,
<0x5 0 &gic 0 48 0>;
};
};
clock: clock-controller@0x10030000 {
compatible = "samsung,exynos4210-clock";
reg = <0x10030000 0x20000>;
#clock-cells = <1>;
};
pmu {
compatible = "arm,cortex-a9-pmu";
interrupt-parent = <&combiner>;
interrupts = <2 2>, <3 2>;
};
pinctrl_0: pinctrl@11400000 {
compatible = "samsung,exynos4210-pinctrl";
reg = <0x11400000 0x1000>;
interrupts = <0 47 0>;
};
pinctrl_1: pinctrl@11000000 {
compatible = "samsung,exynos4210-pinctrl";
reg = <0x11000000 0x1000>;
interrupts = <0 46 0>;
wakup_eint: wakeup-interrupt-controller {
compatible = "samsung,exynos4210-wakeup-eint";
interrupt-parent = <&gic>;
interrupts = <0 32 0>;
};
};
pinctrl_2: pinctrl@03860000 {
compatible = "samsung,exynos4210-pinctrl";
reg = <0x03860000 0x1000>;
};
tmu@100C0000 {
compatible = "samsung,exynos4210-tmu";
interrupt-parent = <&combiner>;
reg = <0x100C0000 0x100>;
interrupts = <2 4>;
};
g2d@12800000 {
compatible = "samsung,s5pv210-g2d";
reg = <0x12800000 0x1000>;
interrupts = <0 89 0>;
status = "disabled";
iommu = <&sysmmu_g2d>;
};
sysmmu_g2d: sysmmu@12A20000 {
compatible = "samsung,exynos4210-sysmmu";
reg = <0x12A20000 0x1000>;
interrupt-parent = <&combiner>;
interrupt-names = "sysmmu-g2d";
interrupts = <4 7>;
clock-names = "sysmmu";
clocks = <&clock 280>;
samsung,power-domain = <&pd_lcd0>;
status = "ok";
};
sysmmu_fimd1: sysmmu@12220000 {
compatible = "samsung,exynos4210-sysmmu";
interrupt-parent = <&combiner>;
interrupt-names = "sysmmu-fimd1";
reg = <0x12220000 0x1000>;
interrupts = <5 3>;
clock-names = "sysmmu";
clocks = <&clock 291>;
samsung,power-domain = <&pd_lcd1>;
status = "ok";
};
camera {
clocks = <&clock 132>, <&clock 133>, <&clock 351>, <&clock 352>,
<&clock 388>, <&clock 389>, <&clock 9>;
clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0",
"pxl_async1", "mux_cam0", "mux_cam1", "parent";
fimc_0: fimc@11800000 {
clocks = <&clock 256>, <&clock 128>, <&clock 384>, <&clock 9>;
clock-names = "fimc", "sclk_fimc", "mux", "parent";
samsung,pix-limits = <4224 8192 1920 4224>;
samsung,mainscaler-ext;
samsung,cam-if;
};
fimc_1: fimc@11810000 {
clocks = <&clock 257>, <&clock 129>, <&clock 385>, <&clock 9>;
clock-names = "fimc", "sclk_fimc", "mux", "parent";
samsung,pix-limits = <4224 8192 1920 4224>;
samsung,mainscaler-ext;
samsung,cam-if;
};
fimc_2: fimc@11820000 {
clocks = <&clock 258>, <&clock 130>, <&clock 386>, <&clock 9>;
clock-names = "fimc", "sclk_fimc", "mux", "parent";
samsung,pix-limits = <4224 8192 1920 4224>;
samsung,mainscaler-ext;
samsung,lcd-wb;
};
fimc_3: fimc@11830000 {
clocks = <&clock 259>, <&clock 131>, <&clock 387>, <&clock 9>;
clock-names = "fimc", "sclk_fimc", "mux", "parent";
samsung,pix-limits = <1920 8192 1366 1920>;
samsung,rotators = <0>;
samsung,mainscaler-ext;
samsung,lcd-wb;
};
csis_0: csis@11880000 {
clocks = <&clock 260>, <&clock 134>, <&clock 390>, <&clock 9>;
clock-names = "csis", "sclk_csis", "mux", "parent";
};
csis_1: csis@11890000 {
clocks = <&clock 261>, <&clock 135>, <&clock 391>, <&clock 9>;
clock-names = "csis", "sclk_csis", "mux", "parent";
};
};
gpu@13000000 {
compatible = "samsung,exynos4210-g3d";
reg = <0x13001000 0x200>,
<0x13000000 0x100>, <0x13003000 0x100>,
<0x13008000 0x1100>, <0x13004000 0x100>,
<0x1300a000 0x1100>, <0x13005000 0x100>,
<0x1300c000 0x1100>, <0x13006000 0x100>,
<0x1300e000 0x1100>, <0x13007000 0x100>;
interrupts = <0 127 0>, <0 122 0>, <0 123 0>, <0 118 0>,
<0 124 0>, <0 119 0>, <0 125 0>, <0 120 0>,
<0 126 0>, <0 121 0>;
clock-names = "sclk_vpll", "mout_g3d1", "mout_g3d", "sclk_g3d";
clocks = <&clock 11>, <&clock 393>, <&clock 394>, <&clock 172>;
samsung,power-domain = <&pd_g3d>;
status = "disabled";
};
cpufreq {
compatible = "samsung,exynos-cpufreq";
clocks = <&clock 12>, <&clock 19>, <&clock 9>, <&clock 20>;
clock-names = "armclk", "moutcore", "mout_mpll", "mout_apll";
status = "disabled";
};
exynos_phy: exynos-phy@10020000 {
compatible = "exynos4210-phy";
reg = <0x10020000 0x1000>;
#phy-cells = <1>;
};
hdmi: hdmi@12D00000 {
phys = <&exynos_phy 0>;
phy-names = "hdmiphy";
compatible = "samsung,exynos4210-hdmi";
};
exynos_usbphy: exynos-usbphy@125B0000 {
compatible = "samsung,exynos4210-usbphy";
reg = <0x125B0000 0x100 0x10020704 0x0c 0x1001021c 0x4>;
clocks = <&clock 305>, <&clock 2>, <&clock 2>, <&clock 2>,
<&clock 2>;
clock-names = "phy", "device", "host", "hsic0", "hsic1";
status = "disabled";
#phy-cells = <1>;
};
};
|
