/*
 * Samsung's Exynos3250 SoC device tree source
 *
 * Copyright (c) 2014 Samsung Electronics Co., Ltd.
 *		http://www.samsung.com
 *
 * Samsung's Exynos3250 SoC device nodes are listed in this file. Exynos3250
 * based board files can include this file and provide values for board specfic
 * bindings.
 *
 * Note: This file does not include device nodes for all the controllers in
 * Exynos3250 SoC. As device tree coverage for Exynos3250 increases, additional
 * nodes can be added to this file.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include "skeleton.dtsi"
#include <dt-bindings/clock/exynos3250.h>

/ {
	compatible = "samsung,exynos3250";
	interrupt-parent = <&gic>;

	aliases {
		pinctrl0 = &pinctrl_0;
		pinctrl1 = &pinctrl_1;
		mshc0 = &mshc_0;
		mshc1 = &mshc_1;
		spi0 = &spi_0;
		spi1 = &spi_1;
		i2c0 = &i2c_0;
		i2c1 = &i2c_1;
		i2c2 = &i2c_2;
		i2c3 = &i2c_3;
		i2c4 = &i2c_4;
		i2c5 = &i2c_5;
		i2c6 = &i2c_6;
		i2c7 = &i2c_7;
		csis0 = &csis_0;
		fimc-lite0 = &fimc_lite_0;
		fimc-lite1 = &fimc_lite_1;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0>;
			clock-frequency = <1000000000>;
		};

		cpu1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <1>;
			clock-frequency = <1000000000>;
		};
	};

	soc: soc {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		fixed-rate-clocks {
			#address-cells = <1>;
			#size-cells = <0>;

			xusbxti: clock@0 {
				compatible = "fixed-clock";
				#address-cells = <1>;
				#size-cells = <0>;
				reg = <0>;
				clock-frequency = <0>;
				#clock-cells = <0>;
				clock-output-names = "xusbxti";
			};

			xxti: clock@1 {
				compatible = "fixed-clock";
				reg = <1>;
				clock-frequency = <0>;
				#clock-cells = <0>;
				clock-output-names = "xxti";
			};

			xtcxo: clock@2 {
				compatible = "fixed-clock";
				reg = <2>;
				clock-frequency = <0>;
				#clock-cells = <0>;
				clock-output-names = "xtcxo";
			};
		};

		sysram@02020000 {
			compatible = "mmio-sram";
			reg = <0x02020000 0x40000>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 0x02020000 0x40000>;

			smp-sysram@0 {
				compatible = "samsung,exynos4210-sysram";
				reg = <0x0 0x1000>;
			};

			smp-sysram@3f000 {
				compatible = "samsung,exynos4210-sysram-ns";
				reg = <0x3f000 0x1000>;
			};
		};

		chipid@10000000 {
			compatible = "samsung,exynos4210-chipid";
			reg = <0x10000000 0x100>;
		};

		busfreq_mif: busfreq@106A0000 {
			compatible = "samsung,exynos3250-busfreq-mif";
			reg = <0x106A0000 0x2000>, <0x106B0000 0x2000>;
			regs-name = "PPMU_DMC0", "PPMU_DMC1";
			status = "disabled";
		};

		busfreq_int: busfreq@0x116A0000 {
			compatible = "samsung,exynos3250-busfreq-int";
			reg = <0x116A0000 0x2000>, <0x112A0000 0x2000>;
			regs-name = "PPMU_LEFT", "PPMU_RIGHT";
			clocks = <&cmu CLK_PPMULEFT>, <&cmu CLK_PPMURIGHT>;
			clock-names = "ppmuleft", "ppmuright";
			status = "disabled";
		};

		sys_reg: syscon@10010000 {
			compatible = "samsung,exynos3-sysreg", "syscon";
			reg = <0x10010000 0x400>;
		};

		pmu_system_controller: system-controller@10020000 {
			compatible = "samsung,exynos3250-pmu", "syscon";
			reg = <0x10020000 0x4000>;
		};

		clkout: clock-controller@10020A00 {
			compatible = "samsung,exynos3250-clkout";
			reg = <0x10020A00 0x4>;
			#clock-cells = <1>;
		};

		pd_cam: cam-power-domain@10023C00 {
			compatible = "samsung,exynos4210-pd";
			reg = <0x10023C00 0x20>;
		};

		pd_mfc: mfc-power-domain@10023C40 {
			compatible = "samsung,exynos4210-pd";
			reg = <0x10023C40 0x20>;
		};

		pd_g3d: g3d-power-domain@10023C60 {
			compatible = "samsung,exynos4210-pd";
			reg = <0x10023C60 0x20>;
		};

		pd_lcd0: lcd0-power-domain@10023C80 {
			compatible = "samsung,exynos4210-pd";
			reg = <0x10023C80 0x20>;
		};

		pd_isp: isp-power-domain@10023CA0 {
			compatible = "samsung,exynos4210-pd";
			reg = <0x10023CA0 0x20>;
		};

		cmu: clock-controller@10030000 {
			compatible = "samsung,exynos3250-cmu";
			reg = <0x10030000 0x18000>;
			#clock-cells = <1>;
		};

		cmu_isp: clock-controller@10048000 {
			compatible = "samsung,exynos3250-cmu-isp";
			reg = <0x10048000 0x1000>;
			#clock-cells = <1>;
		};

		rtc: rtc@10070000 {
			compatible = "samsung,s3c6410-rtc";
			reg = <0x10070000 0x100>;
			interrupts = <0 73 0>, <0 74 0>;
			status = "disabled";
		};

		tmu: tmu@100C0000 {
			compatible = "samsung,exynos3250-tmu";
			interrupt-parent = <&gic>;
			reg = <0x100C0000 0x100>;
			interrupts = <0 216 0>;
			clocks = <&cmu CLK_TMU_APBIF>;
			clock-names = "tmu_apbif";
			status = "disabled";
		};

		gic: interrupt-controller@10481000 {
			compatible = "arm,cortex-a15-gic";
			#interrupt-cells = <3>;
			interrupt-controller;
			reg = <0x10481000 0x1000>,
			      <0x10482000 0x1000>,
			      <0x10484000 0x2000>,
			      <0x10486000 0x2000>;
			interrupts = <1 9 0xf04>;
		};

		fimc_is: fimc-is@12180000 {
			compatible = "samsung,exynos3250-fimc-is";
			reg = <0x12180000 0x10000>; /* MCUCTL */
			interrupts = <0 196 0>, <0 197 0>;
			clocks = <&cmu_isp CLK_ISP>,
				<&cmu_isp CLK_DRC>,
				<&cmu_isp CLK_FD>,
				<&cmu_isp CLK_SCALERC>,
				<&cmu_isp CLK_PPMUISPMX>,
				<&cmu_isp CLK_PPMUISPX>,
				<&cmu_isp CLK_MPWM_ISP>,
				<&cmu_isp CLK_MCUISP>,
				<&cmu_isp CLK_DIV_MPWM>, <&cmu_isp CLK_DIV_ISP0>,
				<&cmu_isp CLK_DIV_ISP1>, <&cmu_isp CLK_DIV_MCUISP0>,
				<&cmu_isp CLK_DIV_MCUISP1>,
				<&cmu CLK_CAM1>,
				<&cmu_isp CLK_SPI1_ISP>,
				<&cmu_isp CLK_SPI0_ISP>,
				<&cmu_isp CLK_UART_ISP>,
				<&cmu CLK_ASYNCAXIM>,
				<&cmu CLK_MOUT_ACLK_400_MCUISP_SUB>,
				<&cmu CLK_DIV_ACLK_400_MCUISP>,
				<&cmu CLK_MOUT_ACLK_400_MCUISP>,
				<&cmu CLK_MOUT_ACLK_266_0>,
				<&cmu CLK_MOUT_ACLK_266>,
				<&cmu CLK_DIV_ACLK_266>,
				<&cmu CLK_MOUT_ACLK_266_SUB>,
				<&cmu CLK_DIV_MPLL_PRE>,
				<&cmu CLK_FIN_PLL>;
			clock-names = "isp",
				     "drc",
				     "fd",
				     "scalerc",
				     "ppmuispmx",
				     "ppmuispx",
				     "mpwm_isp",
				     "mcu_isp",
				     "isp_divmpwm", "isp_div0",
				     "isp_div1", "mcu_isp_div0",
				     "mcu_isp_div1",
				     "cam1",
				     "spi1_isp",
				     "spi0_isp",
				     "uart_isp",
				     "asyncaxim",
				     "mout_aclk400_mcuisp_sub",
				     "div_aclk400_mcuisp",
				     "mout_aclk400_mcuisp",
				     "mout_aclk266_0",
				     "mout_aclk266",
				     "div_aclk266",
				     "mout_aclk266_sub",
				     "div_mpll_pre",
				     "fin_pll";
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <1>;
			#clock-cells = <1>;
			ranges;

			samsung,pmu = <&pmu_system_controller>;
			samsung,power-domain = <&pd_isp>;

			fimc_lite_0: fimc-lite@120a0000 {
				compatible = "samsung,exynos3250-fimc-lite";
				reg = <0x120a0000 0x1000>;
				interrupts = <0 198 0>;
				clocks = <&cmu_isp CLK_LITE0>;
				clock-names = "flite";
				status = "disabled";
				samsung,power-domain = <&pd_isp>;
			};

			fimc_lite_1: fimc-lite@120b0000 {
				compatible = "samsung,exynos3250-fimc-lite";
				reg = <0x120b0000 0x1000>;
				interrupts = <0 199 0>;
				clocks = <&cmu_isp CLK_LITE1>;
				clock-names = "flite";
				status = "disabled";
				samsung,power-domain = <&pd_isp>;
			};

			csis_0: csis@120c0000 {
				compatible = "samsung,exynos3250-csis";
				reg = <0x120c0000 0x4000>;
				interrupts = <0 165 0>;
				clocks = <&cmu CLK_CSIS0>;
				clock-names = "csis";
				bus-width = <2>;
				samsung,power-domain = <&pd_cam>;
				phys = <&mipi_phy 0>;
				phy-names = "csis";
				status = "disabled";
			};

			i2c0_isp: i2c-isp@12130000 {
				compatible = "samsung,exynos4212-i2c-isp";
				reg = <0x12130000 0x100>;
				clocks = <&cmu_isp CLK_I2C0_ISP>;
				clock-names = "i2c_isp";
				#address-cells = <1>;
				#size-cells = <0>;
			};
		};

		mct@10050000 {
			compatible = "samsung,exynos4210-mct";
			reg = <0x10050000 0x800>;
			interrupts = <0 218 0>, <0 219 0>, <0 220 0>, <0 221 0>,
				     <0 223 0>, <0 226 0>, <0 227 0>, <0 228 0>;
			clocks = <&cmu CLK_FIN_PLL>, <&cmu CLK_MCT>;
			clock-names = "fin_pll", "mct";
		};

		pinctrl_1: pinctrl@11000000 {
			compatible = "samsung,exynos3250-pinctrl";
			reg = <0x11000000 0x1000>;
			interrupts = <0 225 0>;

			wakeup-interrupt-controller {
				compatible = "samsung,exynos4210-wakeup-eint";
				interrupt-parent = <&gic>;
				interrupts = <0 48 0>;
			};
		};

		pinctrl_0: pinctrl@11400000 {
			compatible = "samsung,exynos3250-pinctrl";
			reg = <0x11400000 0x1000>;
			interrupts = <0 240 0>;
		};

		exynos_drm_gsc1: gsc@11850000 {
			compatible = "samsung,exynos3250-drm-gsc";
			reg = <0x11850000 0x1000>;
			clocks = <&cmu CLK_GSCALER0>;
			clock-names = "gscl";
			interrupts = <0 167 0>;
			iommu = <&smmu_gsc0>;
			samsung,power-domain = <&pd_cam>;
		};

		exynos_drm_gsc2: gsc@11860000 {
			compatible = "samsung,exynos3250-drm-gsc";
			reg = <0x11860000 0x1000>;
			clocks = <&cmu CLK_GSCALER1>;
			clock-names = "gscl";
			interrupts = <0 168 0>;
			iommu = <&smmu_gsc1>;
			samsung,power-domain = <&pd_cam>;
		};

		smmu_gsc0: sysmmu@11a20000 {
			compatible = "samsung,exynos4210-sysmmu";
			reg = <0x11a20000 0x1000>;
			interrupts = <0 152 0>, <0 157 0>;
			clocks = <&cmu CLK_SMMUGSCALER0>, <&cmu CLK_GSCALER0>;
			clock-names = "sysmmu", "master";
			samsung,power-domain = <&pd_cam>;
		};

		smmu_gsc1: sysmmu@11a30000 {
			compatible = "samsung,exynos4210-sysmmu";
			reg = <0x11a30000 0x1000>;
			interrupts = <0 153 0>, <0 158 0>;
			clocks = <&cmu CLK_SMMUGSCALER1>, <&cmu CLK_GSCALER1>;
			clock-names = "sysmmu", "master";
			samsung,power-domain = <&pd_cam>;
		};

		mshc_0: mshc@12510000 {
			compatible = "samsung,exynos5250-dw-mshc";
			reg = <0x12510000 0x1000>;
			interrupts = <0 142 0>;
			clocks = <&cmu CLK_SDMMC0>, <&cmu CLK_SCLK_MMC0>;
			clock-names = "biu", "ciu";
			fifo-depth = <0x80>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		mshc_1: mshc@12520000 {
			compatible = "samsung,exynos5250-dw-mshc";
			reg = <0x12520000 0x1000>;
			interrupts = <0 143 0>;
			clocks = <&cmu CLK_SDMMC1>, <&cmu CLK_SCLK_MMC1>;
			clock-names = "biu", "ciu";
			fifo-depth = <0x80>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		amba {
			compatible = "arm,amba-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			interrupt-parent = <&gic>;
			ranges;

			pdma0: pdma@12680000 {
				compatible = "arm,pl330", "arm,primecell";
				reg = <0x12680000 0x1000>;
				interrupts = <0 138 0>;
				clocks = <&cmu CLK_PDMA0>;
				clock-names = "apb_pclk";
				#dma-cells = <1>;
				#dma-channels = <8>;
				#dma-requests = <32>;
			};

			pdma1: pdma@12690000 {
				compatible = "arm,pl330", "arm,primecell";
				reg = <0x12690000 0x1000>;
				interrupts = <0 139 0>;
				clocks = <&cmu CLK_PDMA1>;
				clock-names = "apb_pclk";
				#dma-cells = <1>;
				#dma-channels = <8>;
				#dma-requests = <32>;
			};
		};

		adc: adc@126C0000 {
			compatible = "samsung,exynos3250-adc-v2";
			reg = <0x126C0000 0x100>, <0x10020718 0x4>;
			interrupts = <0 137 0>;
			clock-names = "adc", "sclk_adc";
			clocks = <&cmu CLK_TSADC>, <&cmu CLK_SCLK_TSADC>;
			#io-channel-cells = <1>;
			io-channel-ranges;
			status = "disabled";
		};

		dsi_0: dsi@11C80000 {
			compatible = "samsung,exynos3250-mipi-dsi";
			reg = <0x11C80000 0x10000>;
			interrupts = <0 83 0>;
			samsung,phy-type = <0>;
			samsung,power-domain = <&pd_lcd0>;
			phys = <&mipi_phy 1>;
			phy-names = "dsim";
			clocks = <&cmu CLK_DSIM0>, <&cmu CLK_SCLK_MIPI0>;
			clock-names = "bus_clk", "pll_clk";
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		fimd: fimd@11c00000 {
			compatible = "samsung,exynos3250-fimd";
			reg = <0x11c00000 0x30000>;
			interrupt-names = "fifo", "vsync", "lcd_sys";
			interrupts = <0 84 0>, <0 85 0>, <0 86 0>;
			clocks = <&cmu CLK_SCLK_FIMD0>, <&cmu CLK_FIMD0>;
			clock-names = "sclk_fimd", "fimd";
			samsung,power-domain = <&pd_lcd0>;
			samsung,sysreg = <&sys_reg>;
			status = "disabled";
			iommu = <&sysmmu_fimd0>;
		};

		mipi_phy: video-phy@10020710 {
			compatible = "samsung,s5pv210-mipi-video-phy";
			reg = <0x10020710 8>;
			#phy-cells = <1>;
		};

		sysmmu_fimd0: sysmmu@11E20000 {
			compatible = "samsung,exynos4210-sysmmu";
			reg = <0x11E20000 0x1000>;
			interrupt-names = "sysmmu-fimd0";
			interrupts = <0 80 0>, <0 81 0>;
			clock-names = "sysmmu", "master";
			clocks = <&cmu CLK_SMMUFIMD0>, <&cmu CLK_FIMD0>;
			samsung,power-domain = <&pd_lcd0>;
			status = "disabled";
		};

		hsotg: hsotg@12480000 {
			compatible = "samsung,s3c-hsotg";
			reg = <0x12480000 0x20000>;
			interrupts = <0 141 0>;
			clocks = <&cmu CLK_USBOTG>;
			clock-names = "otg";
			phys = <&exynos_usbphy 0>;
			phy-names = "device";
			status = "disabled";
		};

		exynos_usbphy: exynos-usbphy@125B0000 {
			compatible = "samsung,exynos3250-usb2-phy";
			reg = <0x125B0000 0x100>;
			samsung,pmureg-phandle = <&pmu_system_controller>;
			samsung,sysreg-phandle = <&sys_reg>;
			clocks = <&cmu CLK_USBOTG>, <&xusbxti>;
			clock-names = "phy", "ref";
			#phy-cells = <1>;
			status = "disabled";
		};

		gpu: gpu@13000000 {
			compatible = "samsung,exynos3250-g3d";
			reg = <0x13001000 0x200>,
			    <0x13000000 0x100>, <0x13003000 0x100>,
			    <0x13008000 0x1100>, <0x13004000 0x100>,
			    <0x1300a000 0x1100>, <0x13005000 0x100>;
			interrupts = <0 187 0>, <0 182 0>, <0 183 0>, <0 178 0>,
				   <0 184 0>, <0 179 0>;
			clock-names = "pll", "mux1", "mux2", "sclk", "smmu",
				"g3d";
			clocks = <&cmu CLK_DIV_MPLL_PRE>, <&cmu CLK_MOUT_G3D_0>,
					<&cmu CLK_MOUT_G3D>, <&cmu CLK_SCLK_G3D>,
					<&cmu CLK_SMMUG3D>, <&cmu CLK_G3D>;
			samsung,power-domain = <&pd_g3d>;
			status = "disabled";
	       };

		serial_0: serial@13800000 {
			compatible = "samsung,exynos4210-uart";
			reg = <0x13800000 0x100>;
			interrupts = <0 109 0>;
			clocks = <&cmu CLK_UART0>, <&cmu CLK_SCLK_UART0>;
			clock-names = "uart", "clk_uart_baud0";
			status = "disabled";
		};

		serial_1: serial@13810000 {
			compatible = "samsung,exynos4210-uart";
			reg = <0x13810000 0x100>;
			interrupts = <0 110 0>;
			clocks = <&cmu CLK_UART1>, <&cmu CLK_SCLK_UART1>;
			clock-names = "uart", "clk_uart_baud0";
			status = "disabled";
		};

		i2c_0: i2c@13860000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "samsung,s3c2440-i2c";
			reg = <0x13860000 0x100>;
			interrupts = <0 113 0>;
			clocks = <&cmu CLK_I2C0>;
			clock-names = "i2c";
			pinctrl-names = "default";
			pinctrl-0 = <&i2c0_bus>;
			status = "disabled";
		};

		i2c_1: i2c@13870000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "samsung,s3c2440-i2c";
			reg = <0x13870000 0x100>;
			interrupts = <0 114 0>;
			clocks = <&cmu CLK_I2C1>;
			clock-names = "i2c";
			pinctrl-names = "default";
			pinctrl-0 = <&i2c1_bus>;
			status = "disabled";
		};

		i2c_2: i2c@13880000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "samsung,s3c2440-i2c";
			reg = <0x13880000 0x100>;
			interrupts = <0 115 0>;
			clocks = <&cmu CLK_I2C2>;
			clock-names = "i2c";
			pinctrl-names = "default";
			pinctrl-0 = <&i2c2_bus>;
			status = "disabled";
		};

		i2c_3: i2c@13890000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "samsung,s3c2440-i2c";
			reg = <0x13890000 0x100>;
			interrupts = <0 116 0>;
			clocks = <&cmu CLK_I2C3>;
			clock-names = "i2c";
			pinctrl-names = "default";
			pinctrl-0 = <&i2c3_bus>;
			status = "disabled";
		};

		i2c_4: i2c@138A0000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "samsung,s3c2440-i2c";
			reg = <0x138A0000 0x100>;
			interrupts = <0 117 0>;
			clocks = <&cmu CLK_I2C4>;
			clock-names = "i2c";
			pinctrl-names = "default";
			pinctrl-0 = <&i2c4_bus>;
			status = "disabled";
		};

		i2c_5: i2c@138B0000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "samsung,s3c2440-i2c";
			reg = <0x138B0000 0x100>;
			interrupts = <0 118 0>;
			clocks = <&cmu CLK_I2C5>;
			clock-names = "i2c";
			pinctrl-names = "default";
			pinctrl-0 = <&i2c5_bus>;
			status = "disabled";
		};

		i2c_6: i2c@138C0000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "samsung,s3c2440-i2c";
			reg = <0x138C0000 0x100>;
			interrupts = <0 119 0>;
			clocks = <&cmu CLK_I2C6>;
			clock-names = "i2c";
			pinctrl-names = "default";
			pinctrl-0 = <&i2c6_bus>;
			status = "disabled";
		};

		i2c_7: i2c@138D0000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "samsung,s3c2440-i2c";
			reg = <0x138D0000 0x100>;
			interrupts = <0 120 0>;
			clocks = <&cmu CLK_I2C7>;
			clock-names = "i2c";
			pinctrl-names = "default";
			pinctrl-0 = <&i2c7_bus>;
			status = "disabled";
		};

		spi_0: spi@13920000 {
			compatible = "samsung,exynos4210-spi";
			reg = <0x13920000 0x100>;
			interrupts = <0 121 0>;
			dmas = <&pdma0 7>, <&pdma0 6>;
			dma-names = "tx", "rx";
			#address-cells = <1>;
			#size-cells = <0>;
			clocks = <&cmu CLK_SPI0>, <&cmu CLK_SCLK_SPI0>;
			clock-names = "spi", "spi_busclk0";
			samsung,spi-src-clk = <0>;
			pinctrl-names = "default";
			pinctrl-0 = <&spi0_bus>;
			status = "disabled";
		};

		spi_1: spi@13930000 {
			compatible = "samsung,exynos4210-spi";
			reg = <0x13930000 0x100>;
			interrupts = <0 122 0>;
			dmas = <&pdma1 7>, <&pdma1 6>;
			dma-names = "tx", "rx";
			#address-cells = <1>;
			#size-cells = <0>;
			clocks = <&cmu CLK_SPI1>, <&cmu CLK_SCLK_SPI1>;
			clock-names = "spi", "spi_busclk0";
			samsung,spi-src-clk = <0>;
			pinctrl-names = "default";
			pinctrl-0 = <&spi1_bus>;
			status = "disabled";
		};

		i2s2: i2s@13970000 {
			compatible = "samsung,i2s-v5";
			reg = <0x13970000 0x100>;
			interrupts = <0 126 0>;
			clocks = <&cmu CLK_I2S>, <&cmu CLK_SCLK_I2S>;
			clock-names = "iis", "i2s_opclk0";
			dmas = <&pdma0 14>, <&pdma0 13>;
			dma-names = "tx", "rx";
			samsung,no-muxpsr;
			pinctrl-0 = <&i2s2_bus>;
			pinctrl-names = "default";
			status = "disabled";
		};

		pwm: pwm@139D0000 {
			compatible = "samsung,exynos4210-pwm";
			reg = <0x139D0000 0x1000>;
			interrupts = <0 104 0>, <0 105 0>, <0 106 0>,
				     <0 107 0>, <0 108 0>;
			#pwm-cells = <3>;
			status = "disabled";
		};

		cpufreq: cpufreq {
			compatible = "samsung,exynos-cpufreq";
			clocks = <&cmu CLK_DIV_CORE2>,
				 <&cmu CLK_MOUT_CORE>,
			         <&cmu CLK_MOUT_MPLL_USER_C>,
				 <&cmu CLK_MOUT_APLL>;
			clock-names = "div_core2", "mout_core",
				      "mout_mpll_user_c", "mout_apll";
			status = "disabled";
		};

		pmu {
			compatible = "arm,cortex-a7-pmu";
			interrupts = <0 18 0>, <0 19 0>;
		};
	};
};


#include "exynos3250-pinctrl.dtsi"