From 35faa55cff56441477973e454f62408714f35cd3 Mon Sep 17 00:00:00 2001 From: Sebastian Andrzej Siewior Date: Thu, 15 Mar 2012 18:42:31 +0100 Subject: spi/fsl-espi: make the clock computation easier to read The -1 +1 thingy should probably do what DIV_ROUND_UP does. The 4 is 2 the "platform_clock => sysclock" and 2 from the computation part. The 64 is the same 4 times 16. Signed-off-by: Sebastian Andrzej Siewior Signed-off-by: Grant Likely --- drivers/spi/spi-fsl-espi.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers/spi/spi-fsl-espi.c') diff --git a/drivers/spi/spi-fsl-espi.c b/drivers/spi/spi-fsl-espi.c index d770f03705c..43350f99931 100644 --- a/drivers/spi/spi-fsl-espi.c +++ b/drivers/spi/spi-fsl-espi.c @@ -180,7 +180,7 @@ static int fsl_espi_setup_transfer(struct spi_device *spi, if ((mpc8xxx_spi->spibrg / hz) > 64) { cs->hw_mode |= CSMODE_DIV16; - pm = (mpc8xxx_spi->spibrg - 1) / (hz * 64) + 1; + pm = DIV_ROUND_UP(mpc8xxx_spi->spibrg, hz * 16 * 4); WARN_ONCE(pm > 16, "%s: Requested speed is too low: %d Hz. " "Will use %d Hz instead.\n", dev_name(&spi->dev), @@ -188,7 +188,7 @@ static int fsl_espi_setup_transfer(struct spi_device *spi, if (pm > 16) pm = 16; } else { - pm = (mpc8xxx_spi->spibrg - 1) / (hz * 4) + 1; + pm = DIV_ROUND_UP(mpc8xxx_spi->spibrg, hz * 4); } if (pm) pm--; -- cgit v1.2.3