From 08a183f02b5fef1cd78d27ffc8281fa96d79f814 Mon Sep 17 00:00:00 2001 From: Catalin Marinas Date: Tue, 14 Feb 2012 16:33:27 +0100 Subject: ARM: 7323/1: Do not allow ARM_LPAE on pre-ARMv7 architectures This patch expands the Kconfig dependencies for ARM_LPAE to not allow enabling when architectures other than ARMv7 are built into the kernel. Signed-off-by: Catalin Marinas Reported-by: Russell King Signed-off-by: Russell King --- arch/arm/mm/Kconfig | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig index 1a3ca248816..7edef912163 100644 --- a/arch/arm/mm/Kconfig +++ b/arch/arm/mm/Kconfig @@ -631,7 +631,8 @@ comment "Processor Features" config ARM_LPAE bool "Support for the Large Physical Address Extension" - depends on MMU && CPU_V7 + depends on MMU && CPU_32v7 && !CPU_32v6 && !CPU_32v5 && \ + !CPU_32v4 && !CPU_32v3 help Say Y if you have an ARMv7 processor supporting the LPAE page table format and you would like to access memory beyond the -- cgit v1.2.3 From 8e43a905dd574f54c5715d978318290ceafbe275 Mon Sep 17 00:00:00 2001 From: Rabin Vincent Date: Wed, 15 Feb 2012 16:01:42 +0100 Subject: ARM: 7325/1: fix v7 boot with lockdep enabled Bootup with lockdep enabled has been broken on v7 since b46c0f74657d ("ARM: 7321/1: cache-v7: Disable preemption when reading CCSIDR"). This is because v7_setup (which is called very early during boot) calls v7_flush_dcache_all, and the save_and_disable_irqs added by that patch ends up attempting to call into lockdep C code (trace_hardirqs_off()) when we are in no position to execute it (no stack, MMU off). Fix this by using a notrace variant of save_and_disable_irqs. The code already uses the notrace variant of restore_irqs. Reviewed-by: Nicolas Pitre Acked-by: Stephen Boyd Cc: Catalin Marinas Cc: stable@vger.kernel.org Signed-off-by: Rabin Vincent Signed-off-by: Russell King --- arch/arm/include/asm/assembler.h | 5 +++++ arch/arm/mm/cache-v7.S | 2 +- 2 files changed, 6 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/include/asm/assembler.h b/arch/arm/include/asm/assembler.h index 62f8095d46d..23371b17b23 100644 --- a/arch/arm/include/asm/assembler.h +++ b/arch/arm/include/asm/assembler.h @@ -137,6 +137,11 @@ disable_irq .endm + .macro save_and_disable_irqs_notrace, oldcpsr + mrs \oldcpsr, cpsr + disable_irq_notrace + .endm + /* * Restore interrupt state previously stored in a register. We don't * guarantee that this will preserve the flags. diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S index 7a24d39661f..a655d3da386 100644 --- a/arch/arm/mm/cache-v7.S +++ b/arch/arm/mm/cache-v7.S @@ -55,7 +55,7 @@ loop1: cmp r1, #2 @ see what cache we have at this level blt skip @ skip if no cache, or just i-cache #ifdef CONFIG_PREEMPT - save_and_disable_irqs r9 @ make cssr&csidr read atomic + save_and_disable_irqs_notrace r9 @ make cssr&csidr read atomic #endif mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr isb @ isb to sych the new cssr&csidr -- cgit v1.2.3 From 4272f98a1ae81709fc5c804c33c044064e419cd9 Mon Sep 17 00:00:00 2001 From: Javi Merino Date: Wed, 16 Nov 2011 12:36:39 +0100 Subject: ARM: 7164/3: PL330: Fix the size of the dst_cache_ctrl field dst_cache_ctrl affects bits 3, 1 and 0 of AWCACHE but it is a 3-bit field in the Channel Control Register (see Table 3-21 of the DMA-330 Technical Reference Manual) and should be programmed as such. Reference: <1320244259-10496-3-git-send-email-javi.merino@arm.com> Signed-off-by: Javi Merino Acked-by: Jassi Brar Signed-off-by: Russell King --- arch/arm/include/asm/hardware/pl330.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/include/asm/hardware/pl330.h b/arch/arm/include/asm/hardware/pl330.h index 575fa8186ca..c1821385abf 100644 --- a/arch/arm/include/asm/hardware/pl330.h +++ b/arch/arm/include/asm/hardware/pl330.h @@ -41,7 +41,7 @@ enum pl330_dstcachectrl { DCCTRL1, /* Bufferable only */ DCCTRL2, /* Cacheable, but do not allocate */ DCCTRL3, /* Cacheable and bufferable, but do not allocate */ - DINVALID1 = 8, + DINVALID1, /* AWCACHE = 0x1000 */ DINVALID2, DCCTRL6, /* Cacheable write-through, allocate on writes only */ DCCTRL7, /* Cacheable write-back, allocate on writes only */ -- cgit v1.2.3 From 46e33c606af8e0caeeca374103189663d877c0d6 Mon Sep 17 00:00:00 2001 From: Javi Merino Date: Wed, 15 Feb 2012 17:36:39 +0100 Subject: ARM: 7326/2: PL330: fix null pointer dereference in pl330_chan_ctrl() This fixes the thrd->req_running field being accessed before thrd is checked for null. The error was introduced in abb959f: ARM: 7237/1: PL330: Fix driver freeze Reference: <1326458191-23492-1-git-send-email-mans.rullgard@linaro.org> Cc: stable@kernel.org Signed-off-by: Mans Rullgard Acked-by: Javi Merino Signed-off-by: Russell King --- arch/arm/common/pl330.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/common/pl330.c b/arch/arm/common/pl330.c index d8e44a43047..ff3ad224482 100644 --- a/arch/arm/common/pl330.c +++ b/arch/arm/common/pl330.c @@ -1502,12 +1502,13 @@ int pl330_chan_ctrl(void *ch_id, enum pl330_chan_op op) struct pl330_thread *thrd = ch_id; struct pl330_dmac *pl330; unsigned long flags; - int ret = 0, active = thrd->req_running; + int ret = 0, active; if (!thrd || thrd->free || thrd->dmac->state == DYING) return -EINVAL; pl330 = thrd->dmac; + active = thrd->req_running; spin_lock_irqsave(&pl330->lock, flags); -- cgit v1.2.3 From fee6a3c33a8f137f39cd9997b0476411f73576c7 Mon Sep 17 00:00:00 2001 From: Olof Johansson Date: Wed, 15 Feb 2012 21:17:12 +0100 Subject: ARM: 7327/1: need to include asm/system.h in asm/processor.h For files that include asm/processor.h but not asm/system.h: arch/arm/mach-msm/include/mach/uncompress.h: In function 'putc': arch/arm/mach-msm/include/mach/uncompress.h:48:3: error: implicit declaration of function 'smp_mb' [-Werror=implicit-function-declaration] In this case, smp_mb() is from the cpu_relax() call in the msm putc(). It likely went uncaught when the uncompress.h change went in since the defconfig didn't enable that code path, but later changes (e76f4750f4: ARM: debug: arrange Kconfig options more logically) resulted in the option being on for msm_defconfig and thus exposed it. Signed-off-by: Olof Johansson Signed-off-by: Russell King --- arch/arm/include/asm/processor.h | 1 + 1 file changed, 1 insertion(+) (limited to 'arch') diff --git a/arch/arm/include/asm/processor.h b/arch/arm/include/asm/processor.h index ce280b8d613..cb8d638924f 100644 --- a/arch/arm/include/asm/processor.h +++ b/arch/arm/include/asm/processor.h @@ -22,6 +22,7 @@ #include #include #include +#include #ifdef __KERNEL__ #define STACK_TOP ((current->personality & ADDR_LIMIT_32BIT) ? \ -- cgit v1.2.3 From 910ba598c818243cf3de2f97e03c49948bbb0511 Mon Sep 17 00:00:00 2001 From: Santosh Shilimkar Date: Tue, 21 Feb 2012 10:24:22 +0100 Subject: ARM: 7336/1: smp_twd: Don't register CPUFREQ notifiers if local timers are not initialised Current ARM local timer code registers CPUFREQ notifiers even in case the twd_timer_setup() isn't called. That seems to be wrong and would eventually lead to kernel crash on the CPU frequency transitions on the SOCs where the local timer doesn't exist or broken because of hardware BUG. Fix it by testing twd_evt and *__this_cpu_ptr(twd_evt). The issue was observed with v3.3-rc3 and building an OMAP2+ kernel on OMAP3 SOC which doesn't have TWD. Below is the dump for reference : Unable to handle kernel paging request at virtual address 007e900 pgd = cdc20000 [007e9000] *pgd=00000000 Internal error: Oops: 5 [#1] SMP Modules linked in: CPU: 0 Not tainted (3.3.0-rc3-pm+debug+initramfs #9) PC is at twd_update_frequency+0x34/0x48 LR is at twd_update_frequency+0x10/0x48 pc : [] lr : [] psr: 60000093 sp : ce311dd8 ip : 00000000 fp : 00000000 r10: 00000000 r9 : 00000001 r8 : ce310000 r7 : c0440458 r6 : c00137f8 r5 : 00000000 r4 : c0947a74 r3 : 00000000 r2 : 007e9000 r1 : 00000000 r0 : 00000000 Flags: nZCv IRQs off FIQs on Mode SVC_32 ISA ARM Segment usr Control: 10c5387d Table: 8dc20019 DAC: 00000015 Process sh (pid: 599, stack limit = 0xce3102f8) Stack: (0xce311dd8 to 0xce312000) 1dc0: 6000c 1de0: 00000001 00000002 00000000 00000000 00000000 00000000 00000 1e00: ffffffff c093d8f0 00000000 ce311ebc 00000001 00000001 ce310 1e20: c001386c c0437c4c c0e95b60 c0e95ba8 00000001 c0e95bf8 ffff4 1e40: 00000000 00000000 c005ef74 ce310000 c0435cf0 ce311ebc 00000 1e60: ce352b40 0007a120 c08d5108 c08ba040 c08ba040 c005f030 00000 1e80: c08bc554 c032fe2c 0007a120 c08d4b64 ce352b40 c08d8618 ffff8 1ea0: c08ba040 c033364c ce311ecc c0433b50 00000002 ffffffea c0330 1ec0: 0007a120 0007a120 22222201 00000000 22222222 00000000 ce357 1ee0: ce3d6000 cdc2aed8 ce352ba0 c0470164 00000002 c032f47c 00034 1f00: c0331cac ce352b40 00000007 c032f6d0 ce352bbc 0003d090 c0930 1f20: c093d8bc c03306a4 00000007 ce311f80 00000007 cdc2aec0 ce358 1f40: ce8d20c0 00000007 b6fe5000 ce311f80 00000007 ce310000 0000c 1f60: c000de74 ce987400 ce8d20c0 b6fe5000 00000000 00000000 0000c 1f80: 00000000 00000000 001fbac8 00000000 00000007 001fbac8 00004 1fa0: c000df04 c000dd60 00000007 001fbac8 00000001 b6fe5000 00000 1fc0: 00000007 001fbac8 00000007 00000004 b6fe5000 00000000 00202 1fe0: 00000000 beb565f8 00101ffc 00008e8c 60000010 00000001 00000 [] (twd_update_frequency+0x34/0x48) from [] ) [] (smp_call_function_single+0x17c/0x1c8) from [] (twd_cpufreq_transition+0x24/0x30) from [) [] (notifier_call_chain+0x44/0x84) from [] () [] (__srcu_notifier_call_chain+0x70/0xa4) from [] (srcu_notifier_call_chain+0x18/0x20) from [] (cpufreq_notify_transition+0xc8/0x1b0) from [] (omap_target+0x1b4/0x28c) from [] (__cpuf) [] (__cpufreq_driver_target+0x50/0x64) from [] (cpufreq_set+0x78/0x98) from [] (store_sc) [] (store_scaling_setspeed+0x5c/0x74) from [) [] (store+0x58/0x74) from [] (sysfs_write_fi) [] (sysfs_write_file+0x80/0xb4) from [] (vfs) [] (vfs_write+0xa8/0x138) from [] (sys_write) [] (sys_write+0x40/0x6c) from [] (ret_fast_s) Code: e594300c e792210c e1a01000 e5840004 (e7930002) ---[ end trace 5da3b5167c1ecdda ]--- Reported-by: Kevin Hilman Acked-by: Marc Zyngier Tested-by: Kevin Hilman Signed-off-by: Santosh Shilimkar Signed-off-by: Russell King --- arch/arm/kernel/smp_twd.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/kernel/smp_twd.c b/arch/arm/kernel/smp_twd.c index 4285daa077b..7a79b24597b 100644 --- a/arch/arm/kernel/smp_twd.c +++ b/arch/arm/kernel/smp_twd.c @@ -129,7 +129,7 @@ static struct notifier_block twd_cpufreq_nb = { static int twd_cpufreq_init(void) { - if (!IS_ERR(twd_clk)) + if (twd_evt && *__this_cpu_ptr(twd_evt) && !IS_ERR(twd_clk)) return cpufreq_register_notifier(&twd_cpufreq_nb, CPUFREQ_TRANSITION_NOTIFIER); -- cgit v1.2.3 From e23e8c0690d2952dce53e712d01d5b2179f98b64 Mon Sep 17 00:00:00 2001 From: Myron Stowe Date: Tue, 7 Feb 2012 15:26:44 -0700 Subject: ARM/PCI: Remove ARM's duplicate definition of 'pcibios_max_latency' The patch series to re-factor PCI's 'latency timer' setup (re: http://marc.info/?l=linux-kernel&m=131983853831049&w=2) forgot to remove the ARM specific definition of 'pcibios_max_latency' once such had been moved into the pci core resulting in ARM related compile errors - drivers/built-in.o:(.data+0x230): multiple definition of `pcibios_max_latency' arch/arm/common/built-in.o:(.data+0x40c): first defined here make[1]: *** [vmlinux.o] Error 1 In the series, patch 2/16 (commit 168c8619fd8) converted the ARM specific version of 'pcibios_set_master()' to a non-inlined version. This was done in preperation for hosting it up into PCI's core, which was done in patch 10/16 (commit 96c5590058d) of the series (and where the removal of ARM's 'pcibios_max_latency' was overlooked). Reported-by: Russell King Signed-off-by: Myron Stowe Signed-off-by: Russell King --- arch/arm/common/it8152.c | 7 ------- 1 file changed, 7 deletions(-) (limited to 'arch') diff --git a/arch/arm/common/it8152.c b/arch/arm/common/it8152.c index d1bcd7b13eb..fb1f1cfce60 100644 --- a/arch/arm/common/it8152.c +++ b/arch/arm/common/it8152.c @@ -320,13 +320,6 @@ err0: return -EBUSY; } -/* - * If we set up a device for bus mastering, we need to check the latency - * timer as we don't have even crappy BIOSes to set it properly. - * The implementation is from arch/i386/pci/i386.c - */ -unsigned int pcibios_max_latency = 255; - /* ITE bridge requires setting latency timer to avoid early bus access termination by PCI bus master devices */ -- cgit v1.2.3 From 3ddd4d0c629f3d013aa1ab24bb0546dfe342ff94 Mon Sep 17 00:00:00 2001 From: Russell King Date: Wed, 15 Feb 2012 11:28:06 +0000 Subject: ARM: OMAP: fix voltage domain build errors with PM_OPP disabled The voltage domain code wants the voltage tables, which are in the opp*.c files. These files aren't built when PM_OPP is disabled, causing the following build errors at link time: twl-common.c:(.init.text+0x2e48): undefined reference to `omap34xx_vddmpu_volt_data' twl-common.c:(.init.text+0x2e4c): undefined reference to `omap34xx_vddcore_volt_data' twl-common.c:(.init.text+0x2e5c): undefined reference to `omap36xx_vddmpu_volt_data' twl-common.c:(.init.text+0x2e60): undefined reference to `omap36xx_vddcore_volt_data' twl-common.c:(.init.text+0x2830): undefined reference to `omap44xx_vdd_mpu_volt_data' twl-common.c:(.init.text+0x283c): undefined reference to `omap44xx_vdd_iva_volt_data' twl-common.c:(.init.text+0x2844): undefined reference to `omap44xx_vdd_core_volt_data' Acked-by: Kevin Hilman Signed-off-by: Russell King --- arch/arm/mach-omap2/voltagedomains3xxx_data.c | 2 ++ arch/arm/mach-omap2/voltagedomains44xx_data.c | 2 ++ 2 files changed, 4 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-omap2/voltagedomains3xxx_data.c b/arch/arm/mach-omap2/voltagedomains3xxx_data.c index c005e2f5e38..57db2038b23 100644 --- a/arch/arm/mach-omap2/voltagedomains3xxx_data.c +++ b/arch/arm/mach-omap2/voltagedomains3xxx_data.c @@ -108,6 +108,7 @@ void __init omap3xxx_voltagedomains_init(void) * XXX Will depend on the process, validation, and binning * for the currently-running IC */ +#ifdef CONFIG_PM_OPP if (cpu_is_omap3630()) { omap3_voltdm_mpu.volt_data = omap36xx_vddmpu_volt_data; omap3_voltdm_core.volt_data = omap36xx_vddcore_volt_data; @@ -115,6 +116,7 @@ void __init omap3xxx_voltagedomains_init(void) omap3_voltdm_mpu.volt_data = omap34xx_vddmpu_volt_data; omap3_voltdm_core.volt_data = omap34xx_vddcore_volt_data; } +#endif if (cpu_is_omap3517() || cpu_is_omap3505()) voltdms = voltagedomains_am35xx; diff --git a/arch/arm/mach-omap2/voltagedomains44xx_data.c b/arch/arm/mach-omap2/voltagedomains44xx_data.c index 4e11d022595..c3115f6853d 100644 --- a/arch/arm/mach-omap2/voltagedomains44xx_data.c +++ b/arch/arm/mach-omap2/voltagedomains44xx_data.c @@ -100,9 +100,11 @@ void __init omap44xx_voltagedomains_init(void) * XXX Will depend on the process, validation, and binning * for the currently-running IC */ +#ifdef CONFIG_PM_OPP omap4_voltdm_mpu.volt_data = omap44xx_vdd_mpu_volt_data; omap4_voltdm_iva.volt_data = omap44xx_vdd_iva_volt_data; omap4_voltdm_core.volt_data = omap44xx_vdd_core_volt_data; +#endif for (i = 0; voltdm = voltagedomains_omap4[i], voltdm; i++) voltdm->sys_clk.name = sys_clk_name; -- cgit v1.2.3 From 5180bb392a8aab5233e6db858ac1d8371533e20f Mon Sep 17 00:00:00 2001 From: Eric Paris Date: Tue, 21 Feb 2012 11:26:55 -0500 Subject: ARM/audit: include audit header and fix audit arch Both bugs being fixed were introduced in: 29ef73b7a823b77a7cd0bdd7d7cded3fb6c2587b Include linux/audit.h to fix below build errors: CC arch/arm/kernel/ptrace.o arch/arm/kernel/ptrace.c: In function 'syscall_trace': arch/arm/kernel/ptrace.c:919: error: implicit declaration of function 'audit_syscall_exit' arch/arm/kernel/ptrace.c:921: error: implicit declaration of function 'audit_syscall_entry' arch/arm/kernel/ptrace.c:921: error: 'AUDIT_ARCH_ARMEB' undeclared (first use in this function) arch/arm/kernel/ptrace.c:921: error: (Each undeclared identifier is reported only once arch/arm/kernel/ptrace.c:921: error: for each function it appears in.) make[1]: *** [arch/arm/kernel/ptrace.o] Error 1 make: *** [arch/arm/kernel] Error 2 This part of the patch is: Reported-by: Axel Lin Reported-by: Peter Ujfalusi (They both provided patches to fix it) This patch also (at the request of the list) fixes the fact that ARM has both LE and BE versions however the audit code was called as if it was always BE. If audit userspace were to try to interpret the bits it got from a LE system it would obviously do so incorrectly. Fix this by using the right arch flag on the right system. This part of the patch is: Reported-by: Russell King - ARM Linux Signed-off-by: Eric Paris Signed-off-by: Russell King --- arch/arm/kernel/ptrace.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/kernel/ptrace.c b/arch/arm/kernel/ptrace.c index e33870ff0ac..ede6443c34d 100644 --- a/arch/arm/kernel/ptrace.c +++ b/arch/arm/kernel/ptrace.c @@ -23,6 +23,7 @@ #include #include #include +#include #include #include @@ -904,6 +905,12 @@ long arch_ptrace(struct task_struct *child, long request, return ret; } +#ifdef __ARMEB__ +#define AUDIT_ARCH_NR AUDIT_ARCH_ARMEB +#else +#define AUDIT_ARCH_NR AUDIT_ARCH_ARM +#endif + asmlinkage int syscall_trace(int why, struct pt_regs *regs, int scno) { unsigned long ip; @@ -918,7 +925,7 @@ asmlinkage int syscall_trace(int why, struct pt_regs *regs, int scno) if (!ip) audit_syscall_exit(regs); else - audit_syscall_entry(AUDIT_ARCH_ARMEB, scno, regs->ARM_r0, + audit_syscall_entry(AUDIT_ARCH_NR, scno, regs->ARM_r0, regs->ARM_r1, regs->ARM_r2, regs->ARM_r3); if (!test_thread_flag(TIF_SYSCALL_TRACE)) -- cgit v1.2.3