From c4236d2e7913d18d058a018f0d19473eb6a11a3c Mon Sep 17 00:00:00 2001 From: Peter 'p2' De Schrijver Date: Mon, 20 Dec 2010 14:05:07 -0600 Subject: OMAP3630: PM: Disable L2 cache while invalidating L2 cache While coming out of MPU OSWR/OFF states, L2 controller is reseted. The reset behavior is implementation specific as per ARMv7 TRM and hence $L2 needs to be invalidated before it's use. Since the AUXCTRL register is also reconfigured, disable L2 cache before invalidating it and re-enables it afterwards. This is as per Cortex-A8 ARM documentation. Currently this is identified as being needed on OMAP3630 as the disable/enable is done from "public side" while, on OMAP3430, this is done in the "secure side". Cc: Kevin Hilman Cc: Tony Lindgren Acked-by: Jean Pihet Acked-by: Santosh Shilimkar [nm@ti.com: ported to 2.6.37-rc2, added hooks to enable the logic only on 3630] Signed-off-by: Nishanth Menon Signed-off-by: Eduardo Valentin Signed-off-by: Peter 'p2' De Schrijver Signed-off-by: Kevin Hilman --- arch/arm/mach-omap2/pm.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm/mach-omap2/pm.h') diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h index 8d9aa3e0f63..5e0bee96185 100644 --- a/arch/arm/mach-omap2/pm.h +++ b/arch/arm/mach-omap2/pm.h @@ -90,8 +90,10 @@ extern unsigned int omap34xx_cpu_suspend_sz; #if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3) extern u16 pm34xx_errata; #define IS_PM34XX_ERRATUM(id) (pm34xx_errata & (id)) +extern void enable_omap3630_toggle_l2_on_restore(void); #else #define IS_PM34XX_ERRATUM(id) 0 +static inline void enable_omap3630_toggle_l2_on_restore(void) { } #endif /* defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3) */ #endif -- cgit v1.2.3