From d72201391be54c3c43f9f34c2fb68bcb060d45df Mon Sep 17 00:00:00 2001 From: Donghwa Lee Date: Wed, 20 Aug 2014 10:03:51 +0900 Subject: drm: fimc: support ipp dynamic color range This patch support dynamic range for color space conversion. COLOR_RANGE_LIMITED: selects narrow -> Y(16 to 235), Cb/Cr(16 to 240) COLOR_RANGE_FULL: selects wide -> Y/Cb/Cr(0 to 255), Wide default Change-Id: I7bb62883b497b5b6869108247cc33b09c07f470e Signed-off-by: Donghwa Lee --- drivers/gpu/drm/exynos/exynos_drm_fimc.c | 15 ++++++++++++++- include/uapi/drm/exynos_drm.h | 10 ++++++++++ 2 files changed, 24 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimc.c b/drivers/gpu/drm/exynos/exynos_drm_fimc.c index 73c51363862..646bfe1bf02 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_fimc.c +++ b/drivers/gpu/drm/exynos/exynos_drm_fimc.c @@ -1081,6 +1081,7 @@ static int fimc_set_prescaler(struct fimc_context *ctx, struct fimc_scaler *sc, struct drm_exynos_pos *src, struct drm_exynos_pos *dst) { struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv; + struct drm_exynos_ipp_property *property = &ippdrv->c_node->property; u32 cfg, cfg_ext, shfactor; u32 pre_dst_width, pre_dst_height; u32 hfactor, vfactor; @@ -1124,6 +1125,7 @@ static int fimc_set_prescaler(struct fimc_context *ctx, struct fimc_scaler *sc, DRM_DEBUG_KMS("%s:hfactor[%d]vfactor[%d]\n", __func__, hfactor, vfactor); + sc->range = property->range; sc->hratio = (src_w << 14) / (dst_w << hfactor); sc->vratio = (src_h << 14) / (dst_h << vfactor); sc->up_h = (dst_w >= src_w) ? true : false; @@ -1163,9 +1165,20 @@ static void fimc_set_scaler(struct fimc_context *ctx, struct fimc_scaler *sc) EXYNOS_CISCCTRL_CSCR2Y_WIDE | EXYNOS_CISCCTRL_CSCY2R_WIDE); - if (sc->range) + switch (sc->range) { + case COLOR_RANGE_FULL: cfg |= (EXYNOS_CISCCTRL_CSCR2Y_WIDE | EXYNOS_CISCCTRL_CSCY2R_WIDE); + break; + case COLOR_RANGE_LIMITED: + cfg &= ~(EXYNOS_CISCCTRL_CSCR2Y_WIDE | + EXYNOS_CISCCTRL_CSCY2R_WIDE); + break; + default: + DRM_DEBUG_KMS("%s: out of YCbCr dynamic range for csc\n", + __func__); + break; + } if (sc->bypass) cfg |= EXYNOS_CISCCTRL_SCALERBYPASS; if (sc->up_h) diff --git a/include/uapi/drm/exynos_drm.h b/include/uapi/drm/exynos_drm.h index 01879bfa0b9..4b48799ada9 100644 --- a/include/uapi/drm/exynos_drm.h +++ b/include/uapi/drm/exynos_drm.h @@ -254,6 +254,12 @@ enum drm_exynos_ipp_cmd { IPP_CMD_MAX, }; +/* define of color range */ +enum drm_exynos_color_range { + COLOR_RANGE_LIMITED, /* Narrow: Y(16 to 235), Cb/Cr(16 to 240) */ + COLOR_RANGE_FULL, /* Wide: Y/Cb/Cr(0 to 255), Wide default */ +}; + /** * A structure for ipp property. * @@ -262,6 +268,8 @@ enum drm_exynos_ipp_cmd { * @ipp_id: id of ipp driver. * @prop_id: id of property. * @refresh_rate: refresh rate. + * @range: dynamic range for csc. + * @pad: just padding to be 64-bit aligned. */ struct drm_exynos_ipp_property { struct drm_exynos_ipp_config config[EXYNOS_DRM_OPS_MAX]; @@ -269,6 +277,8 @@ struct drm_exynos_ipp_property { __u32 ipp_id; __u32 prop_id; __u32 refresh_rate; + __u32 range; + __u32 pad; }; enum drm_exynos_ipp_buf_type { -- cgit v1.2.3