From 2f02c15a5d963007bd721d76f644c9491f6fec06 Mon Sep 17 00:00:00 2001 From: Aurelien Jarno Date: Tue, 11 Dec 2007 11:30:34 +0100 Subject: [MIPS] Kconfig fixes for BCM47XX platform The patch below fixes two problems for Kconfig on the BCM47xx platform: - arch/mips/bcm47xx/gpio.c uses ssb_extif_* functions. Selecting SSB_DRIVER_EXTIF makes sure those functions are available. - arch/mips/pci/pci.c needs, when enabled, platform specific functions, which are defined when SSB_PCICORE_HOSTMODE is enabled. Signed-off-by: Aurelien Jarno Signed-off-by: Ralf Baechle --- arch/mips/Kconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 291d368ffd2..b22c043b6ef 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -59,6 +59,8 @@ config BCM47XX select SYS_SUPPORTS_LITTLE_ENDIAN select SSB select SSB_DRIVER_MIPS + select SSB_DRIVER_EXTIF + select SSB_PCICORE_HOSTMODE if PCI select GENERIC_GPIO select SYS_HAS_EARLY_PRINTK select CFE -- cgit v1.2.3 From f6c0f32ee8d21e800097fc35ba8ab2b5a3b9bdfa Mon Sep 17 00:00:00 2001 From: Thomas Bogendoerfer Date: Sat, 12 Jan 2008 00:25:14 +0100 Subject: [MIPS] Cobalt: Fix ethernet interrupts for RaQ1 RAQ1 uses the same interrupt routing as Qube2. Signed-off-by: Thomas Bogendoerfer Signed-off-by: Ralf Baechle --- arch/mips/pci/fixup-cobalt.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/mips/pci/fixup-cobalt.c b/arch/mips/pci/fixup-cobalt.c index f7df1142912..9553b14002d 100644 --- a/arch/mips/pci/fixup-cobalt.c +++ b/arch/mips/pci/fixup-cobalt.c @@ -177,7 +177,7 @@ static char irq_tab_raq2[] __initdata = { int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) { - if (cobalt_board_id < COBALT_BRD_ID_QUBE2) + if (cobalt_board_id <= COBALT_BRD_ID_QUBE1) return irq_tab_qube1[slot]; if (cobalt_board_id == COBALT_BRD_ID_RAQ2) -- cgit v1.2.3 From c43756da94863395d5ee088659676029b3ae7191 Mon Sep 17 00:00:00 2001 From: Thomas Bogendoerfer Date: Sat, 12 Jan 2008 00:25:17 +0100 Subject: [MIPS] Cobalt: Qube1 has no serial port so don't use it Because Qube1 doesn't have a serial chip waiting for transmit fifo empty takes forever, which isn't a good idea. No prom_putchar/early console for Qube1 fixes this. Signed-off-by: Thomas Bogendoerfer Acked-by: Yoichi Yuasa Signed-off-by: Ralf Baechle --- arch/mips/cobalt/console.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/mips/cobalt/console.c b/arch/mips/cobalt/console.c index db330e81102..d1ba701c9dd 100644 --- a/arch/mips/cobalt/console.c +++ b/arch/mips/cobalt/console.c @@ -4,10 +4,15 @@ #include #include +#include + #define UART_BASE ((void __iomem *)CKSEG1ADDR(0x1c800000)) void prom_putchar(char c) { + if (cobalt_board_id <= COBALT_BRD_ID_QUBE1) + return; + while (!(readb(UART_BASE + UART_LSR) & UART_LSR_THRE)) ; -- cgit v1.2.3 From 2e4f95822cc17cb7095d50babe2d2fc4c043fa25 Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Mon, 14 Jan 2008 14:46:31 +0000 Subject: [MIPS] Cacheops.h: Fix typo. Signed-off-by: Ralf Baechle --- include/asm-mips/cacheops.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/asm-mips/cacheops.h b/include/asm-mips/cacheops.h index df7f2deb3b5..256ad2cc6eb 100644 --- a/include/asm-mips/cacheops.h +++ b/include/asm-mips/cacheops.h @@ -64,7 +64,7 @@ #define Page_Invalidate_T 0x16 /* - * R1000-specific cacheops + * R10000-specific cacheops * * Cacheops 0x02, 0x06, 0x0a, 0x0c-0x0e, 0x16, 0x1a and 0x1e are unused. * Most of the _S cacheops are identical to the R4000SC _SD cacheops. -- cgit v1.2.3