From 77c0870ca515667b77750b397008d68a17fad9d8 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Mon, 16 Aug 2010 09:21:19 +0300 Subject: omap3: id: fix 3630 rev detection Wrong placement of break causes all revisions of 3630 to be detected as 3630 es1.2, we need to break main loop if we have an identified chip, default falls through as in the rest of the switches in this function. Cc: Paul Walmsley Cc: Sanjeev Premi Cc: Kevin Hilman Cc: Manjunath K Cc: Anand Gadiyar Cc: Felipe Balbi Signed-off-by: Nishanth Menon Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/id.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c index e8256a2ed8e..9a879f95950 100644 --- a/arch/arm/mach-omap2/id.c +++ b/arch/arm/mach-omap2/id.c @@ -284,8 +284,8 @@ static void __init omap3_check_revision(void) default: omap_revision = OMAP3630_REV_ES1_2; omap_chip.oc |= CHIP_IS_OMAP3630ES1_2; - break; } + break; default: /* Unknown default to latest silicon rev as default*/ omap_revision = OMAP3630_REV_ES1_2; -- cgit v1.2.3 From 8098bb0d8c7fe4ace7d13274c85a149503eee114 Mon Sep 17 00:00:00 2001 From: "stanley.miao" Date: Mon, 16 Aug 2010 09:21:19 +0300 Subject: OMAP3: Fix a cpu type check problem cpu_is_omap3517() and cpu_is_omap3505() are the subgroups of cpu_is_omap34xx(), so we should check cpu_is_omap3517() and cpu_is_omap3505() first, then check cpu_is_omap34xx(). Otherwise, All AM35XX (Sitara) clocks do not get registered and device drivers (ti_hecc, etc...) that depend on those clocks are failing to get the clock and end up with non working device. Signed-off-by: Stanley.Miao Tested-by: Igor Grinberg Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/clock3xxx_data.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c index 138646deac8..dfdce2d8277 100644 --- a/arch/arm/mach-omap2/clock3xxx_data.c +++ b/arch/arm/mach-omap2/clock3xxx_data.c @@ -3417,7 +3417,13 @@ int __init omap3xxx_clk_init(void) struct omap_clk *c; u32 cpu_clkflg = CK_3XXX; - if (cpu_is_omap34xx()) { + if (cpu_is_omap3517()) { + cpu_mask = RATE_IN_3XXX | RATE_IN_3430ES2PLUS; + cpu_clkflg |= CK_3517; + } else if (cpu_is_omap3505()) { + cpu_mask = RATE_IN_3XXX | RATE_IN_3430ES2PLUS; + cpu_clkflg |= CK_3505; + } else if (cpu_is_omap34xx()) { cpu_mask = RATE_IN_3XXX; cpu_clkflg |= CK_343X; @@ -3432,12 +3438,6 @@ int __init omap3xxx_clk_init(void) cpu_mask |= RATE_IN_3430ES2PLUS; cpu_clkflg |= CK_3430ES2; } - } else if (cpu_is_omap3517()) { - cpu_mask = RATE_IN_3XXX | RATE_IN_3430ES2PLUS; - cpu_clkflg |= CK_3517; - } else if (cpu_is_omap3505()) { - cpu_mask = RATE_IN_3XXX | RATE_IN_3430ES2PLUS; - cpu_clkflg |= CK_3505; } if (omap3_has_192mhz_clk()) -- cgit v1.2.3 From a4192d32ae6788dc607e96fa85f9c9c8274e2212 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Mon, 16 Aug 2010 09:21:20 +0300 Subject: omap: Fix sev instruction usage for multi-omap Otherwise we get the following error with omap3_defconfig and CONFIG_SMP: Error: selected processor does not support `sev' Signed-off-by: Tony Lindgren Acked-by: Santosh Shilimkar --- arch/arm/mach-omap2/Makefile | 1 + arch/arm/mach-omap2/omap-smp.c | 3 +-- arch/arm/plat-omap/include/plat/smp.h | 7 ------- 3 files changed, 2 insertions(+), 9 deletions(-) diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index 63b2d8859c3..88d3a1e920f 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -25,6 +25,7 @@ obj-$(CONFIG_LOCAL_TIMERS) += timer-mpu.o obj-$(CONFIG_HOTPLUG_CPU) += omap-hotplug.o obj-$(CONFIG_ARCH_OMAP4) += omap44xx-smc.o omap4-common.o +AFLAGS_omap-headsmp.o :=-Wa,-march=armv7-a AFLAGS_omap44xx-smc.o :=-Wa,-march=armv7-a # Functions loaded to SRAM diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c index af3c20c8d3f..9e9f70e18e3 100644 --- a/arch/arm/mach-omap2/omap-smp.c +++ b/arch/arm/mach-omap2/omap-smp.c @@ -102,8 +102,7 @@ static void __init wakeup_secondary(void) * Send a 'sev' to wake the secondary core from WFE. * Drain the outstanding writes to memory */ - dsb(); - set_event(); + dsb_sev(); mb(); } diff --git a/arch/arm/plat-omap/include/plat/smp.h b/arch/arm/plat-omap/include/plat/smp.h index 6a3ff65c030..5177a9c5a25 100644 --- a/arch/arm/plat-omap/include/plat/smp.h +++ b/arch/arm/plat-omap/include/plat/smp.h @@ -19,13 +19,6 @@ #include -/* - * set_event() is used to wake up secondary core from wfe using sev. ROM - * code puts the second core into wfe(standby). - * - */ -#define set_event() __asm__ __volatile__ ("sev" : : : "memory") - /* Needed for secondary core boot */ extern void omap_secondary_startup(void); extern u32 omap_modify_auxcoreboot0(u32 set_mask, u32 clear_mask); -- cgit v1.2.3 From c45bd374e560873f2fff392769b9576c4f3bad40 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Mon, 16 Aug 2010 09:21:20 +0300 Subject: omap: Use CONFIG_SMP for test_for_ipi and test_for_ltirq Otherwise we get the following error when enabling CONFIG_SMP for omap3_defconfig: arch/arm/kernel/entry-armv.S: Assembler messages: arch/arm/kernel/entry-armv.S:48: Error: bad instruction `test_for_ipi r0,r6,r5,lr' arch/arm/kernel/entry-armv.S:48: Error: bad instruction `test_for_ltirq r0,r6,r5,lr' arch/arm/kernel/entry-armv.S:48: Error: bad instruction `test_for_ipi r0,r6,r5,lr' arch/arm/kernel/entry-armv.S:48: Error: bad instruction `test_for_ltirq r0,r6,r5,lr' Signed-off-by: Tony Lindgren Acked-by: Santosh Shilimkar --- arch/arm/mach-omap2/include/mach/entry-macro.S | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-omap2/include/mach/entry-macro.S b/arch/arm/mach-omap2/include/mach/entry-macro.S index 50fd7491664..06e64e1fc28 100644 --- a/arch/arm/mach-omap2/include/mach/entry-macro.S +++ b/arch/arm/mach-omap2/include/mach/entry-macro.S @@ -177,7 +177,10 @@ omap_irq_base: .word 0 cmpne \irqnr, \tmp cmpcs \irqnr, \irqnr .endm +#endif +#endif /* MULTI_OMAP2 */ +#ifdef CONFIG_SMP /* We assume that irqstat (the raw value of the IRQ acknowledge * register) is preserved from the macro above. * If there is an IPI, we immediately signal end of interrupt @@ -205,8 +208,7 @@ omap_irq_base: .word 0 streq \irqstat, [\base, #GIC_CPU_EOI] cmp \tmp, #0 .endm -#endif -#endif /* MULTI_OMAP2 */ +#endif /* CONFIG_SMP */ .macro irq_prio_table .endm -- cgit v1.2.3 From c66dd2660de534973303e2dd4f7784763bc9e549 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Mon, 16 Aug 2010 09:21:20 +0300 Subject: omap: Fix omap_4430sdp_defconfig for make oldconfig Commit ffb63e3402849e1b70119ee0c9a81dc9da4dfa97 changed Kconfig to select support for omap2, 3 and 4 by default. However, CONFIG_SMP won't currently work properly on uniprocessor ARMs, or if support for earlier ARM cores is selected in. Fix this by updating omap_4430sdp_defconfig to not select omap2 or 3 at this point. Signed-off-by: Tony Lindgren Acked-by: Santosh Shilimkar --- arch/arm/configs/omap_4430sdp_defconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/configs/omap_4430sdp_defconfig b/arch/arm/configs/omap_4430sdp_defconfig index 63e0c2d50f3..14c1e18c648 100644 --- a/arch/arm/configs/omap_4430sdp_defconfig +++ b/arch/arm/configs/omap_4430sdp_defconfig @@ -13,6 +13,9 @@ CONFIG_MODULE_SRCVERSION_ALL=y # CONFIG_BLK_DEV_BSG is not set CONFIG_ARCH_OMAP=y CONFIG_ARCH_OMAP4=y +# CONFIG_ARCH_OMAP2PLUS_TYPICAL is not set +# CONFIG_ARCH_OMAP2 is not set +# CONFIG_ARCH_OMAP3 is not set # CONFIG_OMAP_MUX is not set CONFIG_OMAP_32K_TIMER=y CONFIG_OMAP_DM_TIMER=y -- cgit v1.2.3 From 58a5559e461a4ab945286dacef611d3c542c5fee Mon Sep 17 00:00:00 2001 From: Kevin Hilman Date: Mon, 16 Aug 2010 09:21:19 +0300 Subject: OMAP3: PM: ensure IO wakeups are properly disabled Commit 5a5f561 (convert OMAP3 PRCM macros to the _SHIFT/_MASK suffixes) mistakenly removed the check for PER when disabling the IO chain. During idle, if the PER powerdomain transitions into a lower state and CORE does not, the IO pad wakeups are not being disabled in the idle path after they are enabled. This can happen with the lower C-states when using CPUidle for example. This patch ensures that the check for disabling IO wakeups also checks for PER transitions, matching the check done to enable IO wakeups. Found when debugging PM/CPUidle related problems reported by Ameya Palande . Problems were triggered particularily on boards with UART2 consoles (n900, Overo) since UART2 is in the PER powerdomain. Tested on l-o master (omap3_defonfig + CONFIG_CPU_IDLE=y) as well as with current PM branch. Boards tested: n900, Overo, omap3evm. Cc: Paul Walmsley Cc: Ameya Palande Tested-by: Jarkko Nikula Signed-off-by: Kevin Hilman [tony@atomide.com: updated description to clarify the transistion] Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/pm34xx.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c index fb4994ad622..7b03426c72a 100644 --- a/arch/arm/mach-omap2/pm34xx.c +++ b/arch/arm/mach-omap2/pm34xx.c @@ -480,7 +480,9 @@ void omap_sram_idle(void) } /* Disable IO-PAD and IO-CHAIN wakeup */ - if (omap3_has_io_wakeup() && core_next_state < PWRDM_POWER_ON) { + if (omap3_has_io_wakeup() && + (per_next_state < PWRDM_POWER_ON || + core_next_state < PWRDM_POWER_ON)) { prm_clear_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, PM_WKEN); omap3_disable_io_chain(); } -- cgit v1.2.3