From db20da32a22ccfa3a118408034eeb0ba61a42329 Mon Sep 17 00:00:00 2001 From: Russell King Date: Sun, 4 Dec 2005 17:56:46 +0000 Subject: [ARM] Add memory.txt to 00-INDEX Signed-off-by: Russell King --- Documentation/arm/00-INDEX | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/arm/00-INDEX b/Documentation/arm/00-INDEX index d753fe59a24..2c6a3b38967 100644 --- a/Documentation/arm/00-INDEX +++ b/Documentation/arm/00-INDEX @@ -16,5 +16,7 @@ empeg - Empeg documentation mem_alignment - alignment abort handler documentation +memory.txt + - description of the virtual memory layout nwfpe - NWFPE floating point emulator documentation -- cgit v1.2.3 From 9ddf61bd09a7668279d2b208a96eba784bec3d80 Mon Sep 17 00:00:00 2001 From: Marcelo Tosatti Date: Mon, 5 Dec 2005 10:15:06 +0000 Subject: [ARM SMP] mpcore_wdt bogus fpos check drivers/char/watchdog/mpcore_wdt.c write function contains a check for (ppos != &file->f_pos). Such check used to make sense when a pointer to file->f_pos was handed by vfs_write(), not a copy of it as it stands now. Signed-off-by: Marcelo Tosatti Signed-off-by: Russell King --- drivers/char/watchdog/mpcore_wdt.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/drivers/char/watchdog/mpcore_wdt.c b/drivers/char/watchdog/mpcore_wdt.c index 9defcf861b6..b4d84348988 100644 --- a/drivers/char/watchdog/mpcore_wdt.c +++ b/drivers/char/watchdog/mpcore_wdt.c @@ -180,10 +180,6 @@ static ssize_t mpcore_wdt_write(struct file *file, const char *data, size_t len, { struct mpcore_wdt *wdt = file->private_data; - /* Can't seek (pwrite) on this device */ - if (ppos != &file->f_pos) - return -ESPIPE; - /* * Refresh the timer. */ -- cgit v1.2.3 From a0d95af5c28666155ad4c85a63a5065436ae1d79 Mon Sep 17 00:00:00 2001 From: Deepak Saxena Date: Mon, 5 Dec 2005 10:54:59 +0000 Subject: [ARM] 3191/1: Mark I/O pointer as const in __raw_reads[bwl] Patch from Deepak Saxena Mark the ioremap'd cookie/pointer in said functions as const since we should not be actualy touching the data. This fixes a slew of compile warnings on IXP4xx as our reads[bwl] already mark this parameter as const. Signed-off-by: Deepak Saxena Signed-off-by: Russell King --- include/asm-arm/io.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/include/asm-arm/io.h b/include/asm-arm/io.h index ae69db4a101..0cf4d4f9960 100644 --- a/include/asm-arm/io.h +++ b/include/asm-arm/io.h @@ -42,9 +42,9 @@ extern void __raw_writesb(void __iomem *addr, const void *data, int bytelen); extern void __raw_writesw(void __iomem *addr, const void *data, int wordlen); extern void __raw_writesl(void __iomem *addr, const void *data, int longlen); -extern void __raw_readsb(void __iomem *addr, void *data, int bytelen); -extern void __raw_readsw(void __iomem *addr, void *data, int wordlen); -extern void __raw_readsl(void __iomem *addr, void *data, int longlen); +extern void __raw_readsb(const void __iomem *addr, void *data, int bytelen); +extern void __raw_readsw(const void __iomem *addr, void *data, int wordlen); +extern void __raw_readsl(const void __iomem *addr, void *data, int longlen); #define __raw_writeb(v,a) (__chk_io_ptr(a), *(volatile unsigned char __force *)(a) = (v)) #define __raw_writew(v,a) (__chk_io_ptr(a), *(volatile unsigned short __force *)(a) = (v)) -- cgit v1.2.3 From 31a5539e57fa80e877a2f180cd4ec9ce9de6fea0 Mon Sep 17 00:00:00 2001 From: Hiroki Kaminaga Date: Mon, 5 Dec 2005 10:55:00 +0000 Subject: [ARM] 3194/1: add pfn_to_kaddr macro for ARM take2 Patch from Hiroki Kaminaga This patch defines a new macro: pfn_to_kaddr(pfn). Same macro is already defined on other arch, such as i386. Signed-off-by: Hiroki Kaminaga Signed-off-by: Russell King --- include/asm-arm/memory.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/asm-arm/memory.h b/include/asm-arm/memory.h index a547ee598c6..3e572364ee7 100644 --- a/include/asm-arm/memory.h +++ b/include/asm-arm/memory.h @@ -122,6 +122,7 @@ static inline void *phys_to_virt(unsigned long x) */ #define __pa(x) __virt_to_phys((unsigned long)(x)) #define __va(x) ((void *)__phys_to_virt((unsigned long)(x))) +#define pfn_to_kaddr(pfn) __va((pfn) << PAGE_SHIFT) /* * Virtual <-> DMA view memory address translations -- cgit v1.2.3 From 5b35193f5868da5e63f5b4cfe8fbcf9f10fe65cd Mon Sep 17 00:00:00 2001 From: Deepak Saxena Date: Thu, 8 Dec 2005 23:34:44 +0000 Subject: [ARM] 3199/1: Remove bogus function prototype from arch-pxa/irq.h Patch from Deepak Saxena This looks like a leftover from 2.4 days... Signed-off-by: Deepak Saxena Signed-off-by: Russell King --- include/asm-arm/arch-pxa/irq.h | 5 ----- 1 file changed, 5 deletions(-) diff --git a/include/asm-arm/arch-pxa/irq.h b/include/asm-arm/arch-pxa/irq.h index d770e4b37ae..48c60f5eff6 100644 --- a/include/asm-arm/arch-pxa/irq.h +++ b/include/asm-arm/arch-pxa/irq.h @@ -12,8 +12,3 @@ #define fixup_irq(x) (x) -/* - * This prototype is required for cascading of multiplexed interrupts. - * Since it doesn't exist elsewhere, we'll put it here for now. - */ -extern void do_IRQ(int irq, struct pt_regs *regs); -- cgit v1.2.3 From 22f975f4ffa707ea24507f6899bb9f5a1ff034bc Mon Sep 17 00:00:00 2001 From: Nikola Valerjev Date: Sat, 10 Dec 2005 11:59:15 +0000 Subject: [ARM] 3200/1: Singlestep over ARM BX and BLX instructions using ptrace fix Patch from Nikola Valerjev Single stepping an application using ptrace() fails over ARM instructions BX and BLX. Steps to reproduce: Compile and link the following files main.c ----- void foo(); int main() { foo(); return 0; } foo.s ----- .text .globl foo foo: BX LR Using ptrace() functionality, run to main(), and start singlestepping. Singlestep over \"BX LR\" instruction won\'t transfer the control back to main, but run the code to completion. This problems seems to be in the function get_branch_address() in arch/arm/kernel/ptrace.c. The function doesn\'t seem to recognize BX and BLX instructions as branches. BX and BLX instructions can be used to convert from ARM to Thumb mode if the target address has the low bit set. However, they are also perfectly legal in the ARM only mode. Although other things in the kernel seem to indicate that only ARM mode is accepted (and not Thumb), many compilers will generate BX and BLX instructions even when generating ARM only code. Signed-off-by: Nikola Valerjev Signed-off-by: Russell King --- arch/arm/kernel/ptrace.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm/kernel/ptrace.c b/arch/arm/kernel/ptrace.c index 9a340e790da..2b84f78d7b0 100644 --- a/arch/arm/kernel/ptrace.c +++ b/arch/arm/kernel/ptrace.c @@ -242,6 +242,15 @@ get_branch_address(struct task_struct *child, unsigned long pc, unsigned long in */ long aluop1, aluop2, ccbit; + if ((insn & 0x0fffffd0) == 0x012fff10) { + /* + * bx or blx + */ + alt = get_user_reg(child, insn & 15); + break; + } + + if ((insn & 0xf000) != 0xf000) break; -- cgit v1.2.3