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path: root/include/asm-mips/mach-cobalt
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2008-10-11MIPS: Move headfiles to new location below arch/mips/includeRalf Baechle5-187/+0
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-01-29[MIPS] remove unneeded button check for resetYoichi Yuasa1-14/+1
Removed unneeded button check for reset. Because, the Cobalt has power switch. Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-11-02[MIPS] Cobalt: Fix IRQ comment; the Cobalt kernel uses CP0 counter now.Yoichi Yuasa1-2/+1
Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-11[MIPS] Cobalt: Move reset port definition to arch/mips/cobalt/reset.cYoichi Yuasa1-7/+0
It's only used in arch/mips/cobalt/reset.c. Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-11[MIPS] Cobalt: Move UART base definition to arch/mips/cobalt/console.cYoichi Yuasa1-2/+0
They're only used in arch/mips/cobalt/console.c. Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-11[MIPS] Cobalt: Move PCI definitions to arch/mips/pci/fixup-cobalt.c.Yoichi Yuasa1-24/+2
These PCI definitions are only used in arch/mips/pci/fixup-cobalt.c. Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-11[MIPS] Split up war.hRalf Baechle1-0/+25
It was getting a little big, ugly and a primary source for merge conflicts. Also the old method was a bit too forgiving in that the workaround did default to off, so now there is an explicit #error forcing platform maintainers to think if they should enable a workaround for a particular platform. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-11[MIPS] Sibyte: Replace SB1 cachecode with standard R4000 class cache code.Ralf Baechle1-1/+0
It may not be perfect yet but the SB1 code is badly borken and has horrible performance issues. Downside: This seriously breaks support for pass 1 parts of the BCM1250 where indexed cacheops don't work quite reliable but I seem to be the last one on the planet with a pass 1 part anyway. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-11[MIPS] Add GT641xx IRQ routines.Yoichi Yuasa2-26/+58
Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-07-20[MIPS] Disable UserLocal runtime detection on platforms which never have it.Ralf Baechle1-0/+1
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-07-20[MIPS] Disable MT runtime detection on platforms which never support MT.Ralf Baechle1-1/+2
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-07-10[MIPS] remove unused definitions for CobaltYoichi Yuasa1-5/+0
Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-05-11[MIPS] Add extern cobalt_board_idYoichi Yuasa1-0/+2
Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-02-06[MIPS] Define MIPS_CPU_IRQ_BASE in generic headerAtsushi Nemoto1-1/+3
The irq_base for {mips,rm7k,rm9k}_cpu_irq_init() are constant on all platforms and are same value on most platforms (0 or 16, depends on CONFIG_I8259). Define them in asm-mips/mach-generic/irq.h and make them customizable. This will save a few cycle on each CPU interrupt. A good side effect is removing some dependencies to MALTA in generic SMTC code. Although MIPS_CPU_IRQ_BASE is customizable, this patch changes irq mappings on DDB5477, EMMA2RH and MIPS_SIM, since really customizing them might cause some header dependency problem and there seems no good reason to customize it. So currently only VR41XX is using custom MIPS_CPU_IRQ_BASE value, which is 0 regardless of CONFIG_I8259. Testing this patch on those platforms is greatly appreciated. Thank you. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-11-30[MIPS] Rewrite GALILEO_INL/GALILEO_OUTL to GT_READ/GT_WRITEYoichi Yuasa2-28/+29
This patch has rewritten GALILEO_INL/GALILEO_OUTL using GT_READ/GT_WRITE. This patch tested on Cobalt Qube2. Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-07-13[MIPS] Use the proper technical term for naming some of the cache macros.Ralf Baechle1-1/+1
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-04-26Don't include linux/config.h from anywhere else in include/David Woodhouse1-1/+0
Signed-off-by: David Woodhouse <dwmw2@infradead.org>
2006-03-21[MIPS] Add early console for Cobalt.Peter Horton1-0/+2
Signed-off-by: Peter Horton <pdh@colonel-panic.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-02-07[MIPS] CPU definitions for Cobalt.Ralf Baechle1-0/+56
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-02-07[MIPS] Rename include/asm-mips/cobalt to include/asm-mips/mach-cobalt.Ralf Baechle2-0/+117
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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