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path: root/drivers/gpu/drm/nouveau/nva3_pm.c
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2012-10-03Merge branch 'drm-next' of git://people.freedesktop.org/~airlied/linuxLinus Torvalds1-125/+149
Pull drm merge (part 1) from Dave Airlie: "So first of all my tree and uapi stuff has a conflict mess, its my fault as the nouveau stuff didn't hit -next as were trying to rebase regressions out of it before we merged. Highlights: - SH mobile modesetting driver and associated helpers - some DRM core documentation - i915 modesetting rework, haswell hdmi, haswell and vlv fixes, write combined pte writing, ilk rc6 support, - nouveau: major driver rework into a hw core driver, makes features like SLI a lot saner to implement, - psb: add eDP/DP support for Cedarview - radeon: 2 layer page tables, async VM pte updates, better PLL selection for > 2 screens, better ACPI interactions The rest is general grab bag of fixes. So why part 1? well I have the exynos pull req which came in a bit late but was waiting for me to do something they shouldn't have and it looks fairly safe, and David Howells has some more header cleanups he'd like me to pull, that seem like a good idea, but I'd like to get this merge out of the way so -next dosen't get blocked." Tons of conflicts mostly due to silly include line changes, but mostly mindless. A few other small semantic conflicts too, noted from Dave's pre-merged branch. * 'drm-next' of git://people.freedesktop.org/~airlied/linux: (447 commits) drm/nv98/crypt: fix fuc build with latest envyas drm/nouveau/devinit: fixup various issues with subdev ctor/init ordering drm/nv41/vm: fix and enable use of "real" pciegart drm/nv44/vm: fix and enable use of "real" pciegart drm/nv04/dmaobj: fixup vm target handling in preparation for nv4x pcie drm/nouveau: store supported dma mask in vmmgr drm/nvc0/ibus: initial implementation of subdev drm/nouveau/therm: add support for fan-control modes drm/nouveau/hwmon: rename pwm0* to pmw1* to follow hwmon's rules drm/nouveau/therm: calculate the pwm divisor on nv50+ drm/nouveau/fan: rewrite the fan tachometer driver to get more precision, faster drm/nouveau/therm: move thermal-related functions to the therm subdev drm/nouveau/bios: parse the pwm divisor from the perf table drm/nouveau/therm: use the EXTDEV table to detect i2c monitoring devices drm/nouveau/therm: rework thermal table parsing drm/nouveau/gpio: expose the PWM/TOGGLE parameter found in the gpio vbios table drm/nouveau: fix pm initialization order drm/nouveau/bios: check that fixed tvdac gpio data is valid before using it drm/nouveau: log channel debug/error messages from client object rather than drm client drm/nouveau: have drm debugging macros build on top of core macros ...
2012-10-03drm/nouveau: port remainder of drm code, and rip out compat layerBen Skeggs1-123/+149
v2: Ben Skeggs <bskeggs@redhat.com> - fill in nouveau_pm.dev to prevent oops - fix ppc issues (build + OF shadow) Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-10-03drm/nouveau/fb: merge fb/vram and port to subdev interfacesBen Skeggs1-4/+2
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-10-03drm/nouveau/clock: pull in the implementation from all over the placeBen Skeggs1-1/+1
Still missing the main bits we use to change performance levels, I'll get to it after all the hard yakka has been finished. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-10-03drm/nouveau: restructure source tree, split core from drm implementationBen Skeggs1-1/+1
Future work will be headed in the way of separating the policy supplied by the nouveau drm module from the mechanisms provided by the driver core. There will be a couple of major classes (subdev, engine) of driver modules that have clearly defined tasks, and the further directory structure change is to reflect this. No code changes here whatsoever, aside from fixing up a couple of include file pathnames. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-10-02UAPI: (Scripted) Convert #include "..." to #include <path/...> in drivers/gpu/David Howells1-1/+1
Convert #include "..." to #include <path/...> in drivers/gpu/. Signed-off-by: David Howells <dhowells@redhat.com> Acked-by: Dave Airlie <airlied@redhat.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Thomas Gleixner <tglx@linutronix.de> Acked-by: Paul E. McKenney <paulmck@linux.vnet.ibm.com> Acked-by: Dave Jones <davej@redhat.com>
2012-05-24drm/nouveau/pm: some more delays for ddr3 reclockingBen Skeggs1-0/+1
These numbers from the binary driver's daemon scripts, and fix the transition to perflvl 3 on my T510. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-05-24drm/nva3/pm: another few magic regs, and slightly better 0x004018 handlingBen Skeggs1-4/+15
Not entirely convinced 0x004018 transitions are correct yet, but, it's an improvement. The 750MHz value comes from fiddling with the binary driver + coolbits on two different DDR3 NVA8 chipsets (T510 NVS3100M, and NVS300), not a clue where this number comes from. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-05-24drm/nva3/pm: initial attempt at handling 111100/111104Ben Skeggs1-0/+21
Probably not quite right, but this is enough now to make NVS300 reclock between all 3 of its perflvls correctly. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-05-24drm/nva3/pm: make pll->pll mode workBen Skeggs1-6/+21
This probably wants a cleanup, but I'm holding off until I know for sure how the rest of the things that need doing fit together. Tested on NVS300 by hacking up perflvl 1 to require PLL mode, and switching between perflvl 3 and 1. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-05-24drm/nva3/pm: attempt to bash a few 0x100200 bits correctlyBen Skeggs1-20/+46
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-05-24drm/nva3/pm: begin to restructure memory clock changes + another magicBen Skeggs1-8/+40
The binary driver appears to do various bits and pieces of the memory clock frequency change at different times, depending on the particular transition that's occuring. I've attempted to replicate this here for div->pll, pll->div and div->div transitions. With some additional (patches upcoming) magic regs being bashed, this allows me to correctly transition between all 3 perflvls on NVS300. pll->pll transitions will *not* work correctly at the moment, pending me tricking the binary driver into doing one and seeing how to correctly handle it. This patch also handles (hopefully) 0x1110e0, which appears to need changing depending on whether in PLL or divider mode.. Maybe. We'll see. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-05-24drm/nva3/pm: more random unknown PFB regsBen Skeggs1-1/+23
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-05-24drm/nva3/pm: initial attempt at more magic PFB regsBen Skeggs1-1/+24
The reg calculation may get moved elsewhere at some point, but lets figure out what exactly we need to do first. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-05-24drm/nva3/pm: hook up to ram reclocking helperBen Skeggs1-12/+110
This gets us a start on memory timings. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-05-24drm/nva3/pm: introduce more paranoiaBen Skeggs1-5/+10
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-12-21drm/nouveau/pm: make clocks_set return an error code clocks_set can fail.Martin Peres1-1/+5
Reporting an error is better than silently refusing to reclock. V2: Use the same logic on nv40 Signed-off-by: Martin Peres <martin.peres@labri.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-09-20drm/nva3/pm: fixup for NVAF specialBen Skeggs1-1/+7
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-09-20drm/nva3/pm: use crystal freq where appropriateBen Skeggs1-3/+4
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-09-20drm/nva3/pm: pll disabled if bit 0 of ctrl not setBen Skeggs1-19/+23
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-09-20drm/nvc0/pm: more complete parsing of clock domainsBen Skeggs1-0/+2
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-09-20drm/nva3/pm: idle graphics engine before changing clocksBen Skeggs1-0/+40
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-09-20drm/nva3/pm: tidy and add some comments here and thereBen Skeggs1-47/+78
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-09-20drm/nva3/pm: parse/reclock vdec/41a0 clocksBen Skeggs1-0/+20
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-09-20drm/nva3/pm: rewrite clock_set, and switch to new interfacesBen Skeggs1-136/+141
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-09-20drm/nva3/pm: rewrite clock readback functions, far more correct nowBen Skeggs1-33/+62
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-05-16drm/nva3/clk: better pll calculation when no fractional fb div availableBen Skeggs1-2/+2
The core/mem/shader clocks don't support the fractional feedback divider, causing our calculated clocks to be off by quite a lot in some cases. To solve this we will switch to a search-based algorithm when fN is NULL. For my NVA8 at PL3, this actually generates identical cooefficients to the binary driver. Hopefully that's a good sign, and that does not break VPLL calculation for someone.. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-05-16drm/nva3/pm: allow use of divisor 16Ben Skeggs1-1/+1
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-05-16drm/nva3/pm: initial pass at set_clock() hookBen Skeggs1-21/+94
I still discourage anyone from actually doing this yet. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-05-16drm/nva3: somewhat improve clock reportingBen Skeggs1-10/+46
Definitely not 100% correct, but, for the configurations I've seen used it'll read back the correct clocks now. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2010-10-05drm/nva3: split pm backend out from nv50Ben Skeggs1-0/+95
This will end up quite different, it makes sense for it to be completely separate. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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