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path: root/drivers/clk
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2014-11-18clk: samsung: exynos4: Propagate rate change of SPI dividersTomasz Figa1-3/+6
This patch adds missing CLK_SET_RATE_PARENT flag to div_spi{0,1,2} clocks to allow rate change propagation to div_spi{0,1,2}_pre. This fixes the problem with SPI bus clock rate setting. Change-Id: I26ef7028297914d5c99e55f0e9fa6dc6a9292e94 Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-11-18ARM:clk:exynos:pll35xx: Extend pll35xx_set_rate to support only S parameter ↵Lukasz Majewski1-10/+27
switch With PLL35xx device it is possible to switch PLL frequency without waiting for locking. This situation happens when P and M for new frequency are equal to corresponding parameters for old frequency. Then only S needs to be changed. In this patch support for such a change is provided. Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
2014-11-18clk: Implement clk_unregisterSylwester Nawrocki1-8/+124
clk_unregister() is currently not implemented and it is required when a clock provider module needs to be unloaded. Normally the clock supplier module is prevented to be unloaded by taking reference on the module in clk_get(). For cases when the clock supplier module deinitializes despite the consumers of its clocks holding a reference on the module, e.g. when the driver is unbound through "unbind" sysfs attribute, there are empty clock ops added. These ops are assigned temporarily to struct clk and used until all consumers release the clock, to avoid invoking callbacks from the module which just got removed. Signed-off-by: Jiada Wang <jiada_wang@mentor.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> --- Changes since v6: - fixed handling of NULL clk in clk_unregister(), clk pointer checks done before taking prepare_lock, pr_err() replaced with WARN_ON_ONCE. Changes since v5: - ensure clk->kref is not referenced when the passed clk is NULL. Changes since v4: - none. Changes since v3: - Use WARN_ON_ONCE() rather than WARN_ON() in clk_nodrv_disable_unprepare() callback. Changes since v2: - none. Changes since RFC v1: - renamed clk_dummy_* to clk_nodrv_*. Changes since v3 of the original patch [1]: - reparent all children to the orphan list instead of leaving the clock unregistered when it has child clocks, - removed unnecessary prerequisite checks in clk_debug_unregister(), - struct clk is now being freed only when the last clock consumer calls clk_put(), - empty clock ops are used after clk_unregister() has been called until all references to the clock are released and the clock object is freed. [1] http://www.spinics.net/lists/arm-kernel/msg247548.html
2014-11-18clk: Assign module owner of a clock being registeredSylwester Nawrocki1-0/+6
Use dev->driver->owner as the owner module of a clock, it ensures reference on the module is taken in the __clk_get(), __clk_put() helpers. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> --- Changes since v5: - none.
2014-11-18clk: Add common __clk_get(), __clk_put() implementationsSylwester Nawrocki1-0/+20
This patch adds common __clk_get(), __clk_put() clkdev helpers which replace their platform specific counterparts when the common clock API is enabled. The owner module pointer field is added to struct clk so a reference to the clock supplier module can be taken by the clock consumers. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> --- Changes since v5: - none. Changes since v4: - dropped unnecessary struct module forward declaration from clk-provider.h Changes since v3: - dropped exporting of __clk_get(), __clk_put(). Changes since v2: - fixed handling of NULL clock pointers in __clk_get(), __clk_put();
2014-11-18clkdev: Fix race condition in clock lookup from device treeSylwester Nawrocki1-2/+10
There is currently a race condition in the device tree part of clk_get() function, since the pointer returned from of_clk_get_by_name() may become invalid before __clk_get() call. E.g. due to the clock provider driver remove() callback being called in between of_clk_get_by_name() and __clk_get(). Fix this by doing both the look up and __clk_get() operations with the clock providers list mutex held. This ensures that the clock pointer returned from __of_clk_get_from_provider() call and passed to __clk_get() is valid, as long as the clock supplier module first removes its clock provider instance and then does clk_unregister() on the corresponding clocks. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Russell King <rmk+kernel@arm.linux.org.uk> --- Changes since v2: - none. Changes since v1: - include "clk.h".
2014-11-18clk: Provide not locked variant of of_clk_get_from_provider()Sylwester Nawrocki2-8/+46
Add helper functions for the of_clk_providers list locking and an unlocked variant of of_clk_get_from_provider(). These functions are intended to be used in the clkdev to avoid race condition in the device tree based clock look up in clk_get(). Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Russell King <rmk+kernel@arm.linux.org.uk> --- Changes since v3: - none. Changes since v2: - fixed typo in clk.h. Changes since v1: - moved the function declaractions to a local header.
2014-11-18clk: max77686: Register OF clock providerTomasz Figa1-0/+24
If max77686 chip is instantiated from device tree, it is desirable to have an OF clock provider to allow device tree based look-up of clocks. This patch adds OF clock provider registration to the clk-max77686 driver. Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-11-18clk: max77686: Refactor driver data handlingTomasz Figa1-12/+14
As a prerequisite for further patch adding OF clock provider support to the driver, this patch changes the driver to store an array of struct clk * as driver data. Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-11-18clk: max77686: Fix clean-up in error and remove pathsTomasz Figa1-22/+10
This patch fixes invalid kfree() and adds missing call to clk_unregister() in error and remove paths in max77686_clk_probe(). While at it, error handling is also cleaned up. Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-11-18clk: max77686: Make max77686_clk_register() return struct clk *Tomasz Figa1-7/+10
As a preparation for further patches, this patch modifies the clock registration helper function to return a pointer to the newly registered clock. No functional change is done to the driver. Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-11-18clk: max77686: Refactor successful exit of probe functionTomasz Figa1-2/+1
The function can simply return 0, without jumping to a separate label, which does exactly the same. This patch does not introduce any functional change, just a clean-up. Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-11-18clk: max77686: Provide .recalc_rate() operationTomasz Figa1-0/+7
It is usually nice to know frequency of a clock, so this patch adds a .recalc_rate() callback returning rates of provided clocks. Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-11-18clk: max77686: Correct callback used for checking clock statusTomasz Figa1-2/+2
Changing status of clock gates in max77686 requires i2c transfers, which can sleep, so this is done in prepare and unprepare callbacks. Due to this, checking whether whether the clock is ungated must be done in is_prepared() callback as well, for consistency. Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-11-18clk: exynos4: Add additional G2D clocksSachin Kamat1-2/+7
Add G2D clocks for Exynos4x12 SoC and sclk_fimg2d required by G2D IP. Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Cc: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2014-11-18clock: clk-exynos4: set the CLK_SET_RATE_PARENT for mmc4Jaehoon Chung1-1/+2
mmc4_clk set to CLK_SET_PARENT with DIV_F(). Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
2014-11-18clk: samsung: fix section mismatch from audio subsystem clocksSeung-Woo Kim1-1/+1
The init function should have __init flag to match reference sections. Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com>
2014-11-18clk: samsung: exynos4: Do not disable ISP bus clocksTomasz Figa1-4/+4
Some ISP bus clocks must be kept enabled when entering sleep mode, otherwise the system hangs. This patch adds CLK_IGNORE_UNUSED flags to those clocks to keep them ungated when FIMC IS driver is not present. Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-11-18clk: honor CLK_GET_RATE_NOCACHE in clk_set_ratePeter De Schrijver1-1/+1
clk_set_rate() uses clk->rate directly. This causes problems if the clock is marked as CLK_GET_RATE_NOCACHE. Hence call clk_get_rate() to get the current rate. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-11-18clk: exynos4: Add CLK_GET_RATE_NOCACHE flag for the Exynos4x12 ISP clocksSylwester Nawrocki1-30/+34
The ISP clock registers belong to the ISP power domain and may change their values if this power domain is switched off/on. Add CLK_GET_RATE_NOCACHE flags to ensure clk_set_rate() and clk_get_rate() work properly and do not use invalid cached values. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2014-11-18clk: Prevent potential null pointer dereference in clk_set_rate()Sylwester Nawrocki1-0/+3
Ensure the passed clk pointer is not dereferenced if it is invalid. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2014-11-18clk: exynos4: Add clock entries for TMUSachin Kamat1-1/+3
Added clock entries for thermal management unit (TMU) for Exynos4 SoCs. Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Cc: Thomas Abraham <thomas.abraham@linaro.org> Cc: Mike Turquette <mturquette@linaro.org>
2014-11-18clk: samsung: exynos4: Add support for CLKOUTTomasz Figa1-2/+47
This patch adds the ability to control gating and muxing of CLKOUT signal through common clock routines. Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-11-18clk: Add Exynos Audio Subsystem clocks driverSylwester Nawrocki3-4/+119
TODO: gate clocks. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-11-18clk: samsung: exynos4: Add support for PLL46xx rate configurationTomasz Figa3-17/+117
This patch adds support for rate configuration of PLL46xx, which is used for EPLL and VPLL on Exynos4210. Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-11-18clk: samsung: exynos4: Fix clock registration orderTomasz Figa1-4/+5
This patch moves registration of fixed clocks and Exynos4210-specific mux clocks before PLL registration, because some of those clocks are needed for Exynos4210 PLL initialization. Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-11-18clk: samsung: exynos4: Allow rate setting propagation through sclk_vpllTomasz Figa1-4/+4
This patch adds CLK_SET_RATE_PARENT flag to sclk_vpll to allow rate configuration of VPLL on Exynos4210 and Exynos4x12. Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-11-18clk: samsung: pll: Add support for PLL36xx rate configurationTomasz Figa3-15/+138
This patch adds implementation of round_rate and set_rate operations of PLL36xx PLLs used on Exynos 4x12 SoCs as EPLL and VPLL. Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-11-18clk: samsung: pll: Do not return error codes in round_rate callbackTomasz Figa1-2/+2
This patch modifies pll35xx round_rate callback to return current frequency instead of error codes to avoid problems caused by clock core using error codes as frequencies. Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-11-18clk: samsung: pll: Add support for PLL45xx rate settingTomasz Figa3-15/+122
This patch adds support for setting rate of PLL45xx based on PMS table received from SoC-specific code. Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-11-18clock: Support for [A|M]PLL's (35xx) set_rate and round_rate functionsLukasz Majewski3-12/+146
Support for [A|M]PLL's [set|round]_rate functions has been added. Now simple call to clk_set_rate is responsible for setting proper frequency. This commit allows for further refactoring of exynos4x12-cpufreq.c code. Signed-off-by: Lukasz Majewski <l.majewski@samsung.com> clk: Fix bug on setting xpll's pms value in clk-pll.c Signed-off-by: Jonghwa Lee <jonghwa3.lee@samsung.com>
2014-11-18clk: exynos5250: add gate clock descriptions of System MMUCho KyongHo1-7/+46
This adds gate clocks of all System MMUs and their master IPs that are not apeared in clk-exynos5250.c Signed-off-by: Cho KyongHo <pullip.cho@samsung.com>
2014-07-17clk: spear3xx: Use proper control register offsetThomas Gleixner1-1/+1
commit 15ebb05248d025534773c9ef64915bd888f04e4b upstream. The control register is at offset 0x10, not 0x0. This is wreckaged since commit 5df33a62c (SPEAr: Switch to common clock framework). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2014-06-07clk: vexpress: NULL dereference on error pathDan Carpenter1-1/+1
commit 6b4ed8b00e93bd31f24a25f59ed8d1b808d0cc00 upstream. If the allocation fails then we dereference the NULL in the error path. Just return directly. Fixes: ed27ff1db869 ('clk: Versatile Express clock generators ("osc") driver') Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Pawel Moll <pawel.moll@arm.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2014-01-15clk: exynos5250: fix sysmmu_mfc{l,r} gate clocksAndrew Bresticker1-2/+2
commit 97c3557c3e0413efb1f021f582d1459760e22727 upstream. The gate clocks for the MFC sysmmus appear to be flipped, i.e. GATE_IP_MFC[2] gates sysmmu_mfcl and GATE_IP_MFC[1] gates sysmmu_mfcr. Fix this so that the MFC will start up. Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2014-01-15clk: samsung: exynos5250: Add CLK_IGNORE_UNUSED flag for the sysreg clockAbhilash Kesavan1-1/+2
commit 2feed5aecf5f367b92bd6b6e92afe9e3de466907 upstream. The sysreg (system register) generates control signals for various blocks like disp1blk, i2c, mipi, usb etc. However, it gets disabled as an unused clock at boot-up. This can lead to failures in operation of above blocks, because they can not be configured properly if this clock is disabled. Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> [t.figa: Updated patch description.] Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2014-01-15clk: samsung: exynos4: Correct SRC_MFC registerSeung-Woo Kim1-1/+1
commit 5fdd1b56be51b1ec4dbde5b213d649ac717442da upstream. The SRC_MFC register offset was incorrect, which could cause have caused wrong calculation of rate of sclk_mfc clock, that could in turn lead to incorrect operation of MFC. This patch corrects it. Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> [t.figa: Updated patch description] Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2014-01-15clk: clk-divider: fix divisor > 255 bugJames Hogan1-1/+1
commit 778037e1ccb75609846deca9e419449c1dc137fa upstream. Commit 6d9252bd9a4bb (clk: Add support for power of two type dividers) merged in v3.6 added the _get_val function to convert a divisor value to a register field value depending on the flags. However it used the type u8 for the div field, causing divisors larger than 255 to be masked and the resultant clock rate to be too high. E.g. in my case an 11bit divider was supposed to divide 24.576 MHz down to 32.768KHz. The divisor was correctly calculated as 750 (0x2ee). This was masked to 238 (0xee) resulting in a frequency of 103.26KHz. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Rajendra Nayak <rnayak@ti.com> Cc: linux-arm-kernel@lists.infradead.org Signed-off-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2013-12-04clk: armada-370: fix tclk frequenciesSimon Guinot1-2/+2
commit 1022c75f5abd3a3b25e679bc8793d21bedd009b4 upstream. This patch fixes the tclk frequency array for the Armada-370 SoC. This bug has been introduced by commit 6b72333d ("clk: mvebu: add Armada 370 SoC-centric clock init"). A wrong tclk frequency affects the following drivers: mvsdio, mvneta, i2c-mv64xxx and mvebu-devbus. This list may be incomplete. About the mvneta Ethernet driver, note that the tclk frequency is used to compute the Rx time coalescence. Then, this bug harms the coalescence configuration and also degrades the networking performances with the default values. Signed-off-by: Simon Guinot <simon.guinot@sequanux.org> Cc: Andrew Lunn <andrew@lunn.ch> Cc: Gregory CLEMENT <gregory.clement@free-electrons.com> Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Acked-by: Jason Cooper <jason@lakedaemon.net> Signed-off-by: Michael Turquette <mturquette@deferred.io> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2013-11-13clk: fixup argument order when setting VCO parametersJonathan Austin1-1/+1
commit 2f9f64bc5aa31836810cd25301aa4772ad73ebab upstream. The order of arguments in the call to vco_set() for the ICST clocks appears to have been switched in error, which results in the VCO not being initialised correctly. This in turn stops the integrated LCD on things like Integrator/CP from working correctly. This patch fixes the order and restores the expected functionality. Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Jonathan Austin <jonathan.austin@arm.com> Signed-off-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2013-09-26clk: wm831x: Initialise wm831x pointer on initMark Brown1-0/+2
commit 08442ce993deeb15a070c14cc3f3459e87d111e0 upstream. Otherwise any attempt to interact with the hardware will crash. This is what happens when drivers get written blind. Signed-off-by: Mark Brown <broonie@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2013-06-16ARM: tegra30: clocks: Fix pciex clock registrationJay Agarwal1-5/+6
Registering pciex as peripheral clock instead of fixed clock as tegra_perih_reset_assert(deassert) api of this clock api gives warning and ultimately does not succeed to assert(deassert) Signed-off-by: Jay Agarwal <jagarwal@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-06-11clk: exynos5250: Add CLK_IGNORE_UNUSED flag for pmu clockTushar Behera1-1/+1
Currently 'pmu' clock is not handled by any of the drivers. Also before the introduction of CCF, this clock was not defined, hence was left enabled always. When this clock is disabled, software reset register becomes inaccessible and system reboot doesn't work. Upon restoring the default behaviour, system reboot starts working. Signed-off-by: Tushar Behera <tushar.behera@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-06-11clk: spear: fix build error for spear3xxArnd Bergmann1-1/+1
This patch is required to be able to disable spear320 support after the spear320_clk_init() prototype changed for the real function but not for the dummy. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-06-11clk: samsung: Fix pll36xx_recalc_rate to handle kdiv properlyDoug Anderson1-2/+3
The KDIV value is often listed as unsigned but it needs to be treated as a 16-bit signed value when using it in calculations. Fix our rate recalculation to do this correctly. Before doing this, I tried setting EPLL on exynos5250 to: rate, m, p, s, k = 80000000, 107, 2, 4, 43691 This rate is exactly from the table in the exynos5250 user manual. I read this back as 80750003 with: cat /sys/kernel/debug/clk/fin_pll/fout_epll/clk_rate After this patch, it reads back as 80000003 Signed-off-by: Doug Anderson <dianders@chromium.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Reviewed-by: Vikas Sajjan <vikas.sajjan@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-06-10clk: exynos5250: Add sclk_mpll to the parent list of mout_cpu clockTushar Behera1-1/+1
'mout_mpll' is added the list of parent clocks for 'mout_cpu'. 'mout_mpll' is an alias to the clock 'sclk_mpll'. Hence 'sclk_mpll' should be added to the list of parent clocks. This results in an error when cpufreq driver for EXYNOS5250 tries to set 'mout_mpll' as a parent for 'mout_cpu'. clk_set_parent: clk sclk_mpll can not be parent of clk mout_cpu Signed-off-by: Tushar Behera <tushar.behera@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-06-10clk: exynos5250: Update cpufreq related clocks for EXYNOS5250Tushar Behera1-3/+3
cpufreq driver for EXYNOS5250 is not a platform driver, hence we cannot currently pass the clock names through a device tree node. Instead, we need to make them available through a global alias. cpufreq driver for EXYNOS5250 requires four clocks - 'armclk', 'mout_cpu', 'mout_mpll' and 'mout_apll'. 'armclk' has already been defined with an alias, 'mout_cpu', 'mout_mpll' and 'mout_apll' are now defined with an alias. Signed-off-by: Tushar Behera <tushar.behera@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-06-06clk: remove notifier from list before freeing itLai Jiangshan1-0/+1
The @cn is stay in @clk_notifier_list after it is freed, it cause memory corruption. Example, if @clk is registered(first), unregistered(first), registered(second), unregistered(second). The freed @cn will be used when @clk is registered(second), and the bug will be happened when @clk is unregistered(second): [ 517.040000] clk_notif_dbg clk_notif_dbg.1: clk_notifier_unregister() [ 517.040000] Unable to handle kernel paging request at virtual address 00df3008 [ 517.050000] pgd = ed858000 [ 517.050000] [00df3008] *pgd=00000000 [ 517.060000] Internal error: Oops: 5 [#1] PREEMPT SMP ARM [ 517.060000] Modules linked in: clk_notif_dbg(O-) [last unloaded: clk_notif_dbg] [ 517.060000] CPU: 1 PID: 499 Comm: modprobe Tainted: G O 3.10.0-rc3-00119-ga93cb29-dirty #85 [ 517.060000] task: ee1e0180 ti: ee3e6000 task.ti: ee3e6000 [ 517.060000] PC is at srcu_readers_seq_idx+0x48/0x84 [ 517.060000] LR is at srcu_readers_seq_idx+0x60/0x84 [ 517.060000] pc : [<c0052720>] lr : [<c0052738>] psr: 80070013 [ 517.060000] sp : ee3e7d48 ip : 00000000 fp : ee3e7d6c [ 517.060000] r10: 00000000 r9 : ee3e6000 r8 : 00000000 [ 517.060000] r7 : ed84fe4c r6 : c068ec90 r5 : c068e430 r4 : 00000000 [ 517.060000] r3 : 00df3000 r2 : 00000000 r1 : 00000002 r0 : 00000000 [ 517.060000] Flags: Nzcv IRQs on FIQs on Mode SVC_32 ISA ARM Segment user [ 517.060000] Control: 18c5387d Table: 2d85804a DAC: 00000015 [ 517.060000] Process modprobe (pid: 499, stack limit = 0xee3e6238) [ 517.060000] Stack: (0xee3e7d48 to 0xee3e8000) .... [ 517.060000] [<c0052720>] (srcu_readers_seq_idx+0x48/0x84) from [<c0052790>] (try_check_zero+0x34/0xfc) [ 517.060000] [<c0052790>] (try_check_zero+0x34/0xfc) from [<c00528b0>] (srcu_advance_batches+0x58/0x114) [ 517.060000] [<c00528b0>] (srcu_advance_batches+0x58/0x114) from [<c0052c30>] (__synchronize_srcu+0x114/0x1ac) [ 517.060000] [<c0052c30>] (__synchronize_srcu+0x114/0x1ac) from [<c0052d14>] (synchronize_srcu+0x2c/0x34) [ 517.060000] [<c0052d14>] (synchronize_srcu+0x2c/0x34) from [<c0053a08>] (srcu_notifier_chain_unregister+0x68/0x74) [ 517.060000] [<c0053a08>] (srcu_notifier_chain_unregister+0x68/0x74) from [<c0375a78>] (clk_notifier_unregister+0x7c/0xc0) [ 517.060000] [<c0375a78>] (clk_notifier_unregister+0x7c/0xc0) from [<bf008034>] (clk_notif_dbg_remove+0x34/0x9c [clk_notif_dbg]) [ 517.060000] [<bf008034>] (clk_notif_dbg_remove+0x34/0x9c [clk_notif_dbg]) from [<c02bb974>] (platform_drv_remove+0x24/0x28) [ 517.060000] [<c02bb974>] (platform_drv_remove+0x24/0x28) from [<c02b9bf8>] (__device_release_driver+0x8c/0xd4) [ 517.060000] [<c02b9bf8>] (__device_release_driver+0x8c/0xd4) from [<c02ba680>] (driver_detach+0x9c/0xc4) [ 517.060000] [<c02ba680>] (driver_detach+0x9c/0xc4) from [<c02b99c4>] (bus_remove_driver+0xcc/0xfc) [ 517.060000] [<c02b99c4>] (bus_remove_driver+0xcc/0xfc) from [<c02bace4>] (driver_unregister+0x54/0x78) [ 517.060000] [<c02bace4>] (driver_unregister+0x54/0x78) from [<c02bbb44>] (platform_driver_unregister+0x1c/0x20) [ 517.060000] [<c02bbb44>] (platform_driver_unregister+0x1c/0x20) from [<bf0081f8>] (clk_notif_dbg_driver_exit+0x14/0x1c [clk_notif_dbg]) [ 517.060000] [<bf0081f8>] (clk_notif_dbg_driver_exit+0x14/0x1c [clk_notif_dbg]) from [<c00835e4>] (SyS_delete_module+0x200/0x28c) [ 517.060000] [<c00835e4>] (SyS_delete_module+0x200/0x28c) from [<c000edc0>] (ret_fast_syscall+0x0/0x48) [ 517.060000] Code: e5973004 e7911102 e0833001 e2881002 (e7933101) Cc: stable@kernel.org Reported-by: Sören Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Lai Jiangshan <laijs@cn.fujitsu.com> Tested-by: Sören Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Mike Turquette <mturquette@linaro.org> [mturquette@linaro.org: shortened $SUBJECT]
2013-05-30clk: mxs: Include clk mxs header fileFabio Estevam1-0/+1
Fix the following sparse warnings: drivers/clk/mxs/clk-imx28.c:72:5: warning: symbol 'mxs_saif_clkmux_select' was not declared. Should it be static? drivers/clk/mxs/clk-imx28.c:156:12: warning: symbol 'mx28_clocks_init' was not declared. Should it be static? Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org> [mturquette@linaro.org: fixed $SUBJECT line]
2013-05-29clk: vt8500: Fix unbalanced spinlock in vt8500_dclk_set_rate()Tony Prisk1-1/+1
With the addition of a DVO clock, a bug is now evident in the vt8500 clock code: [ 0.290000] WARNING: at init/main.c:698 do_one_initcall+0x158/0x18c() [ 0.300000] initcall wm8505fb_driver_init+0x0/0xc returned with disabled int This is caused by an unbalanced spinlock in vt8500_dclk_set_rate(). Replace the second call to spin_lock_irqsave() with spin_unlock_irqrestore(). Signed-off-by: Tony Prisk <linux@prisktech.co.nz> Signed-off-by: Mike Turquette <mturquette@linaro.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-08 12:41:12 +0000