summaryrefslogtreecommitdiff
path: root/arch
AgeCommit message (Collapse)AuthorFilesLines
2011-05-19SSB: Change fallback sprom to callback mechanism.Hauke Mehrtens1-2/+14
Some embedded devices like the Netgear WNDR3300 have two SSB based cards without an own sprom on the pci bus. We have to provide two different fallback sproms for these and this was not possible with the old solution. In the bcm47xx architecture the sprom data is stored in the nvram in the main flash storage. The architecture code will be able to fill the sprom with the stored data based on the bus where the device was found. The bcm63xx code should do the same thing as before, just using the new API. Acked-by: Michael Buesch <mb@bu3sch.de> Cc: netdev@vger.kernel.org Cc: linux-wireless@vger.kernel.org Cc: Florian Fainelli <florian@openwrt.org> Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2362/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2011-05-19MIPS: Alchemy: Clean up GPIO registers and accessorsManuel Lauss6-52/+56
remove au_readl/au_writel, remove the predefined GPIO1/2 KSEG1 register addresses and fix the fallout in all boards and drivers. This also fixes a bug in the mtx-1_wdt driver which was introduced by commit 6ea8115bb6f359df4f45152f2b40e1d4d1891392 ("Convert mtx1 wdt to be a platform device and use generic GPIO API") before this patch mtx-1_wdt only modified GPIO215, the patch then used the gpio resource information as bit index into the GPIO2 register but the conversion to the GPIO API didn't realize that. With this patch the drivers original behaviour is restored and GPIO15 is left alone. Signed-off-by: Manuel Lauss <manuel.lauss@googlemail.com> Cc: Florian Fainelli <florian@openwrt.org> To: Linux-MIPS <linux-mips@linux-mips.org> Cc: linux-watchdog@vger.kernel.org Cc: Wim Van Sebroeck <wim@iguana.be> Patchwork: https://patchwork.linux-mips.org/patch/2381/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org
2011-05-19MIPS: Alchemy: Cleanup DMA addressesManuel Lauss4-85/+35
According to the databooks, the Au1000 DMA engine must be programmed with the physical FIFO addresses. This patch does that; furthermore this opened the possibility to get rid of a lot of now unnecessary address defines. Signed-off-by: Manuel Lauss <manuel.lauss@googlemail.com> To: Linux-MIPS <linux-mips@linux-mips.org> Cc: Florian Fainelli <florian@openwrt.org> Cc: Wolfgang Grandegger <wg@grandegger.com> Patchwork: https://patchwork.linux-mips.org/patch/2348/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org
2011-05-19MIPS: Alchemy: Rewrite ethernet platform setupManuel Lauss2-91/+123
Rewrite ethernet setup to use runtime cpu detection, and also clean up the ethernet base address mess as far as possible. Signed-off-by: Manuel Lauss <manuel.lauss@googlemail.com> To: Linux-MIPS <linux-mips@linux-mips.org> Cc: Florian Fainelli <florian@openwrt.org> Cc: Wolfgang Grandegger <wg@grandegger.com> Patchwork: https://patchwork.linux-mips.org/patch/2353/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org
2011-05-19MIPS: Alchemy: Rewrite UART setup and constants.Manuel Lauss9-78/+107
Detect CPU type at runtime and setup uarts accordingly; also clean up the uart base address mess in the process as far as possible. Signed-off-by: Manuel Lauss <manuel.lauss@googlemail.com> To: Linux-MIPS <linux-mips@linux-mips.org> Cc: Florian Fainelli <florian@openwrt.org> Cc: Wolfgang Grandegger <wg@grandegger.com> Patchwork: https://patchwork.linux-mips.org/patch/2352/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org
2011-05-19MIPS: Alchemy: Convert dbdma.c to syscore_opsManuel Lauss3-88/+47
Convert the PM sysdev to syscore_ops and clean up the ddma addresses a bit. Signed-off-by: Manuel Lauss <manuel.lauss@googlemail.com> To: Linux-MIPS <linux-mips@linux-mips.org> Cc: Florian Fainelli <florian@openwrt.org> Cc: Wolfgang Grandegger <wg@grandegger.com> Patchwork: https://patchwork.linux-mips.org/patch/2351/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2011-05-19MIPS: Alchemy: Convert irq.c to syscore_ops.Manuel Lauss1-60/+41
Convert the PM sysdev to use syscore_ops instead. Signed-off-by: Manuel Lauss <manuel.lauss@googlemail.com> To: Linux-MIPS <linux-mips@linux-mips.org> Cc: Florian Fainelli <florian@openwrt.org> Cc: Wolfgang Grandegger <wg@grandegger.com> Patchwork: https://patchwork.linux-mips.org/patch/2350/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2011-05-19MIPS: Alchemy: irq code and constant cleanupManuel Lauss2-231/+140
replace au_readl/au_writel with __raw_readl/__raw_writel, and clean up IC-related stuff from the headers. Signed-off-by: Manuel Lauss <manuel.lauss@googlemail.com> To: Linux-MIPS <linux-mips@linux-mips.org> Cc: Florian Fainelli <florian@openwrt.org> Cc: Wolfgang Grandegger <wg@grandegger.com> Patchwork: https://patchwork.linux-mips.org/patch/2354/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2011-05-19MIPS: Alchemy: update inlinable GPIO APIManuel Lauss1-0/+51
This fixes a build failure with gpio_keys and CONFIG_GPIOLIB=n (mtx1): CC drivers/input/keyboard/gpio_keys.o gpio_keys.c: In function 'gpio_keys_report_event': gpio_keys.c:325:2: error: implicit declaration of function 'gpio_get_value_cansleep' gpio_keys.c: In function 'gpio_keys_setup_key': gpio_keys.c:390:3: error: implicit declaration of function 'gpio_set_debounce' Also add stubs for the other new functions. Signed-off-by: Manuel Lauss <manuel.lauss@googlemail.com> To: Linux-MIPS <linux-mips@linux-mips.org> Cc: Florian Fainelli <florian@openwrt.org> Cc: Wolfgang Grandegger <wg@grandegger.com> Patchwork: https://patchwork.linux-mips.org/patch/2346/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2011-05-19MIPS: DB1200: Set Config[OD] for improved stability.Manuel Lauss2-2/+9
Setting Config[OD] gets rid of a _LOT_ of spurious CPLD interrupts, but also decreases overall performance a bit. Signed-off-by: Manuel Lauss <manuel.lauss@googlemail.com> To: Linux-MIPS <linux-mips@linux-mips.org> Cc: Florian Fainelli <florian@openwrt.org> Cc: Wolfgang Grandegger <wg@grandegger.com> Patchwork: https://patchwork.linux-mips.org/patch/2347/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2011-05-19MIPS: Split do_syscall_trace into two functions.Ralf Baechle7-20/+43
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2011-05-19MIPS: Use single define for pending work on syscall exitRalf Baechle2-1/+4
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2011-05-19MIPS: IP27: Remove pointless switch statement.Ralf Baechle1-12/+1
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2011-05-19MIPS: Lantiq: Add etop board supportJohn Crispin1-0/+6
Register the etop platform device inside the machtype specific init code. Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Ralph Hempel <ralph.hempel@lantiq.com> Signed-off-by: David Daney <ddaney@caviumnetworks.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2356/ Patchwork: https://patchwork.linux-mips.org/patch/2370/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2011-05-19MIPS: Lantiq: Add ethernet driverJohn Crispin4-2/+33
This patch adds the driver for the ETOP Packet Processing Engine (PPE32) found inside the XWAY family of Lantiq MIPS SoCs. This driver makes 100MBit ethernet work. Support for all 8 dma channels, gbit and the embedded switch found on the ar9/vr9 still needs to be implemented. Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Ralph Hempel <ralph.hempel@lantiq.com> Cc: linux-mips@linux-mips.org Cc: netdev@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/2357/ Acked-by: David S. Miller <davem@davemloft.net> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2011-05-19MIPS: Lantiq: Add DMA supportJohn Crispin5-2/+317
This patch adds support for the DMA engine found inside the XWAY family of SoCs. The engine has 5 ports and 20 channels. Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Ralph Hempel <ralph.hempel@lantiq.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2355/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2011-05-19MIPS: Lantiq: Add more gpio driversJohn Crispin3-1/+284
The XWAY family allows to extend the number of gpios by using shift registers or latches. This patch adds the 2 drivers needed for this. The extended gpios are output only. [ralf@linux-mips.org: Fixed ltq_stp_probe section() attributes.] Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Ralph Hempel <ralph.hempel@lantiq.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2258/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2011-05-19MIPS: Lantiq: Add machtypes for lantiq eval kitsJohn Crispin6-0/+155
This patch adds mach specific code for the Lantiq EASY50712/50601 evaluation boards Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Ralph Hempel <ralph.hempel@lantiq.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2255/ Patchwork: https://patchwork.linux-mips.org/patch/2361/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2011-05-19MIPS: Lantiq: Add mips_machine supportJohn Crispin7-2/+86
This patch adds support for Gabor's mips_machine patch. Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Ralph Hempel <ralph.hempel@lantiq.com> Cc: Gabor Juhos <juhosg@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2251/ Patchwork: https://patchwork.linux-mips.org/patch/2358/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2011-05-19MIPS: Lantiq: Add platform device supportJohn Crispin6-2/+263
This patch adds the wrappers for registering our platform devices. Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Ralph Hempel <ralph.hempel@lantiq.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2254/ Patchwork: https://patchwork.linux-mips.org/patch/2360/ Patchwork: https://patchwork.linux-mips.org/patch/2359/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2011-05-19MIPS: Lantiq: Add PCI controller support.John Crispin5-0/+478
The Lantiq family of SoCs have a EBU (External Bus Unit). This patch adds the driver that allows us to use the EBU as a PCI controller. In order for PCI to work the EBU is set to endianess swap all the data. In addition we need to make use of SWAP_IO_SPACE for device->host DMA to work. The clock of the PCI works in several modes (internal/external). If this is not configured correctly the SoC will hang. Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Ralph Hempel <ralph.hempel@lantiq.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2250/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2011-05-19MIPS: Lantiq: add SoC specific code for XWAY familyJohn Crispin16-0/+1026
Add support for the Lantiq XWAY family of Mips24KEc SoCs. * Danube (PSB50702) * Twinpass (PSB4000) * AR9 (PSB50802) * Amazon SE (PSB5061) The Amazon SE is a lightweight SoC and has no PCI as well as a different clock. We split the code out into seperate files to handle this. The GPIO pins on the SoCs are multi function and there are several bits we can use to configure the pins. To be as compatible as possible to GPIOLIB we add a function int lq_gpio_request(unsigned int pin, unsigned int alt0, unsigned int alt1, unsigned int dir, const char *name); which lets you configure the 2 "alternate function" bits. This way drivers like PCI can make use of GPIOLIB without a cubersome wrapper. The PLL code inside arch/mips/lantiq/xway/clk-xway.c is voodoo to me. It was taken from a 2.4.20 source tree and was never really changed by me since then. Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Ralph Hempel <ralph.hempel@lantiq.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2249/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2011-05-19MIPS: Lantiq: Add initial support for Lantiq SoCsJohn Crispin13-0/+774
Add initial support for Mips based SoCs made by Lantiq. This series will add support for the XWAY family. The series allows booting a minimal system using a initramfs or NOR. Missing drivers and support for Amazon and GPON family will be provided in a later series. [Ralf: Remove some cargo cult programming and fixed formatting.] Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Ralph Hempel <ralph.hempel@lantiq.com> Signed-off-by: David Daney <ddaney@caviumnetworks.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2252/ Patchwork: https://patchwork.linux-mips.org/patch/2371/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2011-05-19MIPS: Enable kmemleak for MIPSMaxin John1-0/+1
Signed-off-by: Maxin B. John <maxin.john@gmail.com> To: Catalin Marinas <catalin.marinas@arm.com> Cc: Daniel Baluta <dbaluta@ixiacom.com> Cc: naveen yadav <yad.naveen@gmail.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Cc: linux-mm@kvack.org Patchwork: https://patchwork.linux-mips.org/patch/2244/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2011-05-19MIPS: XLR, XLS: Add PCI support.Jayachandran C4-1/+321
Adds pci/pci-xlr.c to support for XLR PCI/PCI-X interface and XLS PCIe interface. Update irq.c to ack PCI interrupts, use irq handler data to do the PCI/PCIe bus ack. Signed-off-by: Jayachandran C <jayachandranc@netlogicmicro.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2337/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2011-05-19MIPS: Add default configuration for XLR/XLS processorsJayachandran C1-0/+574
Enable XLR CPU support, SMP, initramfs based root filesystem etc. [ralf@linux-mips.org: shrink the defconfig file through make savedefconfig.] Signed-off-by: Jayachandran C <jayachandranc@netlogicmicro.com> To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2338/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2011-05-19MIPS: Kconfig and Makefile update for Netlogic XLR/XLSJayachandran C7-0/+67
Add NLM_XLR_BOARD, CPU_XLR and other config options Makefile updates, mostly based on r4k Signed-off-by: Jayachandran C <jayachandranc@netlogicmicro.com> To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2334/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2011-05-19MIPS: Platform files for XLR/XLS processor supportJayachandran C14-0/+1637
* include/asm/netlogic added with files common for all Netlogic processors (common with XLP which will be added later) * include/asm/netlogic/xlr for XLR/XLS chip specific files * netlogic/xlr for XLR/XLS platform files Signed-off-by: Jayachandran C <jayachandranc@netlogicmicro.com> To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2334/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2011-05-19MIPS: Netlogic: Cache, TLB support and feature overrides for XLRJayachandran C3-0/+4
CPU_XLR case added to mm/tlbex.c CPU_XLR case added to mm/c-r4k.c for PINDEX attribute Feature overrides for XLR cpu. Signed-off-by: Jayachandran C <jayachandranc@netlogicmicro.com> To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2333/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2011-05-19MIPS: Netlogic: mach-netlogic include filesJayachandran C3-0/+87
Add war.h and irq.h with XLR/XLS definitions. Signed-off-by: Jayachandran C <jayachandranc@netlogicmicro.com> To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2331/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2011-05-19MIPS: Netlogic XLR/XLS processor IDs.Jayachandran C2-0/+83
Add Netlogic Microsystems company ID and processor IDs for XLR and XLS processors for CPU probe. Add CPU_XLR to cpu_type_enum. Signed-off-by: Jayachandran C <jayachandranc@netlogicmicro.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2367/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2011-05-18Merge branch 'devicetree/merge' of git://git.secretlab.ca/git/linux-2.6Linus Torvalds4-7/+20
* 'devicetree/merge' of git://git.secretlab.ca/git/linux-2.6: drivercore: revert addition of of_match to struct device of: fix race when matching drivers
2011-05-18Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/upstream-linusLinus Torvalds4-8/+6
* 'upstream' of git://git.linux-mips.org/pub/scm/upstream-linus: MIPS: Kludge IP27 build for 2.6.39. MIPS: AR7: Fix GPIO register size for Titan variant. MIPS: Fix duplicate invocation of notify_die. MIPS: RB532: Fix iomap resource size miscalculation.
2011-05-18drivercore: revert addition of of_match to struct deviceGrant Likely4-7/+20
Commit b826291c, "drivercore/dt: add a match table pointer to struct device" added an of_match pointer to struct device to cache the of_match_table entry discovered at driver match time. This was unsafe because matching is not an atomic operation with probing a driver. If two or more drivers are attempted to be matched to a driver at the same time, then the cached matching entry pointer could get overwritten. This patch reverts the of_match cache pointer and reworks all users to call of_match_device() directly instead. Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2011-05-18MIPS: Kludge IP27 build for 2.6.39.Ralf Baechle1-0/+2
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2011-05-18MIPS: AR7: Fix GPIO register size for Titan variant.Florian Fainelli1-3/+1
The 'size' variable contains the correct register size for both AR7 and Titan, but we never used it to ioremap the correct register size. This problem only shows up on Titan. [ralf@linux-mips.org: Fixed the fix. The original patch as in patchwork recognizes the problem correctly then fails to fix it ...] Reported-by: Alexander Clouter <alex@digriz.org.uk> Signed-off-by: Florian Fainelli <florian@openwrt.org> Patchwork: https://patchwork.linux-mips.org/patch/2380/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2011-05-18MIPS: Fix duplicate invocation of notify_die.Ralf Baechle1-4/+2
Initial patch by Yury Polyanskiy <ypolyans@princeton.edu>. Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/2373/
2011-05-18MIPS: RB532: Fix iomap resource size miscalculation.Ralf Baechle1-1/+1
This is the MIPS portion of Joe Perches <joe@perches.com>'s https://patchwork.linux-mips.org/patch/2172/ which seems to have been lost in time and space. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2011-05-18Merge branch 'x86-fixes-for-linus' of ↵Linus Torvalds9-46/+147
git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip * 'x86-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip: x86, AMD: Fix ARAT feature setting again Revert "x86, AMD: Fix APIC timer erratum 400 affecting K8 Rev.A-E processors" x86, apic: Fix spurious error interrupts triggering on all non-boot APs x86, mce, AMD: Fix leaving freed data in a list x86: Fix UV BAU for non-consecutive nasids x86, UV: Fix NMI handler for UV platforms
2011-05-18Merge branch 'perf-fixes-for-linus' of ↵Linus Torvalds1-2/+3
git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip * 'perf-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip: perf evlist: Fix per thread mmap setup perf tools: Honour the cpu list parameter when also monitoring a thread list kprobes, x86: Disable irqs during optimized callback
2011-05-18um: fix abortRichard Weinberger1-1/+22
os_dump_core() uses abort() to terminate UML in case of an fatal error. glibc's abort() calls raise(SIGABRT) which makes use of tgkill(). tgkill() has no effect within UML's kernel threads because they are not pthreads. As fallback abort() executes an invalid instruction to terminate the process. Therefore UML gets killed by SIGSEGV and leaves a ugly log entry in the host's kernel ring buffer. To get rid of this we use our own abort routine. Signed-off-by: Richard Weinberger <richard@nod.at> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2011-05-17x86, AMD: Fix ARAT feature setting againBorislav Petkov1-1/+1
Trying to enable the local APIC timer on early K8 revisions uncovers a number of other issues with it, in conjunction with the C1E enter path on AMD. Fixing those causes much more churn and troubles than the benefit of using that timer brings so don't enable it on K8 at all, falling back to the original functionality the kernel had wrt to that. Reported-and-bisected-by: Nick Bowler <nbowler@elliptictech.com> Cc: Boris Ostrovsky <Boris.Ostrovsky@amd.com> Cc: Andreas Herrmann <andreas.herrmann3@amd.com> Cc: Greg Kroah-Hartman <greg@kroah.com> Cc: Hans Rosenfeld <hans.rosenfeld@amd.com> Cc: Nick Bowler <nbowler@elliptictech.com> Cc: Joerg-Volker-Peetz <jvpeetz@web.de> Signed-off-by: Borislav Petkov <borislav.petkov@amd.com> Link: http://lkml.kernel.org/r/1305636919-31165-3-git-send-email-bp@amd64.org Signed-off-by: Ingo Molnar <mingo@elte.hu>
2011-05-17Revert "x86, AMD: Fix APIC timer erratum 400 affecting K8 Rev.A-E processors"Borislav Petkov1-1/+1
This reverts commit e20a2d205c05cef6b5783df339a7d54adeb50962, as it crashes certain boxes with specific AMD CPU models. Moving the lower endpoint of the Erratum 400 check to accomodate earlier K8 revisions (A-E) opens a can of worms which is simply not worth to fix properly by tweaking the errata checking framework: * missing IntPenging MSR on revisions < CG cause #GP: http://marc.info/?l=linux-kernel&m=130541471818831 * makes earlier revisions use the LAPIC timer instead of the C1E idle routine which switches to HPET, thus not waking up in deeper C-states: http://lkml.org/lkml/2011/4/24/20 Therefore, leave the original boundary starting with K8-revF. Signed-off-by: Ingo Molnar <mingo@elte.hu>
2011-05-16Merge branch 'omap-fixes-for-linus' of ↵Linus Torvalds2-0/+3
git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap-2.6 * 'omap-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap-2.6: OMAP3: set the core dpll clk rate in its set_rate function omap: iommu: Return IRQ_HANDLED in fault handler when no fault occured
2011-05-16x86, apic: Fix spurious error interrupts triggering on all non-boot APsYouquan Song2-5/+8
This patch fixes a bug reported by a customer, who found that many unreasonable error interrupts reported on all non-boot CPUs (APs) during the system boot stage. According to Chapter 10 of Intel Software Developer Manual Volume 3A, Local APIC may signal an illegal vector error when an LVT entry is set as an illegal vector value (0~15) under FIXED delivery mode (bits 8-11 is 0), regardless of whether the mask bit is set or an interrupt actually happen. These errors are seen as error interrupts. The initial value of thermal LVT entries on all APs always reads 0x10000 because APs are woken up by BSP issuing INIT-SIPI-SIPI sequence to them and LVT registers are reset to 0s except for the mask bits which are set to 1s when APs receive INIT IPI. When the BIOS takes over the thermal throttling interrupt, the LVT thermal deliver mode should be SMI and it is required from the kernel to keep AP's LVT thermal monitoring register programmed as such as well. This issue happens when BIOS does not take over thermal throttling interrupt, AP's LVT thermal monitor register will be restored to 0x10000 which means vector 0 and fixed deliver mode, so all APs will signal illegal vector error interrupts. This patch check if interrupt delivery mode is not fixed mode before restoring AP's LVT thermal monitor register. Signed-off-by: Youquan Song <youquan.song@intel.com> Acked-by: Suresh Siddha <suresh.b.siddha@intel.com> Acked-by: Yong Wang <yong.y.wang@intel.com> Cc: hpa@linux.intel.com Cc: joe@perches.com Cc: jbaron@redhat.com Cc: trenn@suse.de Cc: kent.liu@intel.com Cc: chaohong.guo@intel.com Cc: <stable@kernel.org> # As far back as possible Link: http://lkml.kernel.org/r/1303402963-17738-1-git-send-email-youquan.song@intel.com Signed-off-by: Ingo Molnar <mingo@elte.hu>
2011-05-13alpha: Wire up syscalls new to 2.6.39Michael Cree2-5/+13
Wire up the syscalls: name_to_handle_at open_by_handle_at clock_adjtime syncfs and adjust some whitespace in the neighbourhood to align commments. Signed-off-by: Michael Cree <mcree@orcon.net.nz> Signed-off-by: Matt Turner <mattst88@gmail.com>
2011-05-13alpha: convert to clocksource_register_hzJohn Stultz1-2/+1
Converts alpha to use clocksource_register_hz. Signed-off-by: John Stultz <johnstul@us.ibm.com> CC: Richard Henderson <rth@twiddle.net> CC: Ivan Kokshaysky <ink@jurassic.park.msu.ru> CC: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Matt Turner <mattst88@gmail.com>
2011-05-13x86, mce, AMD: Fix leaving freed data in a listJulia Lawall1-0/+1
b may be added to a list, but is not removed before being freed in the case of an error. This is done in the corresponding deallocation function, so the code here has been changed to follow that. The sematic match that finds this problem is as follows: (http://coccinelle.lip6.fr/) // <smpl> @@ expression E,E1,E2; identifier l; @@ *list_add(&E->l,E1); ... when != E1 when != list_del(&E->l) when != list_del_init(&E->l) when != E = E2 *kfree(E);// </smpl> Signed-off-by: Julia Lawall <julia@diku.dk> Cc: Borislav Petkov <borislav.petkov@amd.com> Cc: Robert Richter <robert.richter@amd.com> Cc: Yinghai Lu <yinghai@kernel.org> Cc: Andreas Herrmann <andreas.herrmann3@amd.com> Cc: <stable@kernel.org> Link: http://lkml.kernel.org/r/1305294731-12127-1-git-send-email-julia@diku.dk Signed-off-by: Ingo Molnar <mingo@elte.hu>
2011-05-13OMAP3: set the core dpll clk rate in its set_rate functionAvinash H.M1-0/+1
The debug l3_ick/rate is not displaying the actual rate of the clock in hardware. This is because, the core dpll set_rate function doesn't update the clk.rate. After fixing, the l3_ick/rate is displaying proper values. Signed-off-by: Shweta Gulati <shweta.gulati@ti.com> Signed-off-by: Avinash.H.M <avinashhm@ti.com> Cc: Rajendra Nayak <rnayak@ti.com> Cc: Paul Wamsley <paul@pwsan.com> Acked-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2011-05-12x86: Fix UV BAU for non-consecutive nasidsCliff Wickman2-33/+76
This is a fix for the SGI Altix-UV Broadcast Assist Unit code, which is used for TLB flushing. Certain hardware configurations (that customers are ordering) cause nasids (numa address space id's) to be non-consecutive. Specifically, once you have more than 4 blades in a IRU (Individual Rack Unit - or 1/2 rack) but less than the maximum of 16, the nasid numbering becomes non-consecutive. This currently results in a 'catastrophic error' (CATERR) detected by the firmware during OS boot. The BAU is generating an 'INTD' request that is targeting a non-existent nasid value. Such configurations may also occur when a blade is configured off because of hardware errors. (There is one UV hub per blade.) This patch is required to support such configurations. The problem with the tlb_uv.c code is that is using the consecutive hub numbers as indices to the BAU distribution bit map. These are simply the ordinal position of the hub or blade within its partition. It should be using physical node numbers (pnodes), which correspond to the physical nasid values. Use of the hub number only works as long as the nasids in the partition are consecutive and increase with a stride of 1. This patch changes the index to be the pnode number, thus allowing nasids to be non-consecutive. It also provides a table in local memory for each cpu to translate target cpu number to target pnode and nasid. And it improves naming to properly reflect 'node' and 'uvhub' versus 'nasid'. Signed-off-by: Cliff Wickman <cpw@sgi.com> Cc: <stable@kernel.org> Link: http://lkml.kernel.org/r/E1QJmxX-0002Mz-Fk@eag09.americas.sgi.com Signed-off-by: Ingo Molnar <mingo@elte.hu>
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-30 19:40:11 +0000