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2011-10-24ARM: 7139/1: fix compilation with CONFIG_ARM_ATAG_DTB_COMPAT and large ↵Nicolas Pitre1-1/+2
TEXT_OFFSET If TEXT_OFFSET is too large (e.g. like on MSM) the resulting immediate argument gets wider than 8 bits. Noticed by David Brown <davidb@codeaurora.org> Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-10-23Merge branch 'ppi-irq-core-for-rmk' of ↵Russell King46-307/+829
git://github.com/mzyngier/arm-platforms into devel-stable
2011-10-23ARM: gic, local timers: use the request_percpu_irq() interfaceMarc Zyngier8-111/+99
This patch remove the hardcoded link between local timers and PPIs, and convert the PPI users (TWD, MCT and MSM timers) to the new *_percpu_irq interface. Also some collateral cleanup (local_timer_ack() is gone, and the interrupt handler is strictly private to each driver). PPIs are now useable for more than just the local timers. Additional testing by David Brown (msm8250 and msm8660) and Shawn Guo (imx6q). Cc: David Brown <davidb@codeaurora.org> Cc: Thomas Gleixner <tglx@linutronix.de> Acked-by: David Brown <davidb@codeaurora.org> Tested-by: David Brown <davidb@codeaurora.org> Tested-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2011-10-23ARM: gic: consolidate PPI handlingMarc Zyngier14-178/+88
PPI handling is a bit of an odd beast. It uses its own low level handling code and is hardwired to the local timers (hence lacking a registration interface). Instead, switch the low handling to the normal SPI handling code. PPIs are handled by the handle_percpu_devid_irq flow. This also allows the removal of some duplicated code. Cc: Kukjin Kim <kgene.kim@samsung.com> Cc: David Brown <davidb@codeaurora.org> Cc: Bryan Huntsman <bryanh@codeaurora.org> Cc: Tony Lindgren <tony@atomide.com> Cc: Paul Mundt <lethal@linux-sh.org> Cc: Magnus Damm <magnus.damm@gmail.com> Cc: Thomas Gleixner <tglx@linutronix.de> Acked-by: David Brown <davidb@codeaurora.org> Tested-by: David Brown <davidb@codeaurora.org> Tested-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2011-10-23Merge commit '32cffdd' into ppi-irq-core-for-rmkMarc Zyngier8-35/+364
2011-10-20ARM: smp: fix clipping of number of CPUsRussell King8-28/+38
Rather than clipping the number of CPUs using the compile-time NR_CPUS constant, use the runtime nr_cpu_ids value instead. This allows the nr_cpus command line option to work as expected. Cc: <stable@kernel.org> Reported-by: Mark Salter <msalter@redhat.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-10-18Merge branch 'mach_memory_h' of git://git.linaro.org/people/nico/linux into ↵Russell King117-1168/+347
devel-stable
2011-10-17ARM: 7115/4: move __exception and friends to asm/exception.hJamie Iles7-9/+25
The definition of __exception_irq_entry for CONFIG_FUNCTION_GRAPH_TRACER=y needs linux/ftrace.h, but this creates a circular dependency with it's current home in asm/system.h. Create asm/exception.h and update all current users. v4: - rebase to rmk/for-next v3: - remove redundant includes of linux/ftrace.h v2: - document the usage restricitions of __exception* Cc: Zoltan Devai <zdevai@gmail.com> Signed-off-by: Jamie Iles <jamie@jamieiles.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-10-17ARM: 7124/1: smp: Add a localtimer handler callable from C codeShawn Guo2-0/+9
In order to be able to handle localtimer directly from C code instead of assembly code, introduce handle_local_timer(), which is modeled after handle_IRQ(). Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-10-17ARM: 7123/1: smp: Add an IPI handler callable from C codeShawn Guo2-0/+10
In order to be able to handle IPI directly from C code instead of assembly code, introduce handle_IPI(), which is modeled after handle_IRQ(). Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-10-17ARM: 7100/1: smp_scu: remove __init annotation from scu_enable()Shawn Guo1-1/+1
When Cortex-A9 MPCore resumes from Dormant or Shutdown modes, SCU needs to be re-enabled. This patch removes __init annotation from function scu_enable(), so that platform resume procedure can call it to re-enable SCU. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-10-17ARM: 7061/1: gic: convert logical CPU numbers into physical numbersWill Deacon1-3/+14
The GIC driver must convert logical CPU numbers passed in from Linux into physical CPU numbers that are understood by the hardware. This patch uses the new cpu_logical_map macro for performing the conversion inside the GIC driver. Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-10-17ARM: 7060/1: smp: populate logical CPU mapping during bootWill Deacon2-0/+21
To allow booting Linux on a CPU with physical ID != 0, we need to provide a mapping from the logical CPU number to the physical CPU number. This patch adds such a mapping and populates it during boot. Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-10-17ARM: 7011/1: Add ARM cpu topology definitionVincent Guittot6-0/+218
The affinity between ARM processors is defined in the MPIDR register. We can identify which processors are in the same cluster, and which ones have performance interdependency. We can define the cpu topology of ARM platform, that is then used by sched_mc and sched_smt. The default state of sched_mc and sched_smt config is disable. When enabled, the behavior of the scheduler can be modified with sched_mc_power_savings and sched_smt_power_savings sysfs interfaces. Changes since v4 : * Remove unnecessary parentheses and blank lines Changes since v3 : * Update the format of printk message * Remove blank line Changes since v2 : * Update the commit message and some comments Changes since v1 : * Update the commit message * Add read_cpuid_mpidr in arch/arm/include/asm/cputype.h * Modify header of arch/arm/kernel/topology.c * Modify tests and manipulation of MPIDR's bitfields * Modify the place and dependancy of the config * Modify Noop functions Signed-off-by: Vincent Guittot <vincent.guittot@linaro.org> Reviewed-by: Amit Kucheria <amit.kucheria@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-10-13ARM: switch from NO_MACH_MEMORY_H to NEED_MACH_MEMORY_HNicolas Pitre3-41/+24
Given that we want the default to not have any <mach/memory.h> and given that there are now fewer cases where it is still provided than the cases where it is not at this point, this makes sense to invert the logic and just identify the exception cases. The word "need" instead of "have" was chosen to construct the config symbol so not to suggest that having a mach/memory.h file is actually a feature that one should aim for. Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
2011-10-13ARM: mach-s5p64x0: remove mach/memory.hNicolas Pitre2-18/+1
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
2011-10-13ARM: mach-s3c64xx: remove mach/memory.hNicolas Pitre2-18/+1
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
2011-10-13ARM: plat-mxc: remove mach/memory.hNicolas Pitre2-43/+1
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
2011-10-13ARM: mach-prima2: remove mach/memory.hNicolas Pitre3-17/+3
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
2011-10-13ARM: mach-zynq: remove mach/memory.hNicolas Pitre2-22/+1
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
2011-10-13ARM: mach-bcmring: remove mach/memory.hNicolas Pitre3-30/+2
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
2011-10-13ARM: mach-davinci: remove mach/memory.hNicolas Pitre5-41/+7
Move some DDR2 related defines into a private <mach/ddr2.h> beforehand. Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
2011-10-13ARM: mach-pxa: remove mach/memory.hNicolas Pitre3-21/+2
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
2011-10-13ARM: mach-ixp4xx: remove mach/memory.hNicolas Pitre2-17/+1
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
2011-10-13ARM: mach-h720x: remove mach/memory.hNicolas Pitre2-11/+1
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
2011-10-13ARM: mach-vt8500: remove mach/memory.hNicolas Pitre2-28/+1
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
2011-10-13ARM: mach-s5pc100: remove mach/memory.hNicolas Pitre2-18/+1
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
2011-10-13ARM: mach-tegra: remove mach/memory.hNicolas Pitre2-28/+1
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
2011-10-13ARM: plat-tcc: remove mach/memory.hNicolas Pitre2-18/+1
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
2011-10-13ARM: mach-mmp: remove mach/memory.hNicolas Pitre2-14/+1
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
2011-10-13ARM: mach-cns3xxx: remove mach/memory.hNicolas Pitre2-26/+1
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
2011-10-13ARM: mach-nuc93x: remove mach/memory.hNicolas Pitre2-21/+1
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
2011-10-13ARM: mach-mxs: remove mach/memory.hNicolas Pitre2-24/+1
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
2011-10-13ARM: spear: remove mach/memory.h and plat/memory.hNicolas Pitre4-58/+1
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
2011-10-13ARM: mach-msm: remove mach/memory.hNicolas Pitre2-35/+1
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
2011-10-13ARM: mach-gemini: remove mach/memory.hNicolas Pitre2-19/+1
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
2011-10-13ARM: mach-lpc32xx: remove mach/memory.hNicolas Pitre2-27/+1
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
2011-10-13ARM: mach-netx: remove mach/memory.hNicolas Pitre2-26/+1
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
2011-10-13ARM: mach-versatile: remove mach/memory.hNicolas Pitre2-28/+1
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
2011-10-13ARM: mach-ux500: remove mach/memory.hNicolas Pitre2-18/+1
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
2011-10-13ARM: mach-nomadik: remove mach/memory.hNicolas Pitre2-28/+1
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
2011-10-13ARM: mach-iop32x: remove mach/memory.hNicolas Pitre2-13/+1
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
2011-10-13ARM: mach-pnx4008: remove mach/memory.hNicolas Pitre2-21/+1
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
2011-10-13ARM: mach-w90x900: remove mach/memory.hNicolas Pitre2-23/+1
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
2011-10-13ARM: mach-vexpress: remove mach/memory.hNicolas Pitre2-25/+1
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
2011-10-13ARM: mach-mv78xx0: remove mach/memory.hNicolas Pitre2-10/+1
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
2011-10-13ARM: mach-s3c2410: remove memory.hNicolas Pitre3-36/+1
This also removes the mach/s3c2400 version which was probably never used due to the fact that we have this line in arch/arm/Makefile: machine-$(CONFIG_ARCH_S3C2410) := s3c2410 s3c2400 [...] This is later used to construct the search path for: The compiler would be looking into mach-s3c2410 and picking up this version first. Any config that was actually expecting the mach-s3c2400 version was therefore producing a broken kernel binary. Not relying on any of them anymore would fix that issue. Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
2011-10-08ARM: 7127/1: hw_breakpoint: skip v7-specific reset on v6 coresWill Deacon1-0/+5
ARMv6 cores do not implement the DBGOSLAR register, so we don't need to try and clear it on boot. Furthermore, the VCR is zeroed out of reset, so we don't need to zero it explicitly when a CPU comes online. Tested-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-10-04genirq: Fix fatfinered fixup reallyThomas Gleixner1-1/+1
Putting the argument inside the quote does not really help. Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2011-10-03genirq: percpu: allow interrupt type to be set at enable timeMarc Zyngier2-2/+15
As request_percpu_irq() doesn't allow for a percpu interrupt to have its type configured (it is generally impossible to configure it on all CPUs at once), add a 'type' argument to enable_percpu_irq(). This allows some low-level, board specific init code to be switched to a generic API. [ tglx: Added WARN_ON argument ] Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Cc: Abhijeet Dharmapurikar <adharmap@codeaurora.org> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
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