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2014-06-09Tizen: set permissive mode for smackdevel/aarch64Chanho Park1-0/+1
Change-Id: I45f14ee28bc22b73049a209ee37be68f5f1a0e89 Signed-off-by: Chanho Park <>
2014-06-09smack: add permissive mode for debugging purposeChanho Park5-0/+111
Change-Id: I4389736181c63ae5af670695784cedd21631ba89 Signed-off-by: Chanho Park <>
2014-04-16tizen: arm64: update tizen_aemv8_defconfigChanho Park1-34/+437
Change-Id: Ie97982a2b7288bace26dc26877e904dd86e8e1b7 Signed-off-by: Chanho Park <>
2014-04-16drm/pl111: set default mode to 1024x768x16bppChanho Park2-3/+3
Signed-off-by: Chanho Park <>
2014-04-16tizen: arm: add vexpress defconfig for qemu-armChanho Park1-0/+1937
Signed-off-by: Chanho Park <>
2014-04-16drm/pl111: always use contiguous buffer for gem allocationChanho Park1-29/+7
Signed-off-by: Chanho Park <>
2014-04-16drm/pl111: add missing ioctl connectionChanho Park1-0/+4
Signed-off-by: Chanho Park <>
2014-04-16drm/pl111: add fb helper device to create fb during probeChanho Park9-3/+459
Signed-off-by: Chanho Park <>
2014-04-16drm/pl111: Initial drm/kms driver for pl111Tom Cooksey19-0/+3268
This is a mode-setting driver for the pl111 CLCD display controller found on various ARM reference platforms such as the Versatile Express. The driver supports setting of a single mode (640x480) and has only been tested on Versatile Express with a Cortex-A9 core tile. Known issues: * It still includes code to use KDS, which is not going upstream. * It abuses flags parameter of DRM_IOCTL_MODE_CREATE_DUMB to also allocate buffers for the GPU. * The v_sync handling needs work - a work queue is a little overkill. * Doesn't support the import half of PRIME properly, only export * Need to validate src rectangle size in when updating the cursor plane. * Only supports 640x480 mode, which is hard-coded. * We register both an amba & platform driver, only need one. Signed-off-by: Tom Cooksey <>
2014-04-16arm64: mm: define dma_{alloc/free}_writecombineChanho Park1-0/+16
This patch adds dma_alloc/free_writecombine macros for arm64. The ARMv8 supports 4 types of device memory. The write-combine is Device-GRE type which allows Device Gathering, Reordering and Early Write Acknowledgement. It almost same with normal memory except restricted speculative accesses. If we want to use a same driver which used in older ARM, we should define writecombine functions. Current AArch64 uses swiotlb for dma-mapping. Thus, we don't need to implement the dma-mapping supports such device memory types. Until it is implemented, we will use coherent_alloc. Signed-off-by: Chanho Park <>
2014-04-16video: Versatile Express DVI output driverPawel Moll3-0/+231
Versatile Express' DVI video output can be connected to one the three sources - motherboard's CLCD controller or a video signal generated by one of the daughterboards. This driver configures the muxer FPGA so the output displays content of one of the framebuffers in the system (0 by default, can be changed by user writing to the "fb" sysfs attribute of the muxfpga device). It will also set up the display formatter mode and keep it up to date with mode changes requested by the user (eg. with fbset tool). Signed-off-by: Pawel Moll <>
2014-04-16sched: Add 'flags' argument to sched_{set,get}attr() syscallsPeter Zijlstra2-7/+10
Because of a recent syscall design debate; its deemed appropriate for each syscall to have a flags argument for future extension; without immediately requiring new syscalls. Cc: Cc: Ingo Molnar <> Suggested-by: Michael Kerrisk <> Signed-off-by: Peter Zijlstra <> Link: Signed-off-by: Thomas Gleixner <>
2014-04-16sched: Add new scheduler syscalls to support an extended scheduling ↵Dario Faggioli9-24/+326
parameters ABI Add the syscalls needed for supporting scheduling algorithms with extended scheduling parameters (e.g., SCHED_DEADLINE). In general, it makes possible to specify a periodic/sporadic task, that executes for a given amount of runtime at each instance, and is scheduled according to the urgency of their own timing constraints, i.e.: - a (maximum/typical) instance execution time, - a minimum interval between consecutive instances, - a time constraint by which each instance must be completed. Thus, both the data structure that holds the scheduling parameters of the tasks and the system calls dealing with it must be extended. Unfortunately, modifying the existing struct sched_param would break the ABI and result in potentially serious compatibility issues with legacy binaries. For these reasons, this patch: - defines the new struct sched_attr, containing all the fields that are necessary for specifying a task in the computational model described above; - defines and implements the new scheduling related syscalls that manipulate it, i.e., sched_setattr() and sched_getattr(). Syscalls are introduced for x86 (32 and 64 bits) and ARM only, as a proof of concept and for developing and testing purposes. Making them available on other architectures is straightforward. Since no "user" for these new parameters is introduced in this patch, the implementation of the new system calls is just identical to their already existing counterpart. Future patches that implement scheduling policies able to exploit the new data structure must also take care of modifying the sched_*attr() calls accordingly with their own purposes. Signed-off-by: Dario Faggioli <> [ Rewrote to use sched_attr. ] Signed-off-by: Juri Lelli <> [ Removed sched_setscheduler2() for now. ] Signed-off-by: Peter Zijlstra <> Link: Signed-off-by: Ingo Molnar <>
2014-04-16usb: host: make USB_ARCH_HAS_?HCI obsoleteArnd Bergmann2-66/+8
The three options USB_ARCH_HAS_{EHCI,OHCI,XHCI} are all well beyond their recommended shelf life. They have caused numerous build failures over the years because they are never completely correct, and with the move to splitting out the platform specific back-ends out of the driver, there is no real need for them any more. Also, the use of making USB_ARCH_HAS_HCD depend on it is questionable since one can always enable dummy_hc these days. This patch enables them unconditionally for all platforms and architectures, which means it is now possible to build host controller drivers for machines that are known not to come with this hardware, but that is just how we treat most other drivers. In order to minimise the impact on existing architecture code and defconfig files, all the Kconfig are left present for now. All platforms that currently do 'select USB_ARCH_HAS_*' should subsequently be changed not to select that. All drivers depending on USB_ARCH_HAS_HCD should be changed to depend on USB_SUPPORT instead. Signed-off-by: Arnd Bergmann <> Acked-by: Alan Stern <> Cc: Sarah Sharp <> Signed-off-by: Greg Kroah-Hartman <> Conflicts: drivers/usb/host/Kconfig Change-Id: I5b80b3f4617b192a06eed935bd39b666d3554fa6
2014-04-16net: smsc911x: don't artificially limit buildMark Rutland1-1/+1
Currently the SMSC911X driver may only be built for a specific set of architectures, being limited to do so by a Kconfig depends line. This means that if a platform wishes to use the driver, its architecture must be added to the list explicitly, introducing pointless churn. This may have been due to the driver's use of the {read,write}s{b,w,l} functions, which have since been replaced with the more standard io{read,write}{8,16,32}_rep. We can instead depend on HAS_IOMEM, which should prevent build issues while allowing the driver to be built for currently unlisted architectures, including x86 and arm64. This patch removes the explicit list of architectures from the driver's depend line, and replaces it with a dependency on HAS_IOMEM. Signed-off-by: Mark Rutland <> Cc: David S. Miller <> Cc: Arnd Bergmann <> Cc: Signed-off-by: David S. Miller <>
2014-04-16mm/cma: Move dma contiguous changes into a seperate configAneesh Kumar K.V6-22/+34
We want to use CMA for allocating hash page table and real mode area for PPC64. Hence move DMA contiguous related changes into a seperate config so that ppc64 can enable CMA without requiring DMA contiguous. Acked-by: Michal Nazarewicz <> Acked-by: Paul Mackerras <> Signed-off-by: Aneesh Kumar K.V <> [removed defconfig changes] Signed-off-by: Marek Szyprowski <> Conflicts: drivers/base/Kconfig mm/Kconfig Change-Id: Ic472ec40d73e55a6974b824ec9f6e75976369841
2014-04-16arm64: Clean up the default pgprot settingCatalin Marinas4-95/+50
The primary aim of this patchset is to remove the pgprot_default and prot_sect_default global variables and rely strictly on predefined values. The original goal was to be able to run SMP kernels on UP hardware by not setting the Shareability bit. However, it is unlikely to see UP ARMv8 hardware and even if we do, the Shareability bit is no longer assumed to disable cacheable accesses. A side effect is that the device mappings now have the Shareability attribute set. The hardware, however, should ignore it since Device accesses are always Outer Shareable. Following the removal of the two global variables, there is some PROT_* macro reshuffling and cleanup, including the __PAGE_* macros (replaced by PAGE_*). Signed-off-by: Catalin Marinas <>
2014-04-16Revert "arm64: Fix memory shareability attribute for ioremap_wc/cache"Catalin Marinas1-1/+1
This reverts commit 2f7dc6027522499582a520807cb9ffda589de47e. The above commit breaks the mapping type for Device memory because pgprot_default already contains a Normal memory type. pgprot_default is also not initialised early enough for earlyprintk resulting in an inconsistent memory mapping with 64K PAGE_SIZE configuration. Signed-off-by: Catalin Marinas <> Reported-by: Will Deacon <> Acked-by: Will Deacon <>
2014-04-16arm64: Introduce execute-only page access permissionsCatalin Marinas2-8/+8
The ARMv8 architecture allows execute-only user permissions by clearing the PTE_UXN and PTE_USER bits. The kernel, however, can still access such page. This patch changes the arm64 __P100 and __S100 protection_map[] macros to the new __PAGE_EXECONLY attributes. A side effect is that pte_valid_user() no longer triggers for __PAGE_EXECONLY since PTE_USER isn't set. To work around this, the check is done on the PTE_NG bit via the pte_valid_ng() macro. VM_READ is also checked now for page faults. Signed-off-by: Catalin Marinas <>
2014-04-16arm64: Expose ESR_EL1 information to user when SIGSEGV/SIGBUSCatalin Marinas2-0/+17
This information is useful for instruction emulators to detect read/write and access size without having to decode the faulting instruction. The current patch exports it via sigcontext (struct esr_context) and is only valid for SIGSEGV and SIGBUS. Signed-off-by: Catalin Marinas <>
2014-04-16arm64: Remove the aux_context structureCatalin Marinas2-41/+17
This patch removes the aux_context structure (and the containing file) to allow the placement of the _aarch64_ctx end magic based on the context stored on the signal stack. Signed-off-by: Catalin Marinas <>
2014-04-16arm64: Provide read/write fault information in compat signal handlersCatalin Marinas5-9/+20
For AArch32, bit 11 (WnR) of the FSR/ESR register is set when the fault was caused by a write access and applications like Qemu rely on such information being provided in sigcontext. This patch introduces the ESR_EL1 tracking for the arm64 kernel faults and sets bit 11 accordingly in compat sigcontext. Signed-off-by: Catalin Marinas <>
2014-04-16arm64: Remove boot thread synchronisation for spin-table release methodCatalin Marinas1-38/+1
The synchronisation with the boot thread already happens in __cpu_up() via wait_for_completion_timeout(). In addition, __cpu_up() calls are protected by the cpu_add_remove_lock mutex and already serialised. Signed-off-by: Catalin Marinas <>
2014-04-16arm64: Implement cache_line_size() based on CTR_EL0.CWGCatalin Marinas4-1/+41
The hardware provides the maximum cache line size in the system via the CTR_EL0.CWG bits. This patch implements the cache_line_size() function to read such information, together with a sanity check if the statically defined L1_CACHE_BYTES is smaller than the hardware value. Signed-off-by: Catalin Marinas <>
2014-04-16arm64: vexpress: Add CLCD support to the ARMv8 model platformCatalin Marinas3-0/+31
This patch enables CLCD support for the VE platform emulated by the ARMv8 software model. It requires DT support in the amba-clcd.c driver. Signed-off-by: Catalin Marinas <>
2014-04-16amba-clcd: separate ioremap framebuffer from DMA implementationWill Deacon1-28/+56
The amba-clcd device can be configured to use either DMA or, when this feature is not available, an ioremapped frambuffer in static ram. In the case of the latter, we must take care not to pass ioremapped addresses to dma_common_mmap, since this expects only addresses from dma_mmap_coherent, which reside in the kernel linear mapping. This patch reworks the fb initialisation code so that either DMA or IO implementations of the mmap/remove functions are chosen as appropriate. Signed-off-by: Will Deacon <> Signed-off-by: Catalin Marinas <>
2014-04-16amba-clcd: Only use dma_alloc_writecombine() if the arch supports itCatalin Marinas1-7/+20
This patch hides the dma_(alloc|free)_writecombine() calls behind macros to allow the amba-clcd.c to be used on architectures that do not provide this DMA API. With this patch, the *_writecombine() API is only used on ARM (AArch32). Signed-off-by: Catalin Marinas <>
2014-04-16amba-clcd: Remove check for 'reg' value in clcdfb_probeJon Medhurst1-15/+0
This check was attempting to ensure only one clcd device in the device-tree was probed, however the check fails in the valid case where the device is a child of another device and the 'reg' value is a offset from the start of that other device, not an absolute address. This occurs on vexpress with the motherboard clcd being a child of iofga. For now, we will just have to rely on there only being one display device specified in device-tree. Signed-off-by: Jon Medhurst <> Signed-off-by: Catalin Marinas <>
2014-04-16amba-clcd: Add Device Tree support to amba-clcd driverRyan Harkin1-0/+253
Add support to parse the display configuration from device tree. If the board does not provide platform specific functions in the struct clcd_board contained with the amba device info, then defaults are provided by the driver. The device tree configuration can either ask for a DMA setup or provide a framebuffer address to be remapped into the driver. Signed-off-by: Ryan Harkin <> Signed-off-by: Catalin Marinas <>
2014-04-16arm64: Fix DMA range invalidation for cache line unaligned buffersCatalin Marinas1-4/+11
If the buffer needing cache invalidation for inbound DMA does start or end on a cache line aligned address, we need to use the non-destructive clean&invalidate operation. This issue was introduced by commit 7363590d2c46 (arm64: Implement coherent DMA API based on swiotlb). Signed-off-by: Catalin Marinas <> Reported-by: Jon Medhurst (Tixy) <>
2014-04-16arm64: Add missing Kconfig for CONFIG_STRICT_DEVMEMLaura Abbott1-0/+14
The Kconfig for CONFIG_STRICT_DEVMEM is missing despite being used in mmap.c. Add it. Signed-off-by: Laura Abbott <> Signed-off-by: Catalin Marinas <>
2014-04-16arm64: fix !CONFIG_COMPAT build failuresMark Salter2-0/+6
Recent arm64 builds using CONFIG_ARM64_64K_PAGES are failing with: arch/arm64/kernel/perf_regs.c: In function ‘perf_reg_abi’: arch/arm64/kernel/perf_regs.c:41:2: error: implicit declaration of function ‘is_compat_thread’ arch/arm64/kernel/perf_event.c:1398:2: error: unknown type name ‘compat_uptr_t’ This is due to some recent arm64 perf commits with compat support: commit 23c7d70d55c6d9: ARM64: perf: add support for frame pointer unwinding in compat mode commit 2ee0d7fd36a3f8: ARM64: perf: add support for perf registers API Those patches make the arm64 kernel unbuildable if CONFIG_COMPAT is not defined and CONFIG_ARM64_64K_PAGES depends on !CONFIG_COMPAT. This patch allows the arm64 kernel to build with and without CONFIG_COMPAT. Signed-off-by: Mark Salter <> Signed-off-by: Catalin Marinas <>
2014-04-16Revert "arm64: virt: ensure visibility of __boot_cpu_mode"Catalin Marinas1-13/+0
This reverts commit 82b2f495fba338d1e3098dde1df54944a9c19751. The __boot_cpu_mode variable is flushed in head.S after being written, therefore the additional cache flushing is no longer required. Signed-off-by: Catalin Marinas <>
2014-04-16arm64: Relax the kernel cache requirements for bootCatalin Marinas3-4/+45
With system caches for the host OS or architected caches for guest OS we cannot easily guarantee that there are no dirty or stale cache lines for the areas of memory written by the kernel during boot with the MMU off (therefore non-cacheable accesses). This patch adds the necessary cache maintenance during boot and relaxes the booting requirements. Signed-off-by: Catalin Marinas <>
2014-04-16arm64: Update the TCR_EL1 translation granule definitions for 16K pagesCatalin Marinas2-12/+19
The current TCR register setting in arch/arm64/mm/proc.S assumes that TCR_EL1.TG* fields are one bit wide and bit 31 is RES1 (reserved, set to 1). With the addition of 16K pages (currently unsupported in the kernel), the TCR_EL1.TG* fields have been extended to two bits. This patch updates the corresponding Linux definitions and drops the bit 31 setting in proc.S in favour of the new macros. Signed-off-by: Catalin Marinas <> Reported-by: Joe Sylve <>
2014-04-16ARM: topology: Make it clear that all CPUs need to be describedMark Brown1-0/+475
The ARMv8 code will reject incomplete topologies that omit some CPUs (and it's not clear that it's ever sensible to do so). Update the binding document to make this clear. Since we're reformatting the text also fix incorrect grammar in the final "Any other configuration..." section by removing "consider". Signed-off-by: Mark Brown <> Acked-by: Lorenzo Pieralisi <> Signed-off-by: Catalin Marinas <> Conflicts: Documentation/devicetree/bindings/arm/topology.txt Change-Id: Ic39525a02f6e20bbd34da7991c9723f9f04532e9
2014-04-16arm64: Remove pgprot_dmacoherent()Catalin Marinas2-5/+1
Since this macro is identical to pgprot_writecombine() and is only used in a single place, remove it completely to avoid confusion. On ARMv7+ processors, the coherent DMA mapping must be Normal NonCacheable (a.k.a. writecombine) to avoid mismatched hardware attribute aliases (with the kernel linear mapping as Normal Cacheable). Signed-off-by: Catalin Marinas <>
2014-04-16arm64: Support DMA_ATTR_WRITE_COMBINELaura Abbott1-2/+12
DMA_ATTR_WRITE_COMBINE is currently ignored. Set the pgprot appropriately for non coherent opperations. Signed-off-by: Laura Abbott <> Signed-off-by: Catalin Marinas <>
2014-04-16arm64: Implement custom mmap functions for dma mappingLaura Abbott1-0/+44
The current dma_ops do not specify an mmap function so maping falls back to the default implementation. There are at least two issues with using the default implementation: 1) The pgprot is always pgprot_noncached (strongly ordered) memory even with coherent operations 2) dma_common_mmap calls virt_to_page on the remapped non-coherent address which leads to invalid memory being mapped. Fix both these issue by implementing a custom mmap function which correctly accounts for remapped addresses and sets vm_pg_prot appropriately. Signed-off-by: Laura Abbott <> [ replaced "arm64_" with "__" prefix for consistency] Signed-off-by: Catalin Marinas <>
2014-04-16arm64: Fix __range_ok macroChristopher Covington1-2/+2
Without this, the following scenario is incorrectly determined to be invalid. addr 0x7f_ffffe000 size 8192 addr_limit 0x80_00000000 This behavior was observed while trying to vmsplice the stack as part of a CRIU dump of a process on a system started with the norandmaps kernel parameter. Signed-off-by: Christopher Covington <> Signed-off-by: Catalin Marinas <>
2014-04-16arm64: Fix duplicated Kconfig entriesMark Brown1-6/+0
Probably due to rebasing over the lengthy time it took to get the patch merged commit addea9ef055b (cpufreq: enable ARM drivers on arm64) added a duplicate Power management options section. Add CPUfreq to the CPU power management section and remove a duplicate include of the main power section. Signed-off-by: Mark Brown <> Signed-off-by: Catalin Marinas <>
2014-04-16arm64: mm: Route pmd thp functions through pte equivalentsSteve Capper1-28/+24
Rather than have separate hugetlb and transparent huge page pmd manipulation functions, re-wire our thp functions to simply call the pte equivalents. This allows THP to take advantage of the new PTE_WRITE logic introduced in: c2c93e5 arm64: mm: Introduce PTE_WRITE To represent splitting THPs we use the PTE_SPECIAL bit as this is not used for pmds. Signed-off-by: Steve Capper <> Signed-off-by: Catalin Marinas <>
2014-04-16arm64: rwsem: use asm-generic rwsem implementationWill Deacon2-1/+2
asm-generic offers an atomic-add based rwsem implementation, which can avoid the need for heavier, spinlock-based synchronisation on the fast path. This patch makes use of the optimised implementation for arm64 CPUs. Signed-off-by: Will Deacon <> Signed-off-by: Catalin Marinas <>
2014-04-16asm-generic: rwsem: de-PPCify rwsem.hWill Deacon1-5/+5
asm-generic/rwsem.h used to live under arch/powerpc. During its liberation to common code, a few references to its former home where preserved, in particular the definition of RWSEM_ACTIVE_MASK is predicated on CONFIG_PPC64. This patch updates the ifdefs and comments to architecturally neutral versions. Acked-by: Arnd Bergmann <> Acked-by: Richard Kuo <> Signed-off-by: Will Deacon <> Signed-off-by: Catalin Marinas <>
2014-04-16arm64: enable generic CPU feature modalias matching for this architectureArd Biesheuvel2-0/+30
This enables support for the generic CPU feature modalias implementation that wires up optional CPU features to udev based module autoprobing. A file <asm/cpufeature.h> is provided that maps CPU feature numbers to elf_hwcap bits, which is the standard way on arm64 to advertise optional CPU features both internally and to user space. Signed-off-by: Ard Biesheuvel <> [ removed unnecessary "!!"] Signed-off-by: Catalin Marinas <>
2014-04-16arm64: smp: make local symbol staticJingoo Han1-1/+1
Make smp_spin_table_cpu_postboot() static, because this function is used only in this file. Signed-off-by: Jingoo Han <> Signed-off-by: Catalin Marinas <>
2014-04-16arm64: debug: make local symbols staticJingoo Han1-2/+2
Make local symbols static, because these are used only in this file. Signed-off-by: Jingoo Han <> Signed-off-by: Catalin Marinas <>
2014-04-16ARM64: perf: support dwarf unwinding in compat modeJean Pihet2-2/+2
Add support for unwinding using the dwarf information in compat mode. Using the correct user stack pointer allows perf to record the frames correctly in the native and compat modes. Note that although the dwarf frame unwinding works ok using libunwind in native mode (on ARMv7 & ARMv8), some changes are required to the libunwind code for the compat mode. Those changes are posted separately on the libunwind mailing list. Tested on ARMv8 platform with v8 and compat v7 binaries, the latter are statically built. Signed-off-by: Jean Pihet <> Acked-by: Will Deacon <> Signed-off-by: Catalin Marinas <>
2014-04-16ARM64: perf: add support for frame pointer unwinding in compat modeJean Pihet1-8/+67
When profiling a 32-bit application, user space callchain unwinding using the frame pointer is performed in compat mode. The code is taken over from the AARCH32 code and adapted to work on AARCH64. Signed-off-by: Jean Pihet <> Acked-by: Will Deacon <> Signed-off-by: Catalin Marinas <>
2014-04-16ARM64: perf: add support for perf registers APIJean Pihet6-1/+90
This patch implements the functions required for the perf registers API, allowing the perf tool to interface kernel register dumps with libunwind in order to provide userspace backtracing. Compat mode is also supported. Only the general purpose user space registers are exported, i.e.: PERF_REG_ARM_X0, ... PERF_REG_ARM_X28, PERF_REG_ARM_FP, PERF_REG_ARM_LR, PERF_REG_ARM_SP, PERF_REG_ARM_PC and not the PERF_REG_ARM_V* registers. Signed-off-by: Jean Pihet <> Acked-by: Will Deacon <> Signed-off-by: Catalin Marinas <>