diff options
Diffstat (limited to 'arch/arm/plat-omap/include/mach')
68 files changed, 0 insertions, 9524 deletions
diff --git a/arch/arm/plat-omap/include/mach/blizzard.h b/arch/arm/plat-omap/include/mach/blizzard.h deleted file mode 100644 index 8d160f17137..00000000000 --- a/arch/arm/plat-omap/include/mach/blizzard.h +++ /dev/null @@ -1,12 +0,0 @@ -#ifndef _BLIZZARD_H -#define _BLIZZARD_H - -struct blizzard_platform_data { - void (*power_up)(struct device *dev); - void (*power_down)(struct device *dev); - unsigned long (*get_clock_rate)(struct device *dev); - - unsigned te_connected : 1; -}; - -#endif diff --git a/arch/arm/plat-omap/include/mach/board-ams-delta.h b/arch/arm/plat-omap/include/mach/board-ams-delta.h deleted file mode 100644 index 51b102dc906..00000000000 --- a/arch/arm/plat-omap/include/mach/board-ams-delta.h +++ /dev/null @@ -1,76 +0,0 @@ -/* - * arch/arm/plat-omap/include/mach/board-ams-delta.h - * - * Copyright (C) 2006 Jonathan McDowell <noodles@earth.li> - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ -#ifndef __ASM_ARCH_OMAP_AMS_DELTA_H -#define __ASM_ARCH_OMAP_AMS_DELTA_H - -#if defined (CONFIG_MACH_AMS_DELTA) - -#define AMS_DELTA_LATCH1_PHYS 0x01000000 -#define AMS_DELTA_LATCH1_VIRT 0xEA000000 -#define AMS_DELTA_MODEM_PHYS 0x04000000 -#define AMS_DELTA_MODEM_VIRT 0xEB000000 -#define AMS_DELTA_LATCH2_PHYS 0x08000000 -#define AMS_DELTA_LATCH2_VIRT 0xEC000000 - -#define AMS_DELTA_LATCH1_LED_CAMERA 0x01 -#define AMS_DELTA_LATCH1_LED_ADVERT 0x02 -#define AMS_DELTA_LATCH1_LED_EMAIL 0x04 -#define AMS_DELTA_LATCH1_LED_HANDSFREE 0x08 -#define AMS_DELTA_LATCH1_LED_VOICEMAIL 0x10 -#define AMS_DELTA_LATCH1_LED_VOICE 0x20 - -#define AMS_DELTA_LATCH2_LCD_VBLEN 0x0001 -#define AMS_DELTA_LATCH2_LCD_NDISP 0x0002 -#define AMS_DELTA_LATCH2_NAND_NCE 0x0004 -#define AMS_DELTA_LATCH2_NAND_NRE 0x0008 -#define AMS_DELTA_LATCH2_NAND_NWP 0x0010 -#define AMS_DELTA_LATCH2_NAND_NWE 0x0020 -#define AMS_DELTA_LATCH2_NAND_ALE 0x0040 -#define AMS_DELTA_LATCH2_NAND_CLE 0x0080 -#define AMD_DELTA_LATCH2_KEYBRD_PWR 0x0100 -#define AMD_DELTA_LATCH2_KEYBRD_DATA 0x0200 -#define AMD_DELTA_LATCH2_SCARD_RSTIN 0x0400 -#define AMD_DELTA_LATCH2_SCARD_CMDVCC 0x0800 -#define AMS_DELTA_LATCH2_MODEM_NRESET 0x1000 -#define AMS_DELTA_LATCH2_MODEM_CODEC 0x2000 - -#define AMS_DELTA_GPIO_PIN_KEYBRD_DATA 0 -#define AMS_DELTA_GPIO_PIN_KEYBRD_CLK 1 -#define AMS_DELTA_GPIO_PIN_MODEM_IRQ 2 -#define AMS_DELTA_GPIO_PIN_HOOK_SWITCH 4 -#define AMS_DELTA_GPIO_PIN_SCARD_NOFF 6 -#define AMS_DELTA_GPIO_PIN_SCARD_IO 7 -#define AMS_DELTA_GPIO_PIN_CONFIG 11 -#define AMS_DELTA_GPIO_PIN_NAND_RB 12 - -#ifndef __ASSEMBLY__ -void ams_delta_latch1_write(u8 mask, u8 value); -void ams_delta_latch2_write(u16 mask, u16 value); -#endif - -#endif /* CONFIG_MACH_AMS_DELTA */ - -#endif /* __ASM_ARCH_OMAP_AMS_DELTA_H */ diff --git a/arch/arm/plat-omap/include/mach/board-sx1.h b/arch/arm/plat-omap/include/mach/board-sx1.h deleted file mode 100644 index 355adbdaae3..00000000000 --- a/arch/arm/plat-omap/include/mach/board-sx1.h +++ /dev/null @@ -1,52 +0,0 @@ -/* - * Siemens SX1 board definitions - * - * Copyright: Vovan888 at gmail com - * - * This package is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED - * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. - */ - -#ifndef __ASM_ARCH_SX1_I2C_CHIPS_H -#define __ASM_ARCH_SX1_I2C_CHIPS_H - -#define SOFIA_MAX_LIGHT_VAL 0x2B - -#define SOFIA_I2C_ADDR 0x32 -/* Sofia reg 3 bits masks */ -#define SOFIA_POWER1_REG 0x03 - -#define SOFIA_USB_POWER 0x01 -#define SOFIA_MMC_POWER 0x04 -#define SOFIA_BLUETOOTH_POWER 0x08 -#define SOFIA_MMILIGHT_POWER 0x20 - -#define SOFIA_POWER2_REG 0x04 -#define SOFIA_BACKLIGHT_REG 0x06 -#define SOFIA_KEYLIGHT_REG 0x07 -#define SOFIA_DIMMING_REG 0x09 - - -/* Function Prototypes for SX1 devices control on I2C bus */ - -int sx1_setbacklight(u8 backlight); -int sx1_getbacklight(u8 *backlight); -int sx1_setkeylight(u8 keylight); -int sx1_getkeylight(u8 *keylight); - -int sx1_setmmipower(u8 onoff); -int sx1_setusbpower(u8 onoff); -int sx1_i2c_read_byte(u8 devaddr, u8 regoffset, u8 *value); -int sx1_i2c_write_byte(u8 devaddr, u8 regoffset, u8 value); - -/* MMC prototypes */ - -extern void sx1_mmc_init(void); -extern void sx1_mmc_slot_cover_handler(void *arg, int state); - -#endif /* __ASM_ARCH_SX1_I2C_CHIPS_H */ diff --git a/arch/arm/plat-omap/include/mach/board-voiceblue.h b/arch/arm/plat-omap/include/mach/board-voiceblue.h deleted file mode 100644 index 27916b210f5..00000000000 --- a/arch/arm/plat-omap/include/mach/board-voiceblue.h +++ /dev/null @@ -1,19 +0,0 @@ -/* - * Copyright (C) 2004 2N Telekomunikace, Ladislav Michl <michl@2n.cz> - * - * Hardware definitions for OMAP5910 based VoiceBlue board. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef __ASM_ARCH_VOICEBLUE_H -#define __ASM_ARCH_VOICEBLUE_H - -extern void voiceblue_wdt_enable(void); -extern void voiceblue_wdt_disable(void); -extern void voiceblue_wdt_ping(void); - -#endif /* __ASM_ARCH_VOICEBLUE_H */ - diff --git a/arch/arm/plat-omap/include/mach/board.h b/arch/arm/plat-omap/include/mach/board.h deleted file mode 100644 index 8e913c32281..00000000000 --- a/arch/arm/plat-omap/include/mach/board.h +++ /dev/null @@ -1,160 +0,0 @@ -/* - * arch/arm/plat-omap/include/mach/board.h - * - * Information structures for board-specific data - * - * Copyright (C) 2004 Nokia Corporation - * Written by Juha Yrjölä <juha.yrjola@nokia.com> - */ - -#ifndef _OMAP_BOARD_H -#define _OMAP_BOARD_H - -#include <linux/types.h> - -#include <mach/gpio-switch.h> - -/* Different peripheral ids */ -#define OMAP_TAG_CLOCK 0x4f01 -#define OMAP_TAG_LCD 0x4f05 -#define OMAP_TAG_GPIO_SWITCH 0x4f06 -#define OMAP_TAG_FBMEM 0x4f08 -#define OMAP_TAG_STI_CONSOLE 0x4f09 -#define OMAP_TAG_CAMERA_SENSOR 0x4f0a - -#define OMAP_TAG_BOOT_REASON 0x4f80 -#define OMAP_TAG_FLASH_PART 0x4f81 -#define OMAP_TAG_VERSION_STR 0x4f82 - -struct omap_clock_config { - /* 0 for 12 MHz, 1 for 13 MHz and 2 for 19.2 MHz */ - u8 system_clock_type; -}; - -struct omap_serial_console_config { - u8 console_uart; - u32 console_speed; -}; - -struct omap_sti_console_config { - unsigned enable:1; - u8 channel; -}; - -struct omap_camera_sensor_config { - u16 reset_gpio; - int (*power_on)(void * data); - int (*power_off)(void * data); -}; - -struct omap_usb_config { - /* Configure drivers according to the connectors on your board: - * - "A" connector (rectagular) - * ... for host/OHCI use, set "register_host". - * - "B" connector (squarish) or "Mini-B" - * ... for device/gadget use, set "register_dev". - * - "Mini-AB" connector (very similar to Mini-B) - * ... for OTG use as device OR host, initialize "otg" - */ - unsigned register_host:1; - unsigned register_dev:1; - u8 otg; /* port number, 1-based: usb1 == 2 */ - - u8 hmc_mode; - - /* implicitly true if otg: host supports remote wakeup? */ - u8 rwc; - - /* signaling pins used to talk to transceiver on usbN: - * 0 == usbN unused - * 2 == usb0-only, using internal transceiver - * 3 == 3 wire bidirectional - * 4 == 4 wire bidirectional - * 6 == 6 wire unidirectional (or TLL) - */ - u8 pins[3]; -}; - -struct omap_lcd_config { - char panel_name[16]; - char ctrl_name[16]; - s16 nreset_gpio; - u8 data_lines; -}; - -struct device; -struct fb_info; -struct omap_backlight_config { - int default_intensity; - int (*set_power)(struct device *dev, int state); - int (*check_fb)(struct fb_info *fb); -}; - -struct omap_fbmem_config { - u32 start; - u32 size; -}; - -struct omap_pwm_led_platform_data { - const char *name; - int intensity_timer; - int blink_timer; - void (*set_power)(struct omap_pwm_led_platform_data *self, int on_off); -}; - -/* See arch/arm/plat-omap/include/mach/gpio-switch.h for definitions */ -struct omap_gpio_switch_config { - char name[12]; - u16 gpio; - int flags:4; - int type:4; - int key_code:24; /* Linux key code */ -}; - -struct omap_uart_config { - /* Bit field of UARTs present; bit 0 --> UART1 */ - unsigned int enabled_uarts; -}; - - -struct omap_flash_part_config { - char part_table[0]; -}; - -struct omap_boot_reason_config { - char reason_str[12]; -}; - -struct omap_version_config { - char component[12]; - char version[12]; -}; - -struct omap_board_config_entry { - u16 tag; - u16 len; - u8 data[0]; -}; - -struct omap_board_config_kernel { - u16 tag; - const void *data; -}; - -extern const void *__omap_get_config(u16 tag, size_t len, int nr); - -#define omap_get_config(tag, type) \ - ((const type *) __omap_get_config((tag), sizeof(type), 0)) -#define omap_get_nr_config(tag, type, nr) \ - ((const type *) __omap_get_config((tag), sizeof(type), (nr))) - -extern const void *omap_get_var_config(u16 tag, size_t *len); - -extern struct omap_board_config_kernel *omap_board_config; -extern int omap_board_config_size; - - -/* for TI reference platforms sharing the same debug card */ -extern int debug_card_init(u32 addr, unsigned gpio); - -#endif diff --git a/arch/arm/plat-omap/include/mach/clkdev.h b/arch/arm/plat-omap/include/mach/clkdev.h deleted file mode 100644 index 730c49d1ebd..00000000000 --- a/arch/arm/plat-omap/include/mach/clkdev.h +++ /dev/null @@ -1,13 +0,0 @@ -#ifndef __MACH_CLKDEV_H -#define __MACH_CLKDEV_H - -static inline int __clk_get(struct clk *clk) -{ - return 1; -} - -static inline void __clk_put(struct clk *clk) -{ -} - -#endif diff --git a/arch/arm/plat-omap/include/mach/clock.h b/arch/arm/plat-omap/include/mach/clock.h deleted file mode 100644 index 4b8b0d65cbf..00000000000 --- a/arch/arm/plat-omap/include/mach/clock.h +++ /dev/null @@ -1,163 +0,0 @@ -/* - * arch/arm/plat-omap/include/mach/clock.h - * - * Copyright (C) 2004 - 2005 Nokia corporation - * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com> - * Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef __ARCH_ARM_OMAP_CLOCK_H -#define __ARCH_ARM_OMAP_CLOCK_H - -struct module; -struct clk; -struct clockdomain; - -struct clkops { - int (*enable)(struct clk *); - void (*disable)(struct clk *); - void (*find_idlest)(struct clk *, void __iomem **, u8 *); - void (*find_companion)(struct clk *, void __iomem **, u8 *); -}; - -#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \ - defined(CONFIG_ARCH_OMAP4) - -struct clksel_rate { - u32 val; - u8 div; - u8 flags; -}; - -struct clksel { - struct clk *parent; - const struct clksel_rate *rates; -}; - -struct dpll_data { - void __iomem *mult_div1_reg; - u32 mult_mask; - u32 div1_mask; - struct clk *clk_bypass; - struct clk *clk_ref; - void __iomem *control_reg; - u32 enable_mask; - unsigned int rate_tolerance; - unsigned long last_rounded_rate; - u16 last_rounded_m; - u8 last_rounded_n; - u8 min_divider; - u8 max_divider; - u32 max_tolerance; - u16 max_multiplier; -#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) - u8 modes; - void __iomem *autoidle_reg; - void __iomem *idlest_reg; - u32 autoidle_mask; - u32 freqsel_mask; - u32 idlest_mask; - u8 auto_recal_bit; - u8 recal_en_bit; - u8 recal_st_bit; -# endif -}; - -#endif - -struct clk { - struct list_head node; - const struct clkops *ops; - const char *name; - int id; - struct clk *parent; - struct list_head children; - struct list_head sibling; /* node for children */ - unsigned long rate; - __u32 flags; - void __iomem *enable_reg; - unsigned long (*recalc)(struct clk *); - int (*set_rate)(struct clk *, unsigned long); - long (*round_rate)(struct clk *, unsigned long); - void (*init)(struct clk *); - __u8 enable_bit; - __s8 usecount; -#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \ - defined(CONFIG_ARCH_OMAP4) - u8 fixed_div; - void __iomem *clksel_reg; - u32 clksel_mask; - const struct clksel *clksel; - struct dpll_data *dpll_data; - const char *clkdm_name; - struct clockdomain *clkdm; -#else - __u8 rate_offset; - __u8 src_offset; -#endif -#if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS) - struct dentry *dent; /* For visible tree hierarchy */ -#endif -}; - -struct cpufreq_frequency_table; - -struct clk_functions { - int (*clk_enable)(struct clk *clk); - void (*clk_disable)(struct clk *clk); - long (*clk_round_rate)(struct clk *clk, unsigned long rate); - int (*clk_set_rate)(struct clk *clk, unsigned long rate); - int (*clk_set_parent)(struct clk *clk, struct clk *parent); - void (*clk_allow_idle)(struct clk *clk); - void (*clk_deny_idle)(struct clk *clk); - void (*clk_disable_unused)(struct clk *clk); -#ifdef CONFIG_CPU_FREQ - void (*clk_init_cpufreq_table)(struct cpufreq_frequency_table **); -#endif -}; - -extern unsigned int mpurate; - -extern int clk_init(struct clk_functions *custom_clocks); -extern void clk_preinit(struct clk *clk); -extern int clk_register(struct clk *clk); -extern void clk_reparent(struct clk *child, struct clk *parent); -extern void clk_unregister(struct clk *clk); -extern void propagate_rate(struct clk *clk); -extern void recalculate_root_clocks(void); -extern unsigned long followparent_recalc(struct clk *clk); -extern void clk_enable_init_clocks(void); -#ifdef CONFIG_CPU_FREQ -extern void clk_init_cpufreq_table(struct cpufreq_frequency_table **table); -#endif - -extern const struct clkops clkops_null; - -/* Clock flags */ -/* bit 0 is free */ -#define RATE_FIXED (1 << 1) /* Fixed clock rate */ -/* bits 2-4 are free */ -#define ENABLE_REG_32BIT (1 << 5) /* Use 32-bit access */ -#define CLOCK_IDLE_CONTROL (1 << 7) -#define CLOCK_NO_IDLE_PARENT (1 << 8) -#define DELAYED_APP (1 << 9) /* Delay application of clock */ -#define CONFIG_PARTICIPANT (1 << 10) /* Fundamental clock */ -#define ENABLE_ON_INIT (1 << 11) /* Enable upon framework init */ -#define INVERT_ENABLE (1 << 12) /* 0 enables, 1 disables */ -/* bits 13-31 are currently free */ - -/* Clksel_rate flags */ -#define DEFAULT_RATE (1 << 0) -#define RATE_IN_242X (1 << 1) -#define RATE_IN_243X (1 << 2) -#define RATE_IN_343X (1 << 3) /* rates common to all 343X */ -#define RATE_IN_3430ES2 (1 << 4) /* 3430ES2 rates only */ - -#define RATE_IN_24XX (RATE_IN_242X | RATE_IN_243X) - - -#endif diff --git a/arch/arm/plat-omap/include/mach/clockdomain.h b/arch/arm/plat-omap/include/mach/clockdomain.h deleted file mode 100644 index 99ebd886f13..00000000000 --- a/arch/arm/plat-omap/include/mach/clockdomain.h +++ /dev/null @@ -1,111 +0,0 @@ -/* - * arch/arm/plat-omap/include/mach/clockdomain.h - * - * OMAP2/3 clockdomain framework functions - * - * Copyright (C) 2008 Texas Instruments, Inc. - * Copyright (C) 2008 Nokia Corporation - * - * Written by Paul Walmsley - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef __ASM_ARM_ARCH_OMAP_CLOCKDOMAIN_H -#define __ASM_ARM_ARCH_OMAP_CLOCKDOMAIN_H - -#include <mach/powerdomain.h> -#include <mach/clock.h> -#include <mach/cpu.h> - -/* Clockdomain capability flags */ -#define CLKDM_CAN_FORCE_SLEEP (1 << 0) -#define CLKDM_CAN_FORCE_WAKEUP (1 << 1) -#define CLKDM_CAN_ENABLE_AUTO (1 << 2) -#define CLKDM_CAN_DISABLE_AUTO (1 << 3) - -#define CLKDM_CAN_HWSUP (CLKDM_CAN_ENABLE_AUTO | CLKDM_CAN_DISABLE_AUTO) -#define CLKDM_CAN_SWSUP (CLKDM_CAN_FORCE_SLEEP | CLKDM_CAN_FORCE_WAKEUP) -#define CLKDM_CAN_HWSUP_SWSUP (CLKDM_CAN_SWSUP | CLKDM_CAN_HWSUP) - -/* OMAP24XX CM_CLKSTCTRL_*.AUTOSTATE_* register bit values */ -#define OMAP24XX_CLKSTCTRL_DISABLE_AUTO 0x0 -#define OMAP24XX_CLKSTCTRL_ENABLE_AUTO 0x1 - -/* OMAP3XXX CM_CLKSTCTRL_*.CLKTRCTRL_* register bit values */ -#define OMAP34XX_CLKSTCTRL_DISABLE_AUTO 0x0 -#define OMAP34XX_CLKSTCTRL_FORCE_SLEEP 0x1 -#define OMAP34XX_CLKSTCTRL_FORCE_WAKEUP 0x2 -#define OMAP34XX_CLKSTCTRL_ENABLE_AUTO 0x3 - -/* - * struct clkdm_pwrdm_autodep - a powerdomain that should have wkdeps - * and sleepdeps added when a powerdomain should stay active in hwsup mode; - * and conversely, removed when the powerdomain should be allowed to go - * inactive in hwsup mode. - */ -struct clkdm_pwrdm_autodep { - - union { - /* Name of the powerdomain to add a wkdep/sleepdep on */ - const char *name; - - /* Powerdomain pointer (looked up at clkdm_init() time) */ - struct powerdomain *ptr; - } pwrdm; - - /* OMAP chip types that this clockdomain dep is valid on */ - const struct omap_chip_id omap_chip; - -}; - -struct clockdomain { - - /* Clockdomain name */ - const char *name; - - union { - /* Powerdomain enclosing this clockdomain */ - const char *name; - - /* Powerdomain pointer assigned at clkdm_register() */ - struct powerdomain *ptr; - } pwrdm; - - /* CLKTRCTRL/AUTOSTATE field mask in CM_CLKSTCTRL reg */ - const u16 clktrctrl_mask; - - /* Clockdomain capability flags */ - const u8 flags; - - /* OMAP chip types that this clockdomain is valid on */ - const struct omap_chip_id omap_chip; - - /* Usecount tracking */ - atomic_t usecount; - - struct list_head node; - -}; - -void clkdm_init(struct clockdomain **clkdms, struct clkdm_pwrdm_autodep *autodeps); -int clkdm_register(struct clockdomain *clkdm); -int clkdm_unregister(struct clockdomain *clkdm); -struct clockdomain *clkdm_lookup(const char *name); - -int clkdm_for_each(int (*fn)(struct clockdomain *clkdm, void *user), - void *user); -struct powerdomain *clkdm_get_pwrdm(struct clockdomain *clkdm); - -void omap2_clkdm_allow_idle(struct clockdomain *clkdm); -void omap2_clkdm_deny_idle(struct clockdomain *clkdm); - -int omap2_clkdm_wakeup(struct clockdomain *clkdm); -int omap2_clkdm_sleep(struct clockdomain *clkdm); - -int omap2_clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk); -int omap2_clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk); - -#endif diff --git a/arch/arm/plat-omap/include/mach/common.h b/arch/arm/plat-omap/include/mach/common.h deleted file mode 100644 index fdeab421b4d..00000000000 --- a/arch/arm/plat-omap/include/mach/common.h +++ /dev/null @@ -1,71 +0,0 @@ -/* - * arch/arm/plat-omap/include/mach/common.h - * - * Header for code common to all OMAP machines. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -#ifndef __ARCH_ARM_MACH_OMAP_COMMON_H -#define __ARCH_ARM_MACH_OMAP_COMMON_H - -#include <linux/i2c.h> - -struct sys_timer; - -extern void omap_map_common_io(void); -extern struct sys_timer omap_timer; -#if defined(CONFIG_I2C_OMAP) || defined(CONFIG_I2C_OMAP_MODULE) -extern int omap_register_i2c_bus(int bus_id, u32 clkrate, - struct i2c_board_info const *info, - unsigned len); -#else -static inline int omap_register_i2c_bus(int bus_id, u32 clkrate, - struct i2c_board_info const *info, - unsigned len) -{ - return 0; -} -#endif - -/* IO bases for various OMAP processors */ -struct omap_globals { - u32 class; /* OMAP class to detect */ - void __iomem *tap; /* Control module ID code */ - void __iomem *sdrc; /* SDRAM Controller */ - void __iomem *sms; /* SDRAM Memory Scheduler */ - void __iomem *ctrl; /* System Control Module */ - void __iomem *prm; /* Power and Reset Management */ - void __iomem *cm; /* Clock Management */ -}; - -void omap2_set_globals_242x(void); -void omap2_set_globals_243x(void); -void omap2_set_globals_343x(void); -void omap2_set_globals_443x(void); - -/* These get called from omap2_set_globals_xxxx(), do not call these */ -void omap2_set_globals_tap(struct omap_globals *); -void omap2_set_globals_sdrc(struct omap_globals *); -void omap2_set_globals_control(struct omap_globals *); -void omap2_set_globals_prcm(struct omap_globals *); - -#endif /* __ARCH_ARM_MACH_OMAP_COMMON_H */ diff --git a/arch/arm/plat-omap/include/mach/control.h b/arch/arm/plat-omap/include/mach/control.h deleted file mode 100644 index 826d317cdbe..00000000000 --- a/arch/arm/plat-omap/include/mach/control.h +++ /dev/null @@ -1,227 +0,0 @@ -/* - * arch/arm/plat-omap/include/mach/control.h - * - * OMAP2/3/4 System Control Module definitions - * - * Copyright (C) 2007-2009 Texas Instruments, Inc. - * Copyright (C) 2007-2008 Nokia Corporation - * - * Written by Paul Walmsley - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation. - */ - -#ifndef __ASM_ARCH_CONTROL_H -#define __ASM_ARCH_CONTROL_H - -#include <mach/io.h> - -#ifndef __ASSEMBLY__ -#define OMAP242X_CTRL_REGADDR(reg) \ - OMAP2_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg)) -#define OMAP243X_CTRL_REGADDR(reg) \ - OMAP2_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg)) -#define OMAP343X_CTRL_REGADDR(reg) \ - OMAP2_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg)) -#else -#define OMAP242X_CTRL_REGADDR(reg) OMAP2_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg)) -#define OMAP243X_CTRL_REGADDR(reg) OMAP2_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg)) -#define OMAP343X_CTRL_REGADDR(reg) OMAP2_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg)) -#endif /* __ASSEMBLY__ */ - -/* - * As elsewhere, the "OMAP2_" prefix indicates that the macro is valid for - * OMAP24XX and OMAP34XX. - */ - -/* Control submodule offsets */ - -#define OMAP2_CONTROL_INTERFACE 0x000 -#define OMAP2_CONTROL_PADCONFS 0x030 -#define OMAP2_CONTROL_GENERAL 0x270 -#define OMAP343X_CONTROL_MEM_WKUP 0x600 -#define OMAP343X_CONTROL_PADCONFS_WKUP 0xa00 -#define OMAP343X_CONTROL_GENERAL_WKUP 0xa60 - -/* Control register offsets - read/write with omap_ctrl_{read,write}{bwl}() */ - -#define OMAP2_CONTROL_SYSCONFIG (OMAP2_CONTROL_INTERFACE + 0x10) - -/* CONTROL_GENERAL register offsets common to OMAP2 & 3 */ -#define OMAP2_CONTROL_DEVCONF0 (OMAP2_CONTROL_GENERAL + 0x0004) -#define OMAP2_CONTROL_MSUSPENDMUX_0 (OMAP2_CONTROL_GENERAL + 0x0020) -#define OMAP2_CONTROL_MSUSPENDMUX_1 (OMAP2_CONTROL_GENERAL + 0x0024) -#define OMAP2_CONTROL_MSUSPENDMUX_2 (OMAP2_CONTROL_GENERAL + 0x0028) -#define OMAP2_CONTROL_MSUSPENDMUX_3 (OMAP2_CONTROL_GENERAL + 0x002c) -#define OMAP2_CONTROL_MSUSPENDMUX_4 (OMAP2_CONTROL_GENERAL + 0x0030) -#define OMAP2_CONTROL_MSUSPENDMUX_5 (OMAP2_CONTROL_GENERAL + 0x0034) -#define OMAP2_CONTROL_SEC_CTRL (OMAP2_CONTROL_GENERAL + 0x0040) -#define OMAP2_CONTROL_RPUB_KEY_H_0 (OMAP2_CONTROL_GENERAL + 0x0090) -#define OMAP2_CONTROL_RPUB_KEY_H_1 (OMAP2_CONTROL_GENERAL + 0x0094) -#define OMAP2_CONTROL_RPUB_KEY_H_2 (OMAP2_CONTROL_GENERAL + 0x0098) -#define OMAP2_CONTROL_RPUB_KEY_H_3 (OMAP2_CONTROL_GENERAL + 0x009c) - -/* 242x-only CONTROL_GENERAL register offsets */ -#define OMAP242X_CONTROL_DEVCONF OMAP2_CONTROL_DEVCONF0 /* match TRM */ -#define OMAP242X_CONTROL_OCM_RAM_PERM (OMAP2_CONTROL_GENERAL + 0x0068) - -/* 243x-only CONTROL_GENERAL register offsets */ -/* CONTROL_IVA2_BOOT{ADDR,MOD} are at the same place on 343x - noted below */ -#define OMAP243X_CONTROL_DEVCONF1 (OMAP2_CONTROL_GENERAL + 0x0078) -#define OMAP243X_CONTROL_CSIRXFE (OMAP2_CONTROL_GENERAL + 0x007c) -#define OMAP243X_CONTROL_IVA2_BOOTADDR (OMAP2_CONTROL_GENERAL + 0x0190) -#define OMAP243X_CONTROL_IVA2_BOOTMOD (OMAP2_CONTROL_GENERAL + 0x0194) -#define OMAP243X_CONTROL_IVA2_GEMCFG (OMAP2_CONTROL_GENERAL + 0x0198) -#define OMAP243X_CONTROL_PBIAS_LITE (OMAP2_CONTROL_GENERAL + 0x0230) - -/* 24xx-only CONTROL_GENERAL register offsets */ -#define OMAP24XX_CONTROL_DEBOBS (OMAP2_CONTROL_GENERAL + 0x0000) -#define OMAP24XX_CONTROL_EMU_SUPPORT (OMAP2_CONTROL_GENERAL + 0x0008) -#define OMAP24XX_CONTROL_SEC_TEST (OMAP2_CONTROL_GENERAL + 0x0044) -#define OMAP24XX_CONTROL_PSA_CTRL (OMAP2_CONTROL_GENERAL + 0x0048) -#define OMAP24XX_CONTROL_PSA_CMD (OMAP2_CONTROL_GENERAL + 0x004c) -#define OMAP24XX_CONTROL_PSA_VALUE (OMAP2_CONTROL_GENERAL + 0x0050) -#define OMAP24XX_CONTROL_SEC_EMU (OMAP2_CONTROL_GENERAL + 0x0060) -#define OMAP24XX_CONTROL_SEC_TAP (OMAP2_CONTROL_GENERAL + 0x0064) -#define OMAP24XX_CONTROL_OCM_PUB_RAM_ADD (OMAP2_CONTROL_GENERAL + 0x006c) -#define OMAP24XX_CONTROL_EXT_SEC_RAM_START_ADD (OMAP2_CONTROL_GENERAL + 0x0070) -#define OMAP24XX_CONTROL_EXT_SEC_RAM_STOP_ADD (OMAP2_CONTROL_GENERAL + 0x0074) -#define OMAP24XX_CONTROL_SEC_STATUS (OMAP2_CONTROL_GENERAL + 0x0080) -#define OMAP24XX_CONTROL_SEC_ERR_STATUS (OMAP2_CONTROL_GENERAL + 0x0084) -#define OMAP24XX_CONTROL_STATUS (OMAP2_CONTROL_GENERAL + 0x0088) -#define OMAP24XX_CONTROL_GENERAL_PURPOSE_STATUS (OMAP2_CONTROL_GENERAL + 0x008c) -#define OMAP24XX_CONTROL_RAND_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00a0) -#define OMAP24XX_CONTROL_RAND_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00a4) -#define OMAP24XX_CONTROL_RAND_KEY_2 (OMAP2_CONTROL_GENERAL + 0x00a8) -#define OMAP24XX_CONTROL_RAND_KEY_3 (OMAP2_CONTROL_GENERAL + 0x00ac) -#define OMAP24XX_CONTROL_CUST_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00b0) -#define OMAP24XX_CONTROL_CUST_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00b4) -#define OMAP24XX_CONTROL_TEST_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00c0) -#define OMAP24XX_CONTROL_TEST_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00c4) -#define OMAP24XX_CONTROL_TEST_KEY_2 (OMAP2_CONTROL_GENERAL + 0x00c8) -#define OMAP24XX_CONTROL_TEST_KEY_3 (OMAP2_CONTROL_GENERAL + 0x00cc) -#define OMAP24XX_CONTROL_TEST_KEY_4 (OMAP2_CONTROL_GENERAL + 0x00d0) -#define OMAP24XX_CONTROL_TEST_KEY_5 (OMAP2_CONTROL_GENERAL + 0x00d4) -#define OMAP24XX_CONTROL_TEST_KEY_6 (OMAP2_CONTROL_GENERAL + 0x00d8) -#define OMAP24XX_CONTROL_TEST_KEY_7 (OMAP2_CONTROL_GENERAL + 0x00dc) -#define OMAP24XX_CONTROL_TEST_KEY_8 (OMAP2_CONTROL_GENERAL + 0x00e0) -#define OMAP24XX_CONTROL_TEST_KEY_9 (OMAP2_CONTROL_GENERAL + 0x00e4) - -/* 34xx-only CONTROL_GENERAL register offsets */ -#define OMAP343X_CONTROL_PADCONF_OFF (OMAP2_CONTROL_GENERAL + 0x0000) -#define OMAP343X_CONTROL_MEM_DFTRW0 (OMAP2_CONTROL_GENERAL + 0x0008) -#define OMAP343X_CONTROL_MEM_DFTRW1 (OMAP2_CONTROL_GENERAL + 0x000c) -#define OMAP343X_CONTROL_DEVCONF1 (OMAP2_CONTROL_GENERAL + 0x0068) -#define OMAP343X_CONTROL_CSIRXFE (OMAP2_CONTROL_GENERAL + 0x006c) -#define OMAP343X_CONTROL_SEC_STATUS (OMAP2_CONTROL_GENERAL + 0x0070) -#define OMAP343X_CONTROL_SEC_ERR_STATUS (OMAP2_CONTROL_GENERAL + 0x0074) -#define OMAP343X_CONTROL_SEC_ERR_STATUS_DEBUG (OMAP2_CONTROL_GENERAL + 0x0078) -#define OMAP343X_CONTROL_STATUS (OMAP2_CONTROL_GENERAL + 0x0080) -#define OMAP343X_CONTROL_GENERAL_PURPOSE_STATUS (OMAP2_CONTROL_GENERAL + 0x0084) -#define OMAP343X_CONTROL_RPUB_KEY_H_4 (OMAP2_CONTROL_GENERAL + 0x00a0) -#define OMAP343X_CONTROL_RAND_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00a8) -#define OMAP343X_CONTROL_RAND_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00ac) -#define OMAP343X_CONTROL_RAND_KEY_2 (OMAP2_CONTROL_GENERAL + 0x00b0) -#define OMAP343X_CONTROL_RAND_KEY_3 (OMAP2_CONTROL_GENERAL + 0x00b4) -#define OMAP343X_CONTROL_TEST_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00c8) -#define OMAP343X_CONTROL_TEST_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00cc) -#define OMAP343X_CONTROL_TEST_KEY_2 (OMAP2_CONTROL_GENERAL + 0x00d0) -#define OMAP343X_CONTROL_TEST_KEY_3 (OMAP2_CONTROL_GENERAL + 0x00d4) -#define OMAP343X_CONTROL_TEST_KEY_4 (OMAP2_CONTROL_GENERAL + 0x00d8) -#define OMAP343X_CONTROL_TEST_KEY_5 (OMAP2_CONTROL_GENERAL + 0x00dc) -#define OMAP343X_CONTROL_TEST_KEY_6 (OMAP2_CONTROL_GENERAL + 0x00e0) -#define OMAP343X_CONTROL_TEST_KEY_7 (OMAP2_CONTROL_GENERAL + 0x00e4) -#define OMAP343X_CONTROL_TEST_KEY_8 (OMAP2_CONTROL_GENERAL + 0x00e8) -#define OMAP343X_CONTROL_TEST_KEY_9 (OMAP2_CONTROL_GENERAL + 0x00ec) -#define OMAP343X_CONTROL_TEST_KEY_10 (OMAP2_CONTROL_GENERAL + 0x00f0) -#define OMAP343X_CONTROL_TEST_KEY_11 (OMAP2_CONTROL_GENERAL + 0x00f4) -#define OMAP343X_CONTROL_TEST_KEY_12 (OMAP2_CONTROL_GENERAL + 0x00f8) -#define OMAP343X_CONTROL_TEST_KEY_13 (OMAP2_CONTROL_GENERAL + 0x00fc) -#define OMAP343X_CONTROL_IVA2_BOOTADDR (OMAP2_CONTROL_GENERAL + 0x0190) -#define OMAP343X_CONTROL_IVA2_BOOTMOD (OMAP2_CONTROL_GENERAL + 0x0194) -#define OMAP343X_CONTROL_PBIAS_LITE (OMAP2_CONTROL_GENERAL + 0x02b0) -#define OMAP343X_CONTROL_TEMP_SENSOR (OMAP2_CONTROL_GENERAL + 0x02b4) - -/* 34xx D2D idle-related pins, handled by PM core */ -#define OMAP3_PADCONF_SAD2D_MSTANDBY 0x250 -#define OMAP3_PADCONF_SAD2D_IDLEACK 0x254 - -/* - * REVISIT: This list of registers is not comprehensive - there are more - * that should be added. - */ - -/* - * Control module register bit defines - these should eventually go into - * their own regbits file. Some of these will be complicated, depending - * on the device type (general-purpose, emulator, test, secure, bad, other) - * and the security mode (secure, non-secure, don't care) - */ -/* CONTROL_DEVCONF0 bits */ -#define OMAP2_MMCSDIO1ADPCLKISEL (1 << 24) /* MMC1 loop back clock */ -#define OMAP24XX_USBSTANDBYCTRL (1 << 15) -#define OMAP2_MCBSP2_CLKS_MASK (1 << 6) -#define OMAP2_MCBSP1_CLKS_MASK (1 << 2) - -/* CONTROL_DEVCONF1 bits */ -#define OMAP243X_MMC1_ACTIVE_OVERWRITE (1 << 31) -#define OMAP2_MMCSDIO2ADPCLKISEL (1 << 6) /* MMC2 loop back clock */ -#define OMAP2_MCBSP5_CLKS_MASK (1 << 4) /* > 242x */ -#define OMAP2_MCBSP4_CLKS_MASK (1 << 2) /* > 242x */ -#define OMAP2_MCBSP3_CLKS_MASK (1 << 0) /* > 242x */ - -/* CONTROL_STATUS bits */ -#define OMAP2_DEVICETYPE_MASK (0x7 << 8) -#define OMAP2_SYSBOOT_5_MASK (1 << 5) -#define OMAP2_SYSBOOT_4_MASK (1 << 4) -#define OMAP2_SYSBOOT_3_MASK (1 << 3) -#define OMAP2_SYSBOOT_2_MASK (1 << 2) -#define OMAP2_SYSBOOT_1_MASK (1 << 1) -#define OMAP2_SYSBOOT_0_MASK (1 << 0) - -/* CONTROL_PBIAS_LITE bits */ -#define OMAP343X_PBIASLITESUPPLY_HIGH1 (1 << 15) -#define OMAP343X_PBIASLITEVMODEERROR1 (1 << 11) -#define OMAP343X_PBIASSPEEDCTRL1 (1 << 10) -#define OMAP343X_PBIASLITEPWRDNZ1 (1 << 9) -#define OMAP343X_PBIASLITEVMODE1 (1 << 8) -#define OMAP343X_PBIASLITESUPPLY_HIGH0 (1 << 7) -#define OMAP343X_PBIASLITEVMODEERROR0 (1 << 3) -#define OMAP2_PBIASSPEEDCTRL0 (1 << 2) -#define OMAP2_PBIASLITEPWRDNZ0 (1 << 1) -#define OMAP2_PBIASLITEVMODE0 (1 << 0) - -/* CONTROL_IVA2_BOOTMOD bits */ -#define OMAP3_IVA2_BOOTMOD_SHIFT 0 -#define OMAP3_IVA2_BOOTMOD_MASK (0xf << 0) -#define OMAP3_IVA2_BOOTMOD_IDLE (0x1 << 0) - -/* CONTROL_PADCONF_X bits */ -#define OMAP3_PADCONF_WAKEUPEVENT0 (1 << 15) -#define OMAP3_PADCONF_WAKEUPENABLE0 (1 << 14) - -#ifndef __ASSEMBLY__ -#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \ - defined(CONFIG_ARCH_OMAP4) -extern void __iomem *omap_ctrl_base_get(void); -extern u8 omap_ctrl_readb(u16 offset); -extern u16 omap_ctrl_readw(u16 offset); -extern u32 omap_ctrl_readl(u16 offset); -extern void omap_ctrl_writeb(u8 val, u16 offset); -extern void omap_ctrl_writew(u16 val, u16 offset); -extern void omap_ctrl_writel(u32 val, u16 offset); -#else -#define omap_ctrl_base_get() 0 -#define omap_ctrl_readb(x) 0 -#define omap_ctrl_readw(x) 0 -#define omap_ctrl_readl(x) 0 -#define omap_ctrl_writeb(x, y) WARN_ON(1) -#define omap_ctrl_writew(x, y) WARN_ON(1) -#define omap_ctrl_writel(x, y) WARN_ON(1) -#endif -#endif /* __ASSEMBLY__ */ - -#endif /* __ASM_ARCH_CONTROL_H */ - diff --git a/arch/arm/plat-omap/include/mach/cpu.h b/arch/arm/plat-omap/include/mach/cpu.h deleted file mode 100644 index f129efb3075..00000000000 --- a/arch/arm/plat-omap/include/mach/cpu.h +++ /dev/null @@ -1,426 +0,0 @@ -/* - * arch/arm/plat-omap/include/mach/cpu.h - * - * OMAP cpu type detection - * - * Copyright (C) 2004, 2008 Nokia Corporation - * - * Copyright (C) 2009 Texas Instruments. - * - * Written by Tony Lindgren <tony.lindgren@nokia.com> - * - * Added OMAP4 specific defines - Santosh Shilimkar<santosh.shilimkar@ti.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - * - */ - -#ifndef __ASM_ARCH_OMAP_CPU_H -#define __ASM_ARCH_OMAP_CPU_H - -/* - * Omap device type i.e. EMU/HS/TST/GP/BAD - */ -#define OMAP2_DEVICE_TYPE_TEST 0 -#define OMAP2_DEVICE_TYPE_EMU 1 -#define OMAP2_DEVICE_TYPE_SEC 2 -#define OMAP2_DEVICE_TYPE_GP 3 -#define OMAP2_DEVICE_TYPE_BAD 4 - -int omap_type(void); - -struct omap_chip_id { - u8 oc; - u8 type; -}; - -#define OMAP_CHIP_INIT(x) { .oc = x } - -/* - * omap_rev bits: - * CPU id bits (0730, 1510, 1710, 2422...) [31:16] - * CPU revision (See _REV_ defined in cpu.h) [15:08] - * CPU class bits (15xx, 16xx, 24xx, 34xx...) [07:00] - */ -unsigned int omap_rev(void); - -/* - * Test if multicore OMAP support is needed - */ -#undef MULTI_OMAP1 -#undef MULTI_OMAP2 -#undef OMAP_NAME - -#ifdef CONFIG_ARCH_OMAP730 -# ifdef OMAP_NAME -# undef MULTI_OMAP1 -# define MULTI_OMAP1 -# else -# define OMAP_NAME omap730 -# endif -#endif -#ifdef CONFIG_ARCH_OMAP850 -# ifdef OMAP_NAME -# undef MULTI_OMAP1 -# define MULTI_OMAP1 -# else -# define OMAP_NAME omap850 -# endif -#endif -#ifdef CONFIG_ARCH_OMAP15XX -# ifdef OMAP_NAME -# undef MULTI_OMAP1 -# define MULTI_OMAP1 -# else -# define OMAP_NAME omap1510 -# endif -#endif -#ifdef CONFIG_ARCH_OMAP16XX -# ifdef OMAP_NAME -# undef MULTI_OMAP1 -# define MULTI_OMAP1 -# else -# define OMAP_NAME omap16xx -# endif -#endif -#if (defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)) -# if (defined(OMAP_NAME) || defined(MULTI_OMAP1)) -# error "OMAP1 and OMAP2 can't be selected at the same time" -# endif -#endif -#ifdef CONFIG_ARCH_OMAP2420 -# ifdef OMAP_NAME -# undef MULTI_OMAP2 -# define MULTI_OMAP2 -# else -# define OMAP_NAME omap2420 -# endif -#endif -#ifdef CONFIG_ARCH_OMAP2430 -# ifdef OMAP_NAME -# undef MULTI_OMAP2 -# define MULTI_OMAP2 -# else -# define OMAP_NAME omap2430 -# endif -#endif -#ifdef CONFIG_ARCH_OMAP3430 -# ifdef OMAP_NAME -# undef MULTI_OMAP2 -# define MULTI_OMAP2 -# else -# define OMAP_NAME omap3430 -# endif -#endif - -/* - * Macros to group OMAP into cpu classes. - * These can be used in most places. - * cpu_is_omap7xx(): True for OMAP730, OMAP850 - * cpu_is_omap15xx(): True for OMAP1510, OMAP5910 and OMAP310 - * cpu_is_omap16xx(): True for OMAP1610, OMAP5912 and OMAP1710 - * cpu_is_omap24xx(): True for OMAP2420, OMAP2422, OMAP2423, OMAP2430 - * cpu_is_omap242x(): True for OMAP2420, OMAP2422, OMAP2423 - * cpu_is_omap243x(): True for OMAP2430 - * cpu_is_omap343x(): True for OMAP3430 - */ -#define GET_OMAP_CLASS (omap_rev() & 0xff) - -#define IS_OMAP_CLASS(class, id) \ -static inline int is_omap ##class (void) \ -{ \ - return (GET_OMAP_CLASS == (id)) ? 1 : 0; \ -} - -#define GET_OMAP_SUBCLASS ((omap_rev() >> 20) & 0x0fff) - -#define IS_OMAP_SUBCLASS(subclass, id) \ -static inline int is_omap ##subclass (void) \ -{ \ - return (GET_OMAP_SUBCLASS == (id)) ? 1 : 0; \ -} - -IS_OMAP_CLASS(7xx, 0x07) -IS_OMAP_CLASS(15xx, 0x15) -IS_OMAP_CLASS(16xx, 0x16) -IS_OMAP_CLASS(24xx, 0x24) -IS_OMAP_CLASS(34xx, 0x34) - -IS_OMAP_SUBCLASS(242x, 0x242) -IS_OMAP_SUBCLASS(243x, 0x243) -IS_OMAP_SUBCLASS(343x, 0x343) - -#define cpu_is_omap7xx() 0 -#define cpu_is_omap15xx() 0 -#define cpu_is_omap16xx() 0 -#define cpu_is_omap24xx() 0 -#define cpu_is_omap242x() 0 -#define cpu_is_omap243x() 0 -#define cpu_is_omap34xx() 0 -#define cpu_is_omap343x() 0 -#define cpu_is_omap44xx() 0 -#define cpu_is_omap443x() 0 - -#if defined(MULTI_OMAP1) -# if defined(CONFIG_ARCH_OMAP730) -# undef cpu_is_omap7xx -# define cpu_is_omap7xx() is_omap7xx() -# endif -# if defined(CONFIG_ARCH_OMAP850) -# undef cpu_is_omap7xx -# define cpu_is_omap7xx() is_omap7xx() -# endif -# if defined(CONFIG_ARCH_OMAP15XX) -# undef cpu_is_omap15xx -# define cpu_is_omap15xx() is_omap15xx() -# endif -# if defined(CONFIG_ARCH_OMAP16XX) -# undef cpu_is_omap16xx -# define cpu_is_omap16xx() is_omap16xx() -# endif -#else -# if defined(CONFIG_ARCH_OMAP730) -# undef cpu_is_omap7xx -# define cpu_is_omap7xx() 1 -# endif -# if defined(CONFIG_ARCH_OMAP850) -# undef cpu_is_omap7xx -# define cpu_is_omap7xx() 1 -# endif -# if defined(CONFIG_ARCH_OMAP15XX) -# undef cpu_is_omap15xx -# define cpu_is_omap15xx() 1 -# endif -# if defined(CONFIG_ARCH_OMAP16XX) -# undef cpu_is_omap16xx -# define cpu_is_omap16xx() 1 -# endif -#endif - -#if defined(MULTI_OMAP2) -# if defined(CONFIG_ARCH_OMAP24XX) -# undef cpu_is_omap24xx -# undef cpu_is_omap242x -# undef cpu_is_omap243x -# define cpu_is_omap24xx() is_omap24xx() -# define cpu_is_omap242x() is_omap242x() -# define cpu_is_omap243x() is_omap243x() -# endif -# if defined(CONFIG_ARCH_OMAP34XX) -# undef cpu_is_omap34xx -# undef cpu_is_omap343x -# define cpu_is_omap34xx() is_omap34xx() -# define cpu_is_omap343x() is_omap343x() -# endif -#else -# if defined(CONFIG_ARCH_OMAP24XX) -# undef cpu_is_omap24xx -# define cpu_is_omap24xx() 1 -# endif -# if defined(CONFIG_ARCH_OMAP2420) -# undef cpu_is_omap242x -# define cpu_is_omap242x() 1 -# endif -# if defined(CONFIG_ARCH_OMAP2430) -# undef cpu_is_omap243x -# define cpu_is_omap243x() 1 -# endif -# if defined(CONFIG_ARCH_OMAP34XX) -# undef cpu_is_omap34xx -# define cpu_is_omap34xx() 1 -# endif -# if defined(CONFIG_ARCH_OMAP3430) -# undef cpu_is_omap343x -# define cpu_is_omap343x() 1 -# endif -#endif - -/* - * Macros to detect individual cpu types. - * These are only rarely needed. - * cpu_is_omap330(): True for OMAP330 - * cpu_is_omap730(): True for OMAP730 - * cpu_is_omap850(): True for OMAP850 - * cpu_is_omap1510(): True for OMAP1510 - * cpu_is_omap1610(): True for OMAP1610 - * cpu_is_omap1611(): True for OMAP1611 - * cpu_is_omap5912(): True for OMAP5912 - * cpu_is_omap1621(): True for OMAP1621 - * cpu_is_omap1710(): True for OMAP1710 - * cpu_is_omap2420(): True for OMAP2420 - * cpu_is_omap2422(): True for OMAP2422 - * cpu_is_omap2423(): True for OMAP2423 - * cpu_is_omap2430(): True for OMAP2430 - * cpu_is_omap3430(): True for OMAP3430 - */ -#define GET_OMAP_TYPE ((omap_rev() >> 16) & 0xffff) - -#define IS_OMAP_TYPE(type, id) \ -static inline int is_omap ##type (void) \ -{ \ - return (GET_OMAP_TYPE == (id)) ? 1 : 0; \ -} - -IS_OMAP_TYPE(310, 0x0310) -IS_OMAP_TYPE(730, 0x0730) -IS_OMAP_TYPE(850, 0x0850) -IS_OMAP_TYPE(1510, 0x1510) -IS_OMAP_TYPE(1610, 0x1610) -IS_OMAP_TYPE(1611, 0x1611) -IS_OMAP_TYPE(5912, 0x1611) -IS_OMAP_TYPE(1621, 0x1621) -IS_OMAP_TYPE(1710, 0x1710) -IS_OMAP_TYPE(2420, 0x2420) -IS_OMAP_TYPE(2422, 0x2422) -IS_OMAP_TYPE(2423, 0x2423) -IS_OMAP_TYPE(2430, 0x2430) -IS_OMAP_TYPE(3430, 0x3430) - -#define cpu_is_omap310() 0 -#define cpu_is_omap730() 0 -#define cpu_is_omap850() 0 -#define cpu_is_omap1510() 0 -#define cpu_is_omap1610() 0 -#define cpu_is_omap5912() 0 -#define cpu_is_omap1611() 0 -#define cpu_is_omap1621() 0 -#define cpu_is_omap1710() 0 -#define cpu_is_omap2420() 0 -#define cpu_is_omap2422() 0 -#define cpu_is_omap2423() 0 -#define cpu_is_omap2430() 0 -#define cpu_is_omap3430() 0 - -/* - * Whether we have MULTI_OMAP1 or not, we still need to distinguish - * between 730 vs 850, 330 vs. 1510 and 1611B/5912 vs. 1710. - */ - -#if defined(CONFIG_ARCH_OMAP730) -# undef cpu_is_omap730 -# define cpu_is_omap730() is_omap730() -#endif - -#if defined(CONFIG_ARCH_OMAP850) -# undef cpu_is_omap850 -# define cpu_is_omap850() is_omap850() -#endif - -#if defined(CONFIG_ARCH_OMAP15XX) -# undef cpu_is_omap310 -# undef cpu_is_omap1510 -# define cpu_is_omap310() is_omap310() -# define cpu_is_omap1510() is_omap1510() -#endif - -#if defined(CONFIG_ARCH_OMAP16XX) -# undef cpu_is_omap1610 -# undef cpu_is_omap1611 -# undef cpu_is_omap5912 -# undef cpu_is_omap1621 -# undef cpu_is_omap1710 -# define cpu_is_omap1610() is_omap1610() -# define cpu_is_omap1611() is_omap1611() -# define cpu_is_omap5912() is_omap5912() -# define cpu_is_omap1621() is_omap1621() -# define cpu_is_omap1710() is_omap1710() -#endif - -#if defined(CONFIG_ARCH_OMAP24XX) -# undef cpu_is_omap2420 -# undef cpu_is_omap2422 -# undef cpu_is_omap2423 -# undef cpu_is_omap2430 -# define cpu_is_omap2420() is_omap2420() -# define cpu_is_omap2422() is_omap2422() -# define cpu_is_omap2423() is_omap2423() -# define cpu_is_omap2430() is_omap2430() -#endif - -#if defined(CONFIG_ARCH_OMAP34XX) -# undef cpu_is_omap3430 -# define cpu_is_omap3430() is_omap3430() -#endif - -# if defined(CONFIG_ARCH_OMAP4) -# undef cpu_is_omap44xx -# undef cpu_is_omap443x -# define cpu_is_omap44xx() 1 -# define cpu_is_omap443x() 1 -# endif - -/* Macros to detect if we have OMAP1 or OMAP2 */ -#define cpu_class_is_omap1() (cpu_is_omap7xx() || cpu_is_omap15xx() || \ - cpu_is_omap16xx()) -#define cpu_class_is_omap2() (cpu_is_omap24xx() || cpu_is_omap34xx() || \ - cpu_is_omap44xx()) - -/* Various silicon revisions for omap2 */ -#define OMAP242X_CLASS 0x24200024 -#define OMAP2420_REV_ES1_0 0x24200024 -#define OMAP2420_REV_ES2_0 0x24201024 - -#define OMAP243X_CLASS 0x24300024 -#define OMAP2430_REV_ES1_0 0x24300024 - -#define OMAP343X_CLASS 0x34300034 -#define OMAP3430_REV_ES1_0 0x34300034 -#define OMAP3430_REV_ES2_0 0x34301034 -#define OMAP3430_REV_ES2_1 0x34302034 -#define OMAP3430_REV_ES3_0 0x34303034 -#define OMAP3430_REV_ES3_1 0x34304034 - -#define OMAP443X_CLASS 0x44300034 - -/* - * omap_chip bits - * - * CHIP_IS_OMAP{2420,2430,3430} indicate that a particular structure is - * valid on all chips of that type. CHIP_IS_OMAP3430ES{1,2} indicates - * something that is only valid on that particular ES revision. - * - * These bits may be ORed together to indicate structures that are - * available on multiple chip types. - * - * To test whether a particular structure matches the current OMAP chip type, - * use omap_chip_is(). - * - */ -#define CHIP_IS_OMAP2420 (1 << 0) -#define CHIP_IS_OMAP2430 (1 << 1) -#define CHIP_IS_OMAP3430 (1 << 2) -#define CHIP_IS_OMAP3430ES1 (1 << 3) -#define CHIP_IS_OMAP3430ES2 (1 << 4) -#define CHIP_IS_OMAP3430ES3_0 (1 << 5) -#define CHIP_IS_OMAP3430ES3_1 (1 << 6) - -#define CHIP_IS_OMAP24XX (CHIP_IS_OMAP2420 | CHIP_IS_OMAP2430) - -/* - * "GE" here represents "greater than or equal to" in terms of ES - * levels. So CHIP_GE_OMAP3430ES2 is intended to match all OMAP3430 - * chips at ES2 and beyond, but not, for example, any OMAP lines after - * OMAP3. - */ -#define CHIP_GE_OMAP3430ES2 (CHIP_IS_OMAP3430ES2 | \ - CHIP_IS_OMAP3430ES3_0 | \ - CHIP_IS_OMAP3430ES3_1) -#define CHIP_GE_OMAP3430ES3_1 (CHIP_IS_OMAP3430ES3_1) - - -int omap_chip_is(struct omap_chip_id oci); -void omap2_check_revision(void); - -#endif diff --git a/arch/arm/plat-omap/include/mach/debug-macro.S b/arch/arm/plat-omap/include/mach/debug-macro.S deleted file mode 100644 index ac24050e341..00000000000 --- a/arch/arm/plat-omap/include/mach/debug-macro.S +++ /dev/null @@ -1,70 +0,0 @@ -/* arch/arm/plat-omap/include/mach/debug-macro.S - * - * Debugging macro include header - * - * Copyright (C) 1994-1999 Russell King - * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * -*/ - - .macro addruart,rx - mrc p15, 0, \rx, c1, c0 - tst \rx, #1 @ MMU enabled? -#ifdef CONFIG_ARCH_OMAP1 - moveq \rx, #0xff000000 @ physical base address - movne \rx, #0xfe000000 @ virtual base - orr \rx, \rx, #0x00fb0000 -#ifdef CONFIG_OMAP_LL_DEBUG_UART3 - orr \rx, \rx, #0x00009000 @ UART 3 -#endif -#if defined(CONFIG_OMAP_LL_DEBUG_UART2) || defined(CONFIG_OMAP_LL_DEBUG_UART3) - orr \rx, \rx, #0x00000800 @ UART 2 & 3 -#endif - -#elif CONFIG_ARCH_OMAP2 - moveq \rx, #0x48000000 @ physical base address - movne \rx, #0xd8000000 @ virtual base - orr \rx, \rx, #0x0006a000 -#ifdef CONFIG_OMAP_LL_DEBUG_UART2 - add \rx, \rx, #0x00002000 @ UART 2 -#endif -#ifdef CONFIG_OMAP_LL_DEBUG_UART3 - add \rx, \rx, #0x00004000 @ UART 3 -#endif - -#elif defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) - moveq \rx, #0x48000000 @ physical base address - movne \rx, #0xd8000000 @ virtual base - orr \rx, \rx, #0x0006a000 -#ifdef CONFIG_OMAP_LL_DEBUG_UART2 - add \rx, \rx, #0x00002000 @ UART 2 -#endif -#ifdef CONFIG_OMAP_LL_DEBUG_UART3 - add \rx, \rx, #0x00fb0000 @ UART 3 - add \rx, \rx, #0x00006000 -#endif -#endif - .endm - - .macro senduart,rd,rx - strb \rd, [\rx] - .endm - - .macro busyuart,rd,rx -1001: ldrb \rd, [\rx, #(0x5 << 2)] @ OMAP-1510 and friends - and \rd, \rd, #0x60 - teq \rd, #0x60 - beq 1002f - ldrb \rd, [\rx, #(0x5 << 0)] @ OMAP-730 only - and \rd, \rd, #0x60 - teq \rd, #0x60 - bne 1001b -1002: - .endm - - .macro waituart,rd,rx - .endm diff --git a/arch/arm/plat-omap/include/mach/dma.h b/arch/arm/plat-omap/include/mach/dma.h deleted file mode 100644 index 72f680b7180..00000000000 --- a/arch/arm/plat-omap/include/mach/dma.h +++ /dev/null @@ -1,675 +0,0 @@ -/* - * arch/arm/plat-omap/include/mach/dma.h - * - * Copyright (C) 2003 Nokia Corporation - * Author: Juha Yrjölä <juha.yrjola@nokia.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#ifndef __ASM_ARCH_DMA_H -#define __ASM_ARCH_DMA_H - -/* Hardware registers for omap1 */ -#define OMAP1_DMA_BASE (0xfffed800) - -#define OMAP1_DMA_GCR 0x400 -#define OMAP1_DMA_GSCR 0x404 -#define OMAP1_DMA_GRST 0x408 -#define OMAP1_DMA_HW_ID 0x442 -#define OMAP1_DMA_PCH2_ID 0x444 -#define OMAP1_DMA_PCH0_ID 0x446 -#define OMAP1_DMA_PCH1_ID 0x448 -#define OMAP1_DMA_PCHG_ID 0x44a -#define OMAP1_DMA_PCHD_ID 0x44c -#define OMAP1_DMA_CAPS_0_U 0x44e -#define OMAP1_DMA_CAPS_0_L 0x450 -#define OMAP1_DMA_CAPS_1_U 0x452 -#define OMAP1_DMA_CAPS_1_L 0x454 -#define OMAP1_DMA_CAPS_2 0x456 -#define OMAP1_DMA_CAPS_3 0x458 -#define OMAP1_DMA_CAPS_4 0x45a -#define OMAP1_DMA_PCH2_SR 0x460 -#define OMAP1_DMA_PCH0_SR 0x480 -#define OMAP1_DMA_PCH1_SR 0x482 -#define OMAP1_DMA_PCHD_SR 0x4c0 - -/* Hardware registers for omap2 and omap3 */ -#define OMAP24XX_DMA4_BASE (L4_24XX_BASE + 0x56000) -#define OMAP34XX_DMA4_BASE (L4_34XX_BASE + 0x56000) -#define OMAP44XX_DMA4_BASE (L4_44XX_BASE + 0x56000) - -#define OMAP_DMA4_REVISION 0x00 -#define OMAP_DMA4_GCR 0x78 -#define OMAP_DMA4_IRQSTATUS_L0 0x08 -#define OMAP_DMA4_IRQSTATUS_L1 0x0c -#define OMAP_DMA4_IRQSTATUS_L2 0x10 -#define OMAP_DMA4_IRQSTATUS_L3 0x14 -#define OMAP_DMA4_IRQENABLE_L0 0x18 -#define OMAP_DMA4_IRQENABLE_L1 0x1c -#define OMAP_DMA4_IRQENABLE_L2 0x20 -#define OMAP_DMA4_IRQENABLE_L3 0x24 -#define OMAP_DMA4_SYSSTATUS 0x28 -#define OMAP_DMA4_OCP_SYSCONFIG 0x2c -#define OMAP_DMA4_CAPS_0 0x64 -#define OMAP_DMA4_CAPS_2 0x6c -#define OMAP_DMA4_CAPS_3 0x70 -#define OMAP_DMA4_CAPS_4 0x74 - -#define OMAP1_LOGICAL_DMA_CH_COUNT 17 -#define OMAP_DMA4_LOGICAL_DMA_CH_COUNT 32 /* REVISIT: Is this 32 + 2? */ - -/* Common channel specific registers for omap1 */ -#define OMAP1_DMA_CH_BASE(n) (0x40 * (n) + 0x00) -#define OMAP1_DMA_CSDP(n) (0x40 * (n) + 0x00) -#define OMAP1_DMA_CCR(n) (0x40 * (n) + 0x02) -#define OMAP1_DMA_CICR(n) (0x40 * (n) + 0x04) -#define OMAP1_DMA_CSR(n) (0x40 * (n) + 0x06) -#define OMAP1_DMA_CEN(n) (0x40 * (n) + 0x10) -#define OMAP1_DMA_CFN(n) (0x40 * (n) + 0x12) -#define OMAP1_DMA_CSFI(n) (0x40 * (n) + 0x14) -#define OMAP1_DMA_CSEI(n) (0x40 * (n) + 0x16) -#define OMAP1_DMA_CPC(n) (0x40 * (n) + 0x18) /* 15xx only */ -#define OMAP1_DMA_CSAC(n) (0x40 * (n) + 0x18) -#define OMAP1_DMA_CDAC(n) (0x40 * (n) + 0x1a) -#define OMAP1_DMA_CDEI(n) (0x40 * (n) + 0x1c) -#define OMAP1_DMA_CDFI(n) (0x40 * (n) + 0x1e) -#define OMAP1_DMA_CLNK_CTRL(n) (0x40 * (n) + 0x28) - -/* Common channel specific registers for omap2 */ -#define OMAP_DMA4_CH_BASE(n) (0x60 * (n) + 0x80) -#define OMAP_DMA4_CCR(n) (0x60 * (n) + 0x80) -#define OMAP_DMA4_CLNK_CTRL(n) (0x60 * (n) + 0x84) -#define OMAP_DMA4_CICR(n) (0x60 * (n) + 0x88) -#define OMAP_DMA4_CSR(n) (0x60 * (n) + 0x8c) -#define OMAP_DMA4_CSDP(n) (0x60 * (n) + 0x90) -#define OMAP_DMA4_CEN(n) (0x60 * (n) + 0x94) -#define OMAP_DMA4_CFN(n) (0x60 * (n) + 0x98) -#define OMAP_DMA4_CSEI(n) (0x60 * (n) + 0xa4) -#define OMAP_DMA4_CSFI(n) (0x60 * (n) + 0xa8) -#define OMAP_DMA4_CDEI(n) (0x60 * (n) + 0xac) -#define OMAP_DMA4_CDFI(n) (0x60 * (n) + 0xb0) -#define OMAP_DMA4_CSAC(n) (0x60 * (n) + 0xb4) -#define OMAP_DMA4_CDAC(n) (0x60 * (n) + 0xb8) - -/* Channel specific registers only on omap1 */ -#define OMAP1_DMA_CSSA_L(n) (0x40 * (n) + 0x08) -#define OMAP1_DMA_CSSA_U(n) (0x40 * (n) + 0x0a) -#define OMAP1_DMA_CDSA_L(n) (0x40 * (n) + 0x0c) -#define OMAP1_DMA_CDSA_U(n) (0x40 * (n) + 0x0e) -#define OMAP1_DMA_COLOR_L(n) (0x40 * (n) + 0x20) -#define OMAP1_DMA_COLOR_U(n) (0x40 * (n) + 0x22) -#define OMAP1_DMA_CCR2(n) (0x40 * (n) + 0x24) -#define OMAP1_DMA_LCH_CTRL(n) (0x40 * (n) + 0x2a) /* not on 15xx */ -#define OMAP1_DMA_CCEN(n) 0 -#define OMAP1_DMA_CCFN(n) 0 - -/* Channel specific registers only on omap2 */ -#define OMAP_DMA4_CSSA(n) (0x60 * (n) + 0x9c) -#define OMAP_DMA4_CDSA(n) (0x60 * (n) + 0xa0) -#define OMAP_DMA4_CCEN(n) (0x60 * (n) + 0xbc) -#define OMAP_DMA4_CCFN(n) (0x60 * (n) + 0xc0) -#define OMAP_DMA4_COLOR(n) (0x60 * (n) + 0xc4) - -/* Additional registers available on OMAP4 */ -#define OMAP_DMA4_CDP(n) (0x60 * (n) + 0xd0) -#define OMAP_DMA4_CNDP(n) (0x60 * (n) + 0xd4) -#define OMAP_DMA4_CCDN(n) (0x60 * (n) + 0xd8) - -/* Dummy defines to keep multi-omap compiles happy */ -#define OMAP1_DMA_REVISION 0 -#define OMAP1_DMA_IRQSTATUS_L0 0 -#define OMAP1_DMA_IRQENABLE_L0 0 -#define OMAP1_DMA_OCP_SYSCONFIG 0 -#define OMAP_DMA4_HW_ID 0 -#define OMAP_DMA4_CAPS_0_L 0 -#define OMAP_DMA4_CAPS_0_U 0 -#define OMAP_DMA4_CAPS_1_L 0 -#define OMAP_DMA4_CAPS_1_U 0 -#define OMAP_DMA4_GSCR 0 -#define OMAP_DMA4_CPC(n) 0 - -#define OMAP_DMA4_LCH_CTRL(n) 0 -#define OMAP_DMA4_COLOR_L(n) 0 -#define OMAP_DMA4_COLOR_U(n) 0 -#define OMAP_DMA4_CCR2(n) 0 -#define OMAP1_DMA_CSSA(n) 0 -#define OMAP1_DMA_CDSA(n) 0 -#define OMAP_DMA4_CSSA_L(n) 0 -#define OMAP_DMA4_CSSA_U(n) 0 -#define OMAP_DMA4_CDSA_L(n) 0 -#define OMAP_DMA4_CDSA_U(n) 0 -#define OMAP1_DMA_COLOR(n) 0 - -/*----------------------------------------------------------------------------*/ - -/* DMA channels for omap1 */ -#define OMAP_DMA_NO_DEVICE 0 -#define OMAP_DMA_MCSI1_TX 1 -#define OMAP_DMA_MCSI1_RX 2 -#define OMAP_DMA_I2C_RX 3 -#define OMAP_DMA_I2C_TX 4 -#define OMAP_DMA_EXT_NDMA_REQ 5 -#define OMAP_DMA_EXT_NDMA_REQ2 6 -#define OMAP_DMA_UWIRE_TX 7 -#define OMAP_DMA_MCBSP1_TX 8 -#define OMAP_DMA_MCBSP1_RX 9 -#define OMAP_DMA_MCBSP3_TX 10 -#define OMAP_DMA_MCBSP3_RX 11 -#define OMAP_DMA_UART1_TX 12 -#define OMAP_DMA_UART1_RX 13 -#define OMAP_DMA_UART2_TX 14 -#define OMAP_DMA_UART2_RX 15 -#define OMAP_DMA_MCBSP2_TX 16 -#define OMAP_DMA_MCBSP2_RX 17 -#define OMAP_DMA_UART3_TX 18 -#define OMAP_DMA_UART3_RX 19 -#define OMAP_DMA_CAMERA_IF_RX 20 -#define OMAP_DMA_MMC_TX 21 -#define OMAP_DMA_MMC_RX 22 -#define OMAP_DMA_NAND 23 -#define OMAP_DMA_IRQ_LCD_LINE 24 -#define OMAP_DMA_MEMORY_STICK 25 -#define OMAP_DMA_USB_W2FC_RX0 26 -#define OMAP_DMA_USB_W2FC_RX1 27 -#define OMAP_DMA_USB_W2FC_RX2 28 -#define OMAP_DMA_USB_W2FC_TX0 29 -#define OMAP_DMA_USB_W2FC_TX1 30 -#define OMAP_DMA_USB_W2FC_TX2 31 - -/* These are only for 1610 */ -#define OMAP_DMA_CRYPTO_DES_IN 32 -#define OMAP_DMA_SPI_TX 33 -#define OMAP_DMA_SPI_RX 34 -#define OMAP_DMA_CRYPTO_HASH 35 -#define OMAP_DMA_CCP_ATTN 36 -#define OMAP_DMA_CCP_FIFO_NOT_EMPTY 37 -#define OMAP_DMA_CMT_APE_TX_CHAN_0 38 -#define OMAP_DMA_CMT_APE_RV_CHAN_0 39 -#define OMAP_DMA_CMT_APE_TX_CHAN_1 40 -#define OMAP_DMA_CMT_APE_RV_CHAN_1 41 -#define OMAP_DMA_CMT_APE_TX_CHAN_2 42 -#define OMAP_DMA_CMT_APE_RV_CHAN_2 43 -#define OMAP_DMA_CMT_APE_TX_CHAN_3 44 -#define OMAP_DMA_CMT_APE_RV_CHAN_3 45 -#define OMAP_DMA_CMT_APE_TX_CHAN_4 46 -#define OMAP_DMA_CMT_APE_RV_CHAN_4 47 -#define OMAP_DMA_CMT_APE_TX_CHAN_5 48 -#define OMAP_DMA_CMT_APE_RV_CHAN_5 49 -#define OMAP_DMA_CMT_APE_TX_CHAN_6 50 -#define OMAP_DMA_CMT_APE_RV_CHAN_6 51 -#define OMAP_DMA_CMT_APE_TX_CHAN_7 52 -#define OMAP_DMA_CMT_APE_RV_CHAN_7 53 -#define OMAP_DMA_MMC2_TX 54 -#define OMAP_DMA_MMC2_RX 55 -#define OMAP_DMA_CRYPTO_DES_OUT 56 - -/* DMA channels for 24xx */ -#define OMAP24XX_DMA_NO_DEVICE 0 -#define OMAP24XX_DMA_XTI_DMA 1 /* S_DMA_0 */ -#define OMAP24XX_DMA_EXT_DMAREQ0 2 /* S_DMA_1 */ -#define OMAP24XX_DMA_EXT_DMAREQ1 3 /* S_DMA_2 */ -#define OMAP24XX_DMA_GPMC 4 /* S_DMA_3 */ -#define OMAP24XX_DMA_GFX 5 /* S_DMA_4 */ -#define OMAP24XX_DMA_DSS 6 /* S_DMA_5 */ -#define OMAP242X_DMA_VLYNQ_TX 7 /* S_DMA_6 */ -#define OMAP24XX_DMA_EXT_DMAREQ2 7 /* S_DMA_6 */ -#define OMAP24XX_DMA_CWT 8 /* S_DMA_7 */ -#define OMAP24XX_DMA_AES_TX 9 /* S_DMA_8 */ -#define OMAP24XX_DMA_AES_RX 10 /* S_DMA_9 */ -#define OMAP24XX_DMA_DES_TX 11 /* S_DMA_10 */ -#define OMAP24XX_DMA_DES_RX 12 /* S_DMA_11 */ -#define OMAP24XX_DMA_SHA1MD5_RX 13 /* S_DMA_12 */ -#define OMAP34XX_DMA_SHA2MD5_RX 13 /* S_DMA_12 */ -#define OMAP242X_DMA_EXT_DMAREQ2 14 /* S_DMA_13 */ -#define OMAP242X_DMA_EXT_DMAREQ3 15 /* S_DMA_14 */ -#define OMAP242X_DMA_EXT_DMAREQ4 16 /* S_DMA_15 */ -#define OMAP242X_DMA_EAC_AC_RD 17 /* S_DMA_16 */ -#define OMAP242X_DMA_EAC_AC_WR 18 /* S_DMA_17 */ -#define OMAP242X_DMA_EAC_MD_UL_RD 19 /* S_DMA_18 */ -#define OMAP242X_DMA_EAC_MD_UL_WR 20 /* S_DMA_19 */ -#define OMAP242X_DMA_EAC_MD_DL_RD 21 /* S_DMA_20 */ -#define OMAP242X_DMA_EAC_MD_DL_WR 22 /* S_DMA_21 */ -#define OMAP242X_DMA_EAC_BT_UL_RD 23 /* S_DMA_22 */ -#define OMAP242X_DMA_EAC_BT_UL_WR 24 /* S_DMA_23 */ -#define OMAP242X_DMA_EAC_BT_DL_RD 25 /* S_DMA_24 */ -#define OMAP242X_DMA_EAC_BT_DL_WR 26 /* S_DMA_25 */ -#define OMAP243X_DMA_EXT_DMAREQ3 14 /* S_DMA_13 */ -#define OMAP24XX_DMA_SPI3_TX0 15 /* S_DMA_14 */ -#define OMAP24XX_DMA_SPI3_RX0 16 /* S_DMA_15 */ -#define OMAP24XX_DMA_MCBSP3_TX 17 /* S_DMA_16 */ -#define OMAP24XX_DMA_MCBSP3_RX 18 /* S_DMA_17 */ -#define OMAP24XX_DMA_MCBSP4_TX 19 /* S_DMA_18 */ -#define OMAP24XX_DMA_MCBSP4_RX 20 /* S_DMA_19 */ -#define OMAP24XX_DMA_MCBSP5_TX 21 /* S_DMA_20 */ -#define OMAP24XX_DMA_MCBSP5_RX 22 /* S_DMA_21 */ -#define OMAP24XX_DMA_SPI3_TX1 23 /* S_DMA_22 */ -#define OMAP24XX_DMA_SPI3_RX1 24 /* S_DMA_23 */ -#define OMAP243X_DMA_EXT_DMAREQ4 25 /* S_DMA_24 */ -#define OMAP243X_DMA_EXT_DMAREQ5 26 /* S_DMA_25 */ -#define OMAP34XX_DMA_I2C3_TX 25 /* S_DMA_24 */ -#define OMAP34XX_DMA_I2C3_RX 26 /* S_DMA_25 */ -#define OMAP24XX_DMA_I2C1_TX 27 /* S_DMA_26 */ -#define OMAP24XX_DMA_I2C1_RX 28 /* S_DMA_27 */ -#define OMAP24XX_DMA_I2C2_TX 29 /* S_DMA_28 */ -#define OMAP24XX_DMA_I2C2_RX 30 /* S_DMA_29 */ -#define OMAP24XX_DMA_MCBSP1_TX 31 /* S_DMA_30 */ -#define OMAP24XX_DMA_MCBSP1_RX 32 /* S_DMA_31 */ -#define OMAP24XX_DMA_MCBSP2_TX 33 /* S_DMA_32 */ -#define OMAP24XX_DMA_MCBSP2_RX 34 /* S_DMA_33 */ -#define OMAP24XX_DMA_SPI1_TX0 35 /* S_DMA_34 */ -#define OMAP24XX_DMA_SPI1_RX0 36 /* S_DMA_35 */ -#define OMAP24XX_DMA_SPI1_TX1 37 /* S_DMA_36 */ -#define OMAP24XX_DMA_SPI1_RX1 38 /* S_DMA_37 */ -#define OMAP24XX_DMA_SPI1_TX2 39 /* S_DMA_38 */ -#define OMAP24XX_DMA_SPI1_RX2 40 /* S_DMA_39 */ -#define OMAP24XX_DMA_SPI1_TX3 41 /* S_DMA_40 */ -#define OMAP24XX_DMA_SPI1_RX3 42 /* S_DMA_41 */ -#define OMAP24XX_DMA_SPI2_TX0 43 /* S_DMA_42 */ -#define OMAP24XX_DMA_SPI2_RX0 44 /* S_DMA_43 */ -#define OMAP24XX_DMA_SPI2_TX1 45 /* S_DMA_44 */ -#define OMAP24XX_DMA_SPI2_RX1 46 /* S_DMA_45 */ -#define OMAP24XX_DMA_MMC2_TX 47 /* S_DMA_46 */ -#define OMAP24XX_DMA_MMC2_RX 48 /* S_DMA_47 */ -#define OMAP24XX_DMA_UART1_TX 49 /* S_DMA_48 */ -#define OMAP24XX_DMA_UART1_RX 50 /* S_DMA_49 */ -#define OMAP24XX_DMA_UART2_TX 51 /* S_DMA_50 */ -#define OMAP24XX_DMA_UART2_RX 52 /* S_DMA_51 */ -#define OMAP24XX_DMA_UART3_TX 53 /* S_DMA_52 */ -#define OMAP24XX_DMA_UART3_RX 54 /* S_DMA_53 */ -#define OMAP24XX_DMA_USB_W2FC_TX0 55 /* S_DMA_54 */ -#define OMAP24XX_DMA_USB_W2FC_RX0 56 /* S_DMA_55 */ -#define OMAP24XX_DMA_USB_W2FC_TX1 57 /* S_DMA_56 */ -#define OMAP24XX_DMA_USB_W2FC_RX1 58 /* S_DMA_57 */ -#define OMAP24XX_DMA_USB_W2FC_TX2 59 /* S_DMA_58 */ -#define OMAP24XX_DMA_USB_W2FC_RX2 60 /* S_DMA_59 */ -#define OMAP24XX_DMA_MMC1_TX 61 /* S_DMA_60 */ -#define OMAP24XX_DMA_MMC1_RX 62 /* S_DMA_61 */ -#define OMAP24XX_DMA_MS 63 /* S_DMA_62 */ -#define OMAP242X_DMA_EXT_DMAREQ5 64 /* S_DMA_63 */ -#define OMAP243X_DMA_EXT_DMAREQ6 64 /* S_DMA_63 */ -#define OMAP34XX_DMA_EXT_DMAREQ3 64 /* S_DMA_63 */ -#define OMAP34XX_DMA_AES2_TX 65 /* S_DMA_64 */ -#define OMAP34XX_DMA_AES2_RX 66 /* S_DMA_65 */ -#define OMAP34XX_DMA_DES2_TX 67 /* S_DMA_66 */ -#define OMAP34XX_DMA_DES2_RX 68 /* S_DMA_67 */ -#define OMAP34XX_DMA_SHA1MD5_RX 69 /* S_DMA_68 */ -#define OMAP34XX_DMA_SPI4_TX0 70 /* S_DMA_69 */ -#define OMAP34XX_DMA_SPI4_RX0 71 /* S_DMA_70 */ -#define OMAP34XX_DSS_DMA0 72 /* S_DMA_71 */ -#define OMAP34XX_DSS_DMA1 73 /* S_DMA_72 */ -#define OMAP34XX_DSS_DMA2 74 /* S_DMA_73 */ -#define OMAP34XX_DSS_DMA3 75 /* S_DMA_74 */ -#define OMAP34XX_DMA_MMC3_TX 77 /* S_DMA_76 */ -#define OMAP34XX_DMA_MMC3_RX 78 /* S_DMA_77 */ -#define OMAP34XX_DMA_USIM_TX 79 /* S_DMA_78 */ -#define OMAP34XX_DMA_USIM_RX 80 /* S_DMA_79 */ - -/* DMA request lines for 44xx */ -#define OMAP44XX_DMA_DSS_DISPC_REQ 6 /* S_DMA_5 */ -#define OMAP44XX_DMA_SYS_REQ2 7 /* S_DMA_6 */ -#define OMAP44XX_DMA_ISS_REQ1 9 /* S_DMA_8 */ -#define OMAP44XX_DMA_ISS_REQ2 10 /* S_DMA_9 */ -#define OMAP44XX_DMA_ISS_REQ3 12 /* S_DMA_11 */ -#define OMAP44XX_DMA_ISS_REQ4 13 /* S_DMA_12 */ -#define OMAP44XX_DMA_DSS_RFBI_REQ 14 /* S_DMA_13 */ -#define OMAP44XX_DMA_SPI3_TX0 15 /* S_DMA_14 */ -#define OMAP44XX_DMA_SPI3_RX0 16 /* S_DMA_15 */ -#define OMAP44XX_DMA_MCBSP2_TX 17 /* S_DMA_16 */ -#define OMAP44XX_DMA_MCBSP2_RX 18 /* S_DMA_17 */ -#define OMAP44XX_DMA_MCBSP3_TX 19 /* S_DMA_18 */ -#define OMAP44XX_DMA_MCBSP3_RX 20 /* S_DMA_19 */ -#define OMAP44XX_DMA_SPI3_TX1 23 /* S_DMA_22 */ -#define OMAP44XX_DMA_SPI3_RX1 24 /* S_DMA_23 */ -#define OMAP44XX_DMA_I2C3_TX 25 /* S_DMA_24 */ -#define OMAP44XX_DMA_I2C3_RX 26 /* S_DMA_25 */ -#define OMAP44XX_DMA_I2C1_TX 27 /* S_DMA_26 */ -#define OMAP44XX_DMA_I2C1_RX 28 /* S_DMA_27 */ -#define OMAP44XX_DMA_I2C2_TX 29 /* S_DMA_28 */ -#define OMAP44XX_DMA_I2C2_RX 30 /* S_DMA_29 */ -#define OMAP44XX_DMA_MCBSP4_TX 31 /* S_DMA_30 */ -#define OMAP44XX_DMA_MCBSP4_RX 32 /* S_DMA_31 */ -#define OMAP44XX_DMA_MCBSP1_TX 33 /* S_DMA_32 */ -#define OMAP44XX_DMA_MCBSP1_RX 34 /* S_DMA_33 */ -#define OMAP44XX_DMA_SPI1_TX0 35 /* S_DMA_34 */ -#define OMAP44XX_DMA_SPI1_RX0 36 /* S_DMA_35 */ -#define OMAP44XX_DMA_SPI1_TX1 37 /* S_DMA_36 */ -#define OMAP44XX_DMA_SPI1_RX1 38 /* S_DMA_37 */ -#define OMAP44XX_DMA_SPI1_TX2 39 /* S_DMA_38 */ -#define OMAP44XX_DMA_SPI1_RX2 40 /* S_DMA_39 */ -#define OMAP44XX_DMA_SPI1_TX3 41 /* S_DMA_40 */ -#define OMAP44XX_DMA_SPI1_RX3 42 /* S_DMA_41 */ -#define OMAP44XX_DMA_SPI2_TX0 43 /* S_DMA_42 */ -#define OMAP44XX_DMA_SPI2_RX0 44 /* S_DMA_43 */ -#define OMAP44XX_DMA_SPI2_TX1 45 /* S_DMA_44 */ -#define OMAP44XX_DMA_SPI2_RX1 46 /* S_DMA_45 */ -#define OMAP44XX_DMA_MMC2_TX 47 /* S_DMA_46 */ -#define OMAP44XX_DMA_MMC2_RX 48 /* S_DMA_47 */ -#define OMAP44XX_DMA_UART1_TX 49 /* S_DMA_48 */ -#define OMAP44XX_DMA_UART1_RX 50 /* S_DMA_49 */ -#define OMAP44XX_DMA_UART2_TX 51 /* S_DMA_50 */ -#define OMAP44XX_DMA_UART2_RX 52 /* S_DMA_51 */ -#define OMAP44XX_DMA_UART3_TX 53 /* S_DMA_52 */ -#define OMAP44XX_DMA_UART3_RX 54 /* S_DMA_53 */ -#define OMAP44XX_DMA_UART4_TX 55 /* S_DMA_54 */ -#define OMAP44XX_DMA_UART4_RX 56 /* S_DMA_55 */ -#define OMAP44XX_DMA_MMC4_TX 57 /* S_DMA_56 */ -#define OMAP44XX_DMA_MMC4_RX 58 /* S_DMA_57 */ -#define OMAP44XX_DMA_MMC5_TX 59 /* S_DMA_58 */ -#define OMAP44XX_DMA_MMC5_RX 60 /* S_DMA_59 */ -#define OMAP44XX_DMA_MMC1_TX 61 /* S_DMA_60 */ -#define OMAP44XX_DMA_MMC1_RX 62 /* S_DMA_61 */ -#define OMAP44XX_DMA_SYS_REQ3 64 /* S_DMA_63 */ -#define OMAP44XX_DMA_MCPDM_UP 65 /* S_DMA_64 */ -#define OMAP44XX_DMA_MCPDM_DL 66 /* S_DMA_65 */ -#define OMAP44XX_DMA_SPI4_TX0 70 /* S_DMA_69 */ -#define OMAP44XX_DMA_SPI4_RX0 71 /* S_DMA_70 */ -#define OMAP44XX_DMA_DSS_DSI1_REQ0 72 /* S_DMA_71 */ -#define OMAP44XX_DMA_DSS_DSI1_REQ1 73 /* S_DMA_72 */ -#define OMAP44XX_DMA_DSS_DSI1_REQ2 74 /* S_DMA_73 */ -#define OMAP44XX_DMA_DSS_DSI1_REQ3 75 /* S_DMA_74 */ -#define OMAP44XX_DMA_DSS_HDMI_REQ 76 /* S_DMA_75 */ -#define OMAP44XX_DMA_MMC3_TX 77 /* S_DMA_76 */ -#define OMAP44XX_DMA_MMC3_RX 78 /* S_DMA_77 */ -#define OMAP44XX_DMA_USIM_TX 79 /* S_DMA_78 */ -#define OMAP44XX_DMA_USIM_RX 80 /* S_DMA_79 */ -#define OMAP44XX_DMA_DSS_DSI2_REQ0 81 /* S_DMA_80 */ -#define OMAP44XX_DMA_DSS_DSI2_REQ1 82 /* S_DMA_81 */ -#define OMAP44XX_DMA_DSS_DSI2_REQ2 83 /* S_DMA_82 */ -#define OMAP44XX_DMA_DSS_DSI2_REQ3 84 /* S_DMA_83 */ -#define OMAP44XX_DMA_ABE_REQ0 101 /* S_DMA_100 */ -#define OMAP44XX_DMA_ABE_REQ1 102 /* S_DMA_101 */ -#define OMAP44XX_DMA_ABE_REQ2 103 /* S_DMA_102 */ -#define OMAP44XX_DMA_ABE_REQ3 104 /* S_DMA_103 */ -#define OMAP44XX_DMA_ABE_REQ4 105 /* S_DMA_104 */ -#define OMAP44XX_DMA_ABE_REQ5 106 /* S_DMA_105 */ -#define OMAP44XX_DMA_ABE_REQ6 107 /* S_DMA_106 */ -#define OMAP44XX_DMA_ABE_REQ7 108 /* S_DMA_107 */ -#define OMAP44XX_DMA_I2C4_TX 124 /* S_DMA_123 */ -#define OMAP44XX_DMA_I2C4_RX 125 /* S_DMA_124 */ - -/*----------------------------------------------------------------------------*/ - -/* Hardware registers for LCD DMA */ -#define OMAP1510_DMA_LCD_BASE (0xfffedb00) -#define OMAP1510_DMA_LCD_CTRL (OMAP1510_DMA_LCD_BASE + 0x00) -#define OMAP1510_DMA_LCD_TOP_F1_L (OMAP1510_DMA_LCD_BASE + 0x02) -#define OMAP1510_DMA_LCD_TOP_F1_U (OMAP1510_DMA_LCD_BASE + 0x04) -#define OMAP1510_DMA_LCD_BOT_F1_L (OMAP1510_DMA_LCD_BASE + 0x06) -#define OMAP1510_DMA_LCD_BOT_F1_U (OMAP1510_DMA_LCD_BASE + 0x08) - -#define OMAP1610_DMA_LCD_BASE (0xfffee300) -#define OMAP1610_DMA_LCD_CSDP (OMAP1610_DMA_LCD_BASE + 0xc0) -#define OMAP1610_DMA_LCD_CCR (OMAP1610_DMA_LCD_BASE + 0xc2) -#define OMAP1610_DMA_LCD_CTRL (OMAP1610_DMA_LCD_BASE + 0xc4) -#define OMAP1610_DMA_LCD_TOP_B1_L (OMAP1610_DMA_LCD_BASE + 0xc8) -#define OMAP1610_DMA_LCD_TOP_B1_U (OMAP1610_DMA_LCD_BASE + 0xca) -#define OMAP1610_DMA_LCD_BOT_B1_L (OMAP1610_DMA_LCD_BASE + 0xcc) -#define OMAP1610_DMA_LCD_BOT_B1_U (OMAP1610_DMA_LCD_BASE + 0xce) -#define OMAP1610_DMA_LCD_TOP_B2_L (OMAP1610_DMA_LCD_BASE + 0xd0) -#define OMAP1610_DMA_LCD_TOP_B2_U (OMAP1610_DMA_LCD_BASE + 0xd2) -#define OMAP1610_DMA_LCD_BOT_B2_L (OMAP1610_DMA_LCD_BASE + 0xd4) -#define OMAP1610_DMA_LCD_BOT_B2_U (OMAP1610_DMA_LCD_BASE + 0xd6) -#define OMAP1610_DMA_LCD_SRC_EI_B1 (OMAP1610_DMA_LCD_BASE + 0xd8) -#define OMAP1610_DMA_LCD_SRC_FI_B1_L (OMAP1610_DMA_LCD_BASE + 0xda) -#define OMAP1610_DMA_LCD_SRC_EN_B1 (OMAP1610_DMA_LCD_BASE + 0xe0) -#define OMAP1610_DMA_LCD_SRC_FN_B1 (OMAP1610_DMA_LCD_BASE + 0xe4) -#define OMAP1610_DMA_LCD_LCH_CTRL (OMAP1610_DMA_LCD_BASE + 0xea) -#define OMAP1610_DMA_LCD_SRC_FI_B1_U (OMAP1610_DMA_LCD_BASE + 0xf4) - -#define OMAP1_DMA_TOUT_IRQ (1 << 0) -#define OMAP_DMA_DROP_IRQ (1 << 1) -#define OMAP_DMA_HALF_IRQ (1 << 2) -#define OMAP_DMA_FRAME_IRQ (1 << 3) -#define OMAP_DMA_LAST_IRQ (1 << 4) -#define OMAP_DMA_BLOCK_IRQ (1 << 5) -#define OMAP1_DMA_SYNC_IRQ (1 << 6) -#define OMAP2_DMA_PKT_IRQ (1 << 7) -#define OMAP2_DMA_TRANS_ERR_IRQ (1 << 8) -#define OMAP2_DMA_SECURE_ERR_IRQ (1 << 9) -#define OMAP2_DMA_SUPERVISOR_ERR_IRQ (1 << 10) -#define OMAP2_DMA_MISALIGNED_ERR_IRQ (1 << 11) - -#define OMAP_DMA_DATA_TYPE_S8 0x00 -#define OMAP_DMA_DATA_TYPE_S16 0x01 -#define OMAP_DMA_DATA_TYPE_S32 0x02 - -#define OMAP_DMA_SYNC_ELEMENT 0x00 -#define OMAP_DMA_SYNC_FRAME 0x01 -#define OMAP_DMA_SYNC_BLOCK 0x02 -#define OMAP_DMA_SYNC_PACKET 0x03 - -#define OMAP_DMA_SRC_SYNC 0x01 -#define OMAP_DMA_DST_SYNC 0x00 - -#define OMAP_DMA_PORT_EMIFF 0x00 -#define OMAP_DMA_PORT_EMIFS 0x01 -#define OMAP_DMA_PORT_OCP_T1 0x02 -#define OMAP_DMA_PORT_TIPB 0x03 -#define OMAP_DMA_PORT_OCP_T2 0x04 -#define OMAP_DMA_PORT_MPUI 0x05 - -#define OMAP_DMA_AMODE_CONSTANT 0x00 -#define OMAP_DMA_AMODE_POST_INC 0x01 -#define OMAP_DMA_AMODE_SINGLE_IDX 0x02 -#define OMAP_DMA_AMODE_DOUBLE_IDX 0x03 - -#define DMA_DEFAULT_FIFO_DEPTH 0x10 -#define DMA_DEFAULT_ARB_RATE 0x01 -/* Pass THREAD_RESERVE ORed with THREAD_FIFO for tparams */ -#define DMA_THREAD_RESERVE_NORM (0x00 << 12) /* Def */ -#define DMA_THREAD_RESERVE_ONET (0x01 << 12) -#define DMA_THREAD_RESERVE_TWOT (0x02 << 12) -#define DMA_THREAD_RESERVE_THREET (0x03 << 12) -#define DMA_THREAD_FIFO_NONE (0x00 << 14) /* Def */ -#define DMA_THREAD_FIFO_75 (0x01 << 14) -#define DMA_THREAD_FIFO_25 (0x02 << 14) -#define DMA_THREAD_FIFO_50 (0x03 << 14) - -/* DMA4_OCP_SYSCONFIG bits */ -#define DMA_SYSCONFIG_MIDLEMODE_MASK (3 << 12) -#define DMA_SYSCONFIG_CLOCKACTIVITY_MASK (3 << 8) -#define DMA_SYSCONFIG_EMUFREE (1 << 5) -#define DMA_SYSCONFIG_SIDLEMODE_MASK (3 << 3) -#define DMA_SYSCONFIG_SOFTRESET (1 << 2) -#define DMA_SYSCONFIG_AUTOIDLE (1 << 0) - -#define DMA_SYSCONFIG_MIDLEMODE(n) ((n) << 12) -#define DMA_SYSCONFIG_SIDLEMODE(n) ((n) << 3) - -#define DMA_IDLEMODE_SMARTIDLE 0x2 -#define DMA_IDLEMODE_NO_IDLE 0x1 -#define DMA_IDLEMODE_FORCE_IDLE 0x0 - -/* Chaining modes*/ -#ifndef CONFIG_ARCH_OMAP1 -#define OMAP_DMA_STATIC_CHAIN 0x1 -#define OMAP_DMA_DYNAMIC_CHAIN 0x2 -#define OMAP_DMA_CHAIN_ACTIVE 0x1 -#define OMAP_DMA_CHAIN_INACTIVE 0x0 -#endif - -#define DMA_CH_PRIO_HIGH 0x1 -#define DMA_CH_PRIO_LOW 0x0 /* Def */ - -/* LCD DMA block numbers */ -enum { - OMAP_LCD_DMA_B1_TOP, - OMAP_LCD_DMA_B1_BOTTOM, - OMAP_LCD_DMA_B2_TOP, - OMAP_LCD_DMA_B2_BOTTOM -}; - -enum omap_dma_burst_mode { - OMAP_DMA_DATA_BURST_DIS = 0, - OMAP_DMA_DATA_BURST_4, - OMAP_DMA_DATA_BURST_8, - OMAP_DMA_DATA_BURST_16, -}; - -enum end_type { - OMAP_DMA_LITTLE_ENDIAN = 0, - OMAP_DMA_BIG_ENDIAN -}; - -enum omap_dma_color_mode { - OMAP_DMA_COLOR_DIS = 0, - OMAP_DMA_CONSTANT_FILL, - OMAP_DMA_TRANSPARENT_COPY -}; - -enum omap_dma_write_mode { - OMAP_DMA_WRITE_NON_POSTED = 0, - OMAP_DMA_WRITE_POSTED, - OMAP_DMA_WRITE_LAST_NON_POSTED -}; - -enum omap_dma_channel_mode { - OMAP_DMA_LCH_2D = 0, - OMAP_DMA_LCH_G, - OMAP_DMA_LCH_P, - OMAP_DMA_LCH_PD -}; - -struct omap_dma_channel_params { - int data_type; /* data type 8,16,32 */ - int elem_count; /* number of elements in a frame */ - int frame_count; /* number of frames in a element */ - - int src_port; /* Only on OMAP1 REVISIT: Is this needed? */ - int src_amode; /* constant, post increment, indexed, - double indexed */ - unsigned long src_start; /* source address : physical */ - int src_ei; /* source element index */ - int src_fi; /* source frame index */ - - int dst_port; /* Only on OMAP1 REVISIT: Is this needed? */ - int dst_amode; /* constant, post increment, indexed, - double indexed */ - unsigned long dst_start; /* source address : physical */ - int dst_ei; /* source element index */ - int dst_fi; /* source frame index */ - - int trigger; /* trigger attached if the channel is - synchronized */ - int sync_mode; /* sycn on element, frame , block or packet */ - int src_or_dst_synch; /* source synch(1) or destination synch(0) */ - - int ie; /* interrupt enabled */ - - unsigned char read_prio;/* read priority */ - unsigned char write_prio;/* write priority */ - -#ifndef CONFIG_ARCH_OMAP1 - enum omap_dma_burst_mode burst_mode; /* Burst mode 4/8/16 words */ -#endif -}; - - -extern void omap_set_dma_priority(int lch, int dst_port, int priority); -extern int omap_request_dma(int dev_id, const char *dev_name, - void (*callback)(int lch, u16 ch_status, void *data), - void *data, int *dma_ch); -extern void omap_enable_dma_irq(int ch, u16 irq_bits); -extern void omap_disable_dma_irq(int ch, u16 irq_bits); -extern void omap_free_dma(int ch); -extern void omap_start_dma(int lch); -extern void omap_stop_dma(int lch); -extern void omap_set_dma_transfer_params(int lch, int data_type, - int elem_count, int frame_count, - int sync_mode, - int dma_trigger, int src_or_dst_synch); -extern void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, - u32 color); -extern void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode); -extern void omap_set_dma_channel_mode(int lch, enum omap_dma_channel_mode mode); - -extern void omap_set_dma_src_params(int lch, int src_port, int src_amode, - unsigned long src_start, - int src_ei, int src_fi); -extern void omap_set_dma_src_index(int lch, int eidx, int fidx); -extern void omap_set_dma_src_data_pack(int lch, int enable); -extern void omap_set_dma_src_burst_mode(int lch, - enum omap_dma_burst_mode burst_mode); - -extern void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode, - unsigned long dest_start, - int dst_ei, int dst_fi); -extern void omap_set_dma_dest_index(int lch, int eidx, int fidx); -extern void omap_set_dma_dest_data_pack(int lch, int enable); -extern void omap_set_dma_dest_burst_mode(int lch, - enum omap_dma_burst_mode burst_mode); - -extern void omap_set_dma_params(int lch, - struct omap_dma_channel_params *params); - -extern void omap_dma_link_lch(int lch_head, int lch_queue); -extern void omap_dma_unlink_lch(int lch_head, int lch_queue); - -extern int omap_set_dma_callback(int lch, - void (*callback)(int lch, u16 ch_status, void *data), - void *data); -extern dma_addr_t omap_get_dma_src_pos(int lch); -extern dma_addr_t omap_get_dma_dst_pos(int lch); -extern void omap_clear_dma(int lch); -extern int omap_get_dma_active_status(int lch); -extern int omap_dma_running(void); -extern void omap_dma_set_global_params(int arb_rate, int max_fifo_depth, - int tparams); -extern int omap_dma_set_prio_lch(int lch, unsigned char read_prio, - unsigned char write_prio); -extern void omap_set_dma_dst_endian_type(int lch, enum end_type etype); -extern void omap_set_dma_src_endian_type(int lch, enum end_type etype); -extern int omap_get_dma_index(int lch, int *ei, int *fi); - -/* Chaining APIs */ -#ifndef CONFIG_ARCH_OMAP1 -extern int omap_request_dma_chain(int dev_id, const char *dev_name, - void (*callback) (int lch, u16 ch_status, - void *data), - int *chain_id, int no_of_chans, - int chain_mode, - struct omap_dma_channel_params params); -extern int omap_free_dma_chain(int chain_id); -extern int omap_dma_chain_a_transfer(int chain_id, int src_start, - int dest_start, int elem_count, - int frame_count, void *callbk_data); -extern int omap_start_dma_chain_transfers(int chain_id); -extern int omap_stop_dma_chain_transfers(int chain_id); -extern int omap_get_dma_chain_index(int chain_id, int *ei, int *fi); -extern int omap_get_dma_chain_dst_pos(int chain_id); -extern int omap_get_dma_chain_src_pos(int chain_id); - -extern int omap_modify_dma_chain_params(int chain_id, - struct omap_dma_channel_params params); -extern int omap_dma_chain_status(int chain_id); -#endif - -/* LCD DMA functions */ -extern int omap_request_lcd_dma(void (*callback)(u16 status, void *data), - void *data); -extern void omap_free_lcd_dma(void); -extern void omap_setup_lcd_dma(void); -extern void omap_enable_lcd_dma(void); -extern void omap_stop_lcd_dma(void); -extern void omap_set_lcd_dma_ext_controller(int external); -extern void omap_set_lcd_dma_single_transfer(int single); -extern void omap_set_lcd_dma_b1(unsigned long addr, u16 fb_xres, u16 fb_yres, - int data_type); -extern void omap_set_lcd_dma_b1_rotation(int rotate); -extern void omap_set_lcd_dma_b1_vxres(unsigned long vxres); -extern void omap_set_lcd_dma_b1_mirror(int mirror); -extern void omap_set_lcd_dma_b1_scale(unsigned int xscale, unsigned int yscale); - -#endif /* __ASM_ARCH_DMA_H */ diff --git a/arch/arm/plat-omap/include/mach/dmtimer.h b/arch/arm/plat-omap/include/mach/dmtimer.h deleted file mode 100644 index 20f1054c0a8..00000000000 --- a/arch/arm/plat-omap/include/mach/dmtimer.h +++ /dev/null @@ -1,84 +0,0 @@ -/* - * arch/arm/plat-omap/include/mach/dmtimer.h - * - * OMAP Dual-Mode Timers - * - * Copyright (C) 2005 Nokia Corporation - * Author: Lauri Leukkunen <lauri.leukkunen@nokia.com> - * PWM and clock framwork support by Timo Teras. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -#ifndef __ASM_ARCH_DMTIMER_H -#define __ASM_ARCH_DMTIMER_H - -/* clock sources */ -#define OMAP_TIMER_SRC_SYS_CLK 0x00 -#define OMAP_TIMER_SRC_32_KHZ 0x01 -#define OMAP_TIMER_SRC_EXT_CLK 0x02 - -/* timer interrupt enable bits */ -#define OMAP_TIMER_INT_CAPTURE (1 << 2) -#define OMAP_TIMER_INT_OVERFLOW (1 << 1) -#define OMAP_TIMER_INT_MATCH (1 << 0) - -/* trigger types */ -#define OMAP_TIMER_TRIGGER_NONE 0x00 -#define OMAP_TIMER_TRIGGER_OVERFLOW 0x01 -#define OMAP_TIMER_TRIGGER_OVERFLOW_AND_COMPARE 0x02 - -struct omap_dm_timer; -struct clk; - -int omap_dm_timer_init(void); - -struct omap_dm_timer *omap_dm_timer_request(void); -struct omap_dm_timer *omap_dm_timer_request_specific(int timer_id); -void omap_dm_timer_free(struct omap_dm_timer *timer); -void omap_dm_timer_enable(struct omap_dm_timer *timer); -void omap_dm_timer_disable(struct omap_dm_timer *timer); - -int omap_dm_timer_get_irq(struct omap_dm_timer *timer); - -u32 omap_dm_timer_modify_idlect_mask(u32 inputmask); -struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer); - -void omap_dm_timer_trigger(struct omap_dm_timer *timer); -void omap_dm_timer_start(struct omap_dm_timer *timer); -void omap_dm_timer_stop(struct omap_dm_timer *timer); - -int omap_dm_timer_set_source(struct omap_dm_timer *timer, int source); -void omap_dm_timer_set_load(struct omap_dm_timer *timer, int autoreload, unsigned int value); -void omap_dm_timer_set_load_start(struct omap_dm_timer *timer, int autoreload, unsigned int value); -void omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable, unsigned int match); -void omap_dm_timer_set_pwm(struct omap_dm_timer *timer, int def_on, int toggle, int trigger); -void omap_dm_timer_set_prescaler(struct omap_dm_timer *timer, int prescaler); - -void omap_dm_timer_set_int_enable(struct omap_dm_timer *timer, unsigned int value); - -unsigned int omap_dm_timer_read_status(struct omap_dm_timer *timer); -void omap_dm_timer_write_status(struct omap_dm_timer *timer, unsigned int value); -unsigned int omap_dm_timer_read_counter(struct omap_dm_timer *timer); -void omap_dm_timer_write_counter(struct omap_dm_timer *timer, unsigned int value); - -int omap_dm_timers_active(void); - - -#endif /* __ASM_ARCH_DMTIMER_H */ diff --git a/arch/arm/plat-omap/include/mach/dsp_common.h b/arch/arm/plat-omap/include/mach/dsp_common.h deleted file mode 100644 index da97736f3ef..00000000000 --- a/arch/arm/plat-omap/include/mach/dsp_common.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * This file is part of OMAP DSP driver (DSP Gateway version 3.3.1) - * - * Copyright (C) 2004-2006 Nokia Corporation. All rights reserved. - * - * Contact: Toshihiro Kobayashi <toshihiro.kobayashi@nokia.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA - * 02110-1301 USA - * - */ - -#ifndef ASM_ARCH_DSP_COMMON_H -#define ASM_ARCH_DSP_COMMON_H - -#if defined(CONFIG_ARCH_OMAP1) && defined(CONFIG_OMAP_MMU_FWK) -extern void omap_dsp_request_mpui(void); -extern void omap_dsp_release_mpui(void); -extern int omap_dsp_request_mem(void); -extern int omap_dsp_release_mem(void); -#else -static inline int omap_dsp_request_mem(void) -{ - return 0; -} -#define omap_dsp_release_mem() do {} while (0) -#endif - -#endif /* ASM_ARCH_DSP_COMMON_H */ diff --git a/arch/arm/plat-omap/include/mach/entry-macro.S b/arch/arm/plat-omap/include/mach/entry-macro.S deleted file mode 100644 index a5592991634..00000000000 --- a/arch/arm/plat-omap/include/mach/entry-macro.S +++ /dev/null @@ -1,172 +0,0 @@ -/* - * arch/arm/plat-omap/include/mach/entry-macro.S - * - * Low-level IRQ helper macros for OMAP-based platforms - * - * Copyright (C) 2009 Texas Instruments - * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ -#include <mach/hardware.h> -#include <mach/io.h> -#include <mach/irqs.h> -#include <asm/hardware/gic.h> - -#if defined(CONFIG_ARCH_OMAP1) - -#if defined(CONFIG_ARCH_OMAP730) && \ - (defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX)) -#error "FIXME: OMAP730 doesn't support multiple-OMAP" -#elif defined(CONFIG_ARCH_OMAP730) -#define INT_IH2_IRQ INT_730_IH2_IRQ -#elif defined(CONFIG_ARCH_OMAP15XX) -#define INT_IH2_IRQ INT_1510_IH2_IRQ -#elif defined(CONFIG_ARCH_OMAP16XX) -#define INT_IH2_IRQ INT_1610_IH2_IRQ -#else -#warning "IH2 IRQ defaulted" -#define INT_IH2_IRQ INT_1510_IH2_IRQ -#endif - - .macro disable_fiq - .endm - - .macro get_irqnr_preamble, base, tmp - .endm - - .macro arch_ret_to_user, tmp1, tmp2 - .endm - - .macro get_irqnr_and_base, irqnr, irqstat, base, tmp - ldr \base, =OMAP1_IO_ADDRESS(OMAP_IH1_BASE) - ldr \irqnr, [\base, #IRQ_ITR_REG_OFFSET] - ldr \tmp, [\base, #IRQ_MIR_REG_OFFSET] - mov \irqstat, #0xffffffff - bic \tmp, \irqstat, \tmp - tst \irqnr, \tmp - beq 1510f - - ldr \irqnr, [\base, #IRQ_SIR_FIQ_REG_OFFSET] - cmp \irqnr, #0 - ldreq \irqnr, [\base, #IRQ_SIR_IRQ_REG_OFFSET] - cmpeq \irqnr, #INT_IH2_IRQ - ldreq \base, =OMAP1_IO_ADDRESS(OMAP_IH2_BASE) - ldreq \irqnr, [\base, #IRQ_SIR_IRQ_REG_OFFSET] - addeqs \irqnr, \irqnr, #32 -1510: - .endm - -#endif -#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \ - defined(CONFIG_ARCH_OMAP4) - -#include <mach/omap24xx.h> -#include <mach/omap34xx.h> - -/* REVISIT: This should be set dynamically if CONFIG_MULTI_OMAP2 is selected */ -#if defined(CONFIG_ARCH_OMAP2420) || defined(CONFIG_ARCH_OMAP2430) -#define OMAP2_VA_IC_BASE OMAP2_IO_ADDRESS(OMAP24XX_IC_BASE) -#elif defined(CONFIG_ARCH_OMAP34XX) -#define OMAP2_VA_IC_BASE OMAP2_IO_ADDRESS(OMAP34XX_IC_BASE) -#endif -#if defined(CONFIG_ARCH_OMAP4) -#include <mach/omap44xx.h> -#endif -#define INTCPS_SIR_IRQ_OFFSET 0x0040 /* Active interrupt offset */ -#define ACTIVEIRQ_MASK 0x7f /* Active interrupt bits */ - - .macro disable_fiq - .endm - - .macro get_irqnr_preamble, base, tmp - .endm - - .macro arch_ret_to_user, tmp1, tmp2 - .endm - -#ifndef CONFIG_ARCH_OMAP4 - .macro get_irqnr_and_base, irqnr, irqstat, base, tmp - ldr \base, =OMAP2_VA_IC_BASE - ldr \irqnr, [\base, #0x98] /* IRQ pending reg 1 */ - cmp \irqnr, #0x0 - bne 2222f - ldr \irqnr, [\base, #0xb8] /* IRQ pending reg 2 */ - cmp \irqnr, #0x0 - bne 2222f - ldr \irqnr, [\base, #0xd8] /* IRQ pending reg 3 */ - cmp \irqnr, #0x0 -2222: - ldrne \irqnr, [\base, #INTCPS_SIR_IRQ_OFFSET] - and \irqnr, \irqnr, #ACTIVEIRQ_MASK /* Clear spurious bits */ - - .endm -#else - /* - * The interrupt numbering scheme is defined in the - * interrupt controller spec. To wit: - * - * Interrupts 0-15 are IPI - * 16-28 are reserved - * 29-31 are local. We allow 30 to be used for the watchdog. - * 32-1020 are global - * 1021-1022 are reserved - * 1023 is "spurious" (no interrupt) - * - * For now, we ignore all local interrupts so only return an - * interrupt if it's between 30 and 1020. The test_for_ipi - * routine below will pick up on IPIs. - * A simple read from the controller will tell us the number - * of the highest priority enabled interrupt. - * We then just need to check whether it is in the - * valid range for an IRQ (30-1020 inclusive). - */ - .macro get_irqnr_and_base, irqnr, irqstat, base, tmp - ldr \base, =OMAP44XX_VA_GIC_CPU_BASE - ldr \irqstat, [\base, #GIC_CPU_INTACK] - - ldr \tmp, =1021 - - bic \irqnr, \irqstat, #0x1c00 - - cmp \irqnr, #29 - cmpcc \irqnr, \irqnr - cmpne \irqnr, \tmp - cmpcs \irqnr, \irqnr - .endm - - /* We assume that irqstat (the raw value of the IRQ acknowledge - * register) is preserved from the macro above. - * If there is an IPI, we immediately signal end of interrupt - * on the controller, since this requires the original irqstat - * value which we won't easily be able to recreate later. - */ - - .macro test_for_ipi, irqnr, irqstat, base, tmp - bic \irqnr, \irqstat, #0x1c00 - cmp \irqnr, #16 - it cc - strcc \irqstat, [\base, #GIC_CPU_EOI] - it cs - cmpcs \irqnr, \irqnr - .endm - - /* As above, this assumes that irqstat and base are preserved */ - - .macro test_for_ltirq, irqnr, irqstat, base, tmp - bic \irqnr, \irqstat, #0x1c00 - mov \tmp, #0 - cmp \irqnr, #29 - itt eq - moveq \tmp, #1 - streq \irqstat, [\base, #GIC_CPU_EOI] - cmp \tmp, #0 - .endm -#endif - - .macro irq_prio_table - .endm - -#endif diff --git a/arch/arm/plat-omap/include/mach/fpga.h b/arch/arm/plat-omap/include/mach/fpga.h deleted file mode 100644 index f1864a652f7..00000000000 --- a/arch/arm/plat-omap/include/mach/fpga.h +++ /dev/null @@ -1,197 +0,0 @@ -/* - * arch/arm/plat-omap/include/mach/fpga.h - * - * Interrupt handler for OMAP-1510 FPGA - * - * Copyright (C) 2001 RidgeRun, Inc. - * Author: Greg Lonnon <glonnon@ridgerun.com> - * - * Copyright (C) 2002 MontaVista Software, Inc. - * - * Separated FPGA interrupts from innovator1510.c and cleaned up for 2.6 - * Copyright (C) 2004 Nokia Corporation by Tony Lindrgen <tony@atomide.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef __ASM_ARCH_OMAP_FPGA_H -#define __ASM_ARCH_OMAP_FPGA_H - -#if defined(CONFIG_MACH_OMAP_INNOVATOR) && defined(CONFIG_ARCH_OMAP15XX) -extern void omap1510_fpga_init_irq(void); -#else -#define omap1510_fpga_init_irq() (0) -#endif - -#define fpga_read(reg) __raw_readb(reg) -#define fpga_write(val, reg) __raw_writeb(val, reg) - -/* - * --------------------------------------------------------------------------- - * H2/P2 Debug board FPGA - * --------------------------------------------------------------------------- - */ -/* maps in the FPGA registers and the ETHR registers */ -#define H2P2_DBG_FPGA_BASE IOMEM(0xE8000000) /* VA */ -#define H2P2_DBG_FPGA_SIZE SZ_4K /* SIZE */ -#define H2P2_DBG_FPGA_START 0x04000000 /* PA */ - -#define H2P2_DBG_FPGA_ETHR_START (H2P2_DBG_FPGA_START + 0x300) -#define H2P2_DBG_FPGA_FPGA_REV (H2P2_DBG_FPGA_BASE + 0x10) /* FPGA Revision */ -#define H2P2_DBG_FPGA_BOARD_REV (H2P2_DBG_FPGA_BASE + 0x12) /* Board Revision */ -#define H2P2_DBG_FPGA_GPIO (H2P2_DBG_FPGA_BASE + 0x14) /* GPIO outputs */ -#define H2P2_DBG_FPGA_LEDS (H2P2_DBG_FPGA_BASE + 0x16) /* LEDs outputs */ -#define H2P2_DBG_FPGA_MISC_INPUTS (H2P2_DBG_FPGA_BASE + 0x18) /* Misc inputs */ -#define H2P2_DBG_FPGA_LAN_STATUS (H2P2_DBG_FPGA_BASE + 0x1A) /* LAN Status line */ -#define H2P2_DBG_FPGA_LAN_RESET (H2P2_DBG_FPGA_BASE + 0x1C) /* LAN Reset line */ - -/* NOTE: most boards don't have a static mapping for the FPGA ... */ -struct h2p2_dbg_fpga { - /* offset 0x00 */ - u16 smc91x[8]; - /* offset 0x10 */ - u16 fpga_rev; - u16 board_rev; - u16 gpio_outputs; - u16 leds; - /* offset 0x18 */ - u16 misc_inputs; - u16 lan_status; - u16 lan_reset; - u16 reserved0; - /* offset 0x20 */ - u16 ps2_data; - u16 ps2_ctrl; - /* plus also 4 rs232 ports ... */ -}; - -/* LEDs definition on debug board (16 LEDs, all physically green) */ -#define H2P2_DBG_FPGA_LED_GREEN (1 << 15) -#define H2P2_DBG_FPGA_LED_AMBER (1 << 14) -#define H2P2_DBG_FPGA_LED_RED (1 << 13) -#define H2P2_DBG_FPGA_LED_BLUE (1 << 12) -/* cpu0 load-meter LEDs */ -#define H2P2_DBG_FPGA_LOAD_METER (1 << 0) // A bit of fun on our board ... -#define H2P2_DBG_FPGA_LOAD_METER_SIZE 11 -#define H2P2_DBG_FPGA_LOAD_METER_MASK ((1 << H2P2_DBG_FPGA_LOAD_METER_SIZE) - 1) - -#define H2P2_DBG_FPGA_P2_LED_TIMER (1 << 0) -#define H2P2_DBG_FPGA_P2_LED_IDLE (1 << 1) - -/* - * --------------------------------------------------------------------------- - * OMAP-1510 FPGA - * --------------------------------------------------------------------------- - */ -#define OMAP1510_FPGA_BASE IOMEM(0xE8000000) /* VA */ -#define OMAP1510_FPGA_SIZE SZ_4K -#define OMAP1510_FPGA_START 0x08000000 /* PA */ - -/* Revision */ -#define OMAP1510_FPGA_REV_LOW (OMAP1510_FPGA_BASE + 0x0) -#define OMAP1510_FPGA_REV_HIGH (OMAP1510_FPGA_BASE + 0x1) - -#define OMAP1510_FPGA_LCD_PANEL_CONTROL (OMAP1510_FPGA_BASE + 0x2) -#define OMAP1510_FPGA_LED_DIGIT (OMAP1510_FPGA_BASE + 0x3) -#define INNOVATOR_FPGA_HID_SPI (OMAP1510_FPGA_BASE + 0x4) -#define OMAP1510_FPGA_POWER (OMAP1510_FPGA_BASE + 0x5) - -/* Interrupt status */ -#define OMAP1510_FPGA_ISR_LO (OMAP1510_FPGA_BASE + 0x6) -#define OMAP1510_FPGA_ISR_HI (OMAP1510_FPGA_BASE + 0x7) - -/* Interrupt mask */ -#define OMAP1510_FPGA_IMR_LO (OMAP1510_FPGA_BASE + 0x8) -#define OMAP1510_FPGA_IMR_HI (OMAP1510_FPGA_BASE + 0x9) - -/* Reset registers */ -#define OMAP1510_FPGA_HOST_RESET (OMAP1510_FPGA_BASE + 0xa) -#define OMAP1510_FPGA_RST (OMAP1510_FPGA_BASE + 0xb) - -#define OMAP1510_FPGA_AUDIO (OMAP1510_FPGA_BASE + 0xc) -#define OMAP1510_FPGA_DIP (OMAP1510_FPGA_BASE + 0xe) -#define OMAP1510_FPGA_FPGA_IO (OMAP1510_FPGA_BASE + 0xf) -#define OMAP1510_FPGA_UART1 (OMAP1510_FPGA_BASE + 0x14) -#define OMAP1510_FPGA_UART2 (OMAP1510_FPGA_BASE + 0x15) -#define OMAP1510_FPGA_OMAP1510_STATUS (OMAP1510_FPGA_BASE + 0x16) -#define OMAP1510_FPGA_BOARD_REV (OMAP1510_FPGA_BASE + 0x18) -#define OMAP1510P1_PPT_DATA (OMAP1510_FPGA_BASE + 0x100) -#define OMAP1510P1_PPT_STATUS (OMAP1510_FPGA_BASE + 0x101) -#define OMAP1510P1_PPT_CONTROL (OMAP1510_FPGA_BASE + 0x102) - -#define OMAP1510_FPGA_TOUCHSCREEN (OMAP1510_FPGA_BASE + 0x204) - -#define INNOVATOR_FPGA_INFO (OMAP1510_FPGA_BASE + 0x205) -#define INNOVATOR_FPGA_LCD_BRIGHT_LO (OMAP1510_FPGA_BASE + 0x206) -#define INNOVATOR_FPGA_LCD_BRIGHT_HI (OMAP1510_FPGA_BASE + 0x207) -#define INNOVATOR_FPGA_LED_GRN_LO (OMAP1510_FPGA_BASE + 0x208) -#define INNOVATOR_FPGA_LED_GRN_HI (OMAP1510_FPGA_BASE + 0x209) -#define INNOVATOR_FPGA_LED_RED_LO (OMAP1510_FPGA_BASE + 0x20a) -#define INNOVATOR_FPGA_LED_RED_HI (OMAP1510_FPGA_BASE + 0x20b) -#define INNOVATOR_FPGA_CAM_USB_CONTROL (OMAP1510_FPGA_BASE + 0x20c) -#define INNOVATOR_FPGA_EXP_CONTROL (OMAP1510_FPGA_BASE + 0x20d) -#define INNOVATOR_FPGA_ISR2 (OMAP1510_FPGA_BASE + 0x20e) -#define INNOVATOR_FPGA_IMR2 (OMAP1510_FPGA_BASE + 0x210) - -#define OMAP1510_FPGA_ETHR_START (OMAP1510_FPGA_START + 0x300) - -/* - * Power up Giga UART driver, turn on HID clock. - * Turn off BT power, since we're not using it and it - * draws power. - */ -#define OMAP1510_FPGA_RESET_VALUE 0x42 - -#define OMAP1510_FPGA_PCR_IF_PD0 (1 << 7) -#define OMAP1510_FPGA_PCR_COM2_EN (1 << 6) -#define OMAP1510_FPGA_PCR_COM1_EN (1 << 5) -#define OMAP1510_FPGA_PCR_EXP_PD0 (1 << 4) -#define OMAP1510_FPGA_PCR_EXP_PD1 (1 << 3) -#define OMAP1510_FPGA_PCR_48MHZ_CLK (1 << 2) -#define OMAP1510_FPGA_PCR_4MHZ_CLK (1 << 1) -#define OMAP1510_FPGA_PCR_RSRVD_BIT0 (1 << 0) - -/* - * Innovator/OMAP1510 FPGA HID register bit definitions - */ -#define OMAP1510_FPGA_HID_SCLK (1<<0) /* output */ -#define OMAP1510_FPGA_HID_MOSI (1<<1) /* output */ -#define OMAP1510_FPGA_HID_nSS (1<<2) /* output 0/1 chip idle/select */ -#define OMAP1510_FPGA_HID_nHSUS (1<<3) /* output 0/1 host active/suspended */ -#define OMAP1510_FPGA_HID_MISO (1<<4) /* input */ -#define OMAP1510_FPGA_HID_ATN (1<<5) /* input 0/1 chip idle/ATN */ -#define OMAP1510_FPGA_HID_rsrvd (1<<6) -#define OMAP1510_FPGA_HID_RESETn (1<<7) /* output - 0/1 USAR reset/run */ - -/* The FPGA IRQ is cascaded through GPIO_13 */ -#define OMAP1510_INT_FPGA (IH_GPIO_BASE + 13) - -/* IRQ Numbers for interrupts muxed through the FPGA */ -#define OMAP1510_INT_FPGA_ATN (OMAP_FPGA_IRQ_BASE + 0) -#define OMAP1510_INT_FPGA_ACK (OMAP_FPGA_IRQ_BASE + 1) -#define OMAP1510_INT_FPGA2 (OMAP_FPGA_IRQ_BASE + 2) -#define OMAP1510_INT_FPGA3 (OMAP_FPGA_IRQ_BASE + 3) -#define OMAP1510_INT_FPGA4 (OMAP_FPGA_IRQ_BASE + 4) -#define OMAP1510_INT_FPGA5 (OMAP_FPGA_IRQ_BASE + 5) -#define OMAP1510_INT_FPGA6 (OMAP_FPGA_IRQ_BASE + 6) -#define OMAP1510_INT_FPGA7 (OMAP_FPGA_IRQ_BASE + 7) -#define OMAP1510_INT_FPGA8 (OMAP_FPGA_IRQ_BASE + 8) -#define OMAP1510_INT_FPGA9 (OMAP_FPGA_IRQ_BASE + 9) -#define OMAP1510_INT_FPGA10 (OMAP_FPGA_IRQ_BASE + 10) -#define OMAP1510_INT_FPGA11 (OMAP_FPGA_IRQ_BASE + 11) -#define OMAP1510_INT_FPGA12 (OMAP_FPGA_IRQ_BASE + 12) -#define OMAP1510_INT_ETHER (OMAP_FPGA_IRQ_BASE + 13) -#define OMAP1510_INT_FPGAUART1 (OMAP_FPGA_IRQ_BASE + 14) -#define OMAP1510_INT_FPGAUART2 (OMAP_FPGA_IRQ_BASE + 15) -#define OMAP1510_INT_FPGA_TS (OMAP_FPGA_IRQ_BASE + 16) -#define OMAP1510_INT_FPGA17 (OMAP_FPGA_IRQ_BASE + 17) -#define OMAP1510_INT_FPGA_CAM (OMAP_FPGA_IRQ_BASE + 18) -#define OMAP1510_INT_FPGA_RTC_A (OMAP_FPGA_IRQ_BASE + 19) -#define OMAP1510_INT_FPGA_RTC_B (OMAP_FPGA_IRQ_BASE + 20) -#define OMAP1510_INT_FPGA_CD (OMAP_FPGA_IRQ_BASE + 21) -#define OMAP1510_INT_FPGA22 (OMAP_FPGA_IRQ_BASE + 22) -#define OMAP1510_INT_FPGA23 (OMAP_FPGA_IRQ_BASE + 23) - -#endif diff --git a/arch/arm/plat-omap/include/mach/gpio-switch.h b/arch/arm/plat-omap/include/mach/gpio-switch.h deleted file mode 100644 index 10da0e07c0c..00000000000 --- a/arch/arm/plat-omap/include/mach/gpio-switch.h +++ /dev/null @@ -1,54 +0,0 @@ -/* - * GPIO switch definitions - * - * Copyright (C) 2006 Nokia Corporation - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef __ASM_ARCH_OMAP_GPIO_SWITCH_H -#define __ASM_ARCH_OMAP_GPIO_SWITCH_H - -#include <linux/types.h> - -/* Cover: - * high -> closed - * low -> open - * Connection: - * high -> connected - * low -> disconnected - * Activity: - * high -> active - * low -> inactive - * - */ -#define OMAP_GPIO_SWITCH_TYPE_COVER 0x0000 -#define OMAP_GPIO_SWITCH_TYPE_CONNECTION 0x0001 -#define OMAP_GPIO_SWITCH_TYPE_ACTIVITY 0x0002 -#define OMAP_GPIO_SWITCH_FLAG_INVERTED 0x0001 -#define OMAP_GPIO_SWITCH_FLAG_OUTPUT 0x0002 - -struct omap_gpio_switch { - const char *name; - s16 gpio; - unsigned flags:4; - unsigned type:4; - - /* Time in ms to debounce when transitioning from - * inactive state to active state. */ - u16 debounce_rising; - /* Same for transition from active to inactive state. */ - u16 debounce_falling; - - /* notify board-specific code about state changes */ - void (* notify)(void *data, int state); - void *notify_data; -}; - -/* Call at init time only */ -extern void omap_register_gpio_switches(const struct omap_gpio_switch *tbl, - int count); - -#endif diff --git a/arch/arm/plat-omap/include/mach/gpio.h b/arch/arm/plat-omap/include/mach/gpio.h deleted file mode 100644 index 633ff688b92..00000000000 --- a/arch/arm/plat-omap/include/mach/gpio.h +++ /dev/null @@ -1,128 +0,0 @@ -/* - * arch/arm/plat-omap/include/mach/gpio.h - * - * OMAP GPIO handling defines and functions - * - * Copyright (C) 2003-2005 Nokia Corporation - * - * Written by Juha Yrjölä <juha.yrjola@nokia.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - * - */ - -#ifndef __ASM_ARCH_OMAP_GPIO_H -#define __ASM_ARCH_OMAP_GPIO_H - -#include <linux/io.h> -#include <mach/irqs.h> - -#define OMAP1_MPUIO_BASE 0xfffb5000 - -#if (defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)) - -#define OMAP_MPUIO_INPUT_LATCH 0x00 -#define OMAP_MPUIO_OUTPUT 0x02 -#define OMAP_MPUIO_IO_CNTL 0x04 -#define OMAP_MPUIO_KBR_LATCH 0x08 -#define OMAP_MPUIO_KBC 0x0a -#define OMAP_MPUIO_GPIO_EVENT_MODE 0x0c -#define OMAP_MPUIO_GPIO_INT_EDGE 0x0e -#define OMAP_MPUIO_KBD_INT 0x10 -#define OMAP_MPUIO_GPIO_INT 0x12 -#define OMAP_MPUIO_KBD_MASKIT 0x14 -#define OMAP_MPUIO_GPIO_MASKIT 0x16 -#define OMAP_MPUIO_GPIO_DEBOUNCING 0x18 -#define OMAP_MPUIO_LATCH 0x1a -#else -#define OMAP_MPUIO_INPUT_LATCH 0x00 -#define OMAP_MPUIO_OUTPUT 0x04 -#define OMAP_MPUIO_IO_CNTL 0x08 -#define OMAP_MPUIO_KBR_LATCH 0x10 -#define OMAP_MPUIO_KBC 0x14 -#define OMAP_MPUIO_GPIO_EVENT_MODE 0x18 -#define OMAP_MPUIO_GPIO_INT_EDGE 0x1c -#define OMAP_MPUIO_KBD_INT 0x20 -#define OMAP_MPUIO_GPIO_INT 0x24 -#define OMAP_MPUIO_KBD_MASKIT 0x28 -#define OMAP_MPUIO_GPIO_MASKIT 0x2c -#define OMAP_MPUIO_GPIO_DEBOUNCING 0x30 -#define OMAP_MPUIO_LATCH 0x34 -#endif - -#define OMAP34XX_NR_GPIOS 6 - -#define OMAP_MPUIO(nr) (OMAP_MAX_GPIO_LINES + (nr)) -#define OMAP_GPIO_IS_MPUIO(nr) ((nr) >= OMAP_MAX_GPIO_LINES) - -#define OMAP_GPIO_IRQ(nr) (OMAP_GPIO_IS_MPUIO(nr) ? \ - IH_MPUIO_BASE + ((nr) & 0x0f) : \ - IH_GPIO_BASE + (nr)) - -extern int omap_gpio_init(void); /* Call from board init only */ -extern void omap2_gpio_prepare_for_retention(void); -extern void omap2_gpio_resume_after_retention(void); -extern void omap_set_gpio_debounce(int gpio, int enable); -extern void omap_set_gpio_debounce_time(int gpio, int enable); - -/*-------------------------------------------------------------------------*/ - -/* Wrappers for "new style" GPIO calls, using the new infrastructure - * which lets us plug in FPGA, I2C, and other implementations. - * * - * The original OMAP-specfic calls should eventually be removed. - */ - -#include <linux/errno.h> -#include <asm-generic/gpio.h> - -static inline int gpio_get_value(unsigned gpio) -{ - return __gpio_get_value(gpio); -} - -static inline void gpio_set_value(unsigned gpio, int value) -{ - __gpio_set_value(gpio, value); -} - -static inline int gpio_cansleep(unsigned gpio) -{ - return __gpio_cansleep(gpio); -} - -static inline int gpio_to_irq(unsigned gpio) -{ - return __gpio_to_irq(gpio); -} - -static inline int irq_to_gpio(unsigned irq) -{ - int tmp; - - /* omap1 SOC mpuio */ - if (cpu_class_is_omap1() && (irq < (IH_MPUIO_BASE + 16))) - return (irq - IH_MPUIO_BASE) + OMAP_MAX_GPIO_LINES; - - /* SOC gpio */ - tmp = irq - IH_GPIO_BASE; - if (tmp < OMAP_MAX_GPIO_LINES) - return tmp; - - /* we don't supply reverse mappings for non-SOC gpios */ - return -EIO; -} - -#endif diff --git a/arch/arm/plat-omap/include/mach/gpmc-smc91x.h b/arch/arm/plat-omap/include/mach/gpmc-smc91x.h deleted file mode 100644 index b64fbee4d56..00000000000 --- a/arch/arm/plat-omap/include/mach/gpmc-smc91x.h +++ /dev/null @@ -1,42 +0,0 @@ -/* - * arch/arm/plat-omap/include/mach/gpmc-smc91x.h - * - * Copyright (C) 2009 Nokia Corporation - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef __ASM_ARCH_OMAP_GPMC_SMC91X_H__ - -#define GPMC_TIMINGS_SMC91C96 (1 << 4) -#define GPMC_MUX_ADD_DATA (1 << 5) /* GPMC_CONFIG1_MUXADDDATA */ -#define GPMC_READ_MON (1 << 6) /* GPMC_CONFIG1_WAIT_READ_MON */ -#define GPMC_WRITE_MON (1 << 7) /* GPMC_CONFIG1_WAIT_WRITE_MON */ - -struct omap_smc91x_platform_data { - int cs; - int gpio_irq; - int gpio_pwrdwn; - int gpio_reset; - int wait_pin; /* Optional GPMC_CONFIG1_WAITPINSELECT */ - u32 flags; - int (*retime)(void); -}; - -#if defined(CONFIG_SMC91X) || \ - defined(CONFIG_SMC91X_MODULE) - -extern void gpmc_smc91x_init(struct omap_smc91x_platform_data *d); - -#else - -#define board_smc91x_data NULL - -static inline void gpmc_smc91x_init(struct omap_smc91x_platform_data *d) -{ -} - -#endif -#endif diff --git a/arch/arm/plat-omap/include/mach/gpmc.h b/arch/arm/plat-omap/include/mach/gpmc.h deleted file mode 100644 index 9c99cda77ba..00000000000 --- a/arch/arm/plat-omap/include/mach/gpmc.h +++ /dev/null @@ -1,112 +0,0 @@ -/* - * General-Purpose Memory Controller for OMAP2 - * - * Copyright (C) 2005-2006 Nokia Corporation - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef __OMAP2_GPMC_H -#define __OMAP2_GPMC_H - -/* Maximum Number of Chip Selects */ -#define GPMC_CS_NUM 8 - -#define GPMC_CS_CONFIG1 0x00 -#define GPMC_CS_CONFIG2 0x04 -#define GPMC_CS_CONFIG3 0x08 -#define GPMC_CS_CONFIG4 0x0c -#define GPMC_CS_CONFIG5 0x10 -#define GPMC_CS_CONFIG6 0x14 -#define GPMC_CS_CONFIG7 0x18 -#define GPMC_CS_NAND_COMMAND 0x1c -#define GPMC_CS_NAND_ADDRESS 0x20 -#define GPMC_CS_NAND_DATA 0x24 - -#define GPMC_CONFIG 0x50 -#define GPMC_STATUS 0x54 - -#define GPMC_CONFIG1_WRAPBURST_SUPP (1 << 31) -#define GPMC_CONFIG1_READMULTIPLE_SUPP (1 << 30) -#define GPMC_CONFIG1_READTYPE_ASYNC (0 << 29) -#define GPMC_CONFIG1_READTYPE_SYNC (1 << 29) -#define GPMC_CONFIG1_WRITEMULTIPLE_SUPP (1 << 28) -#define GPMC_CONFIG1_WRITETYPE_ASYNC (0 << 27) -#define GPMC_CONFIG1_WRITETYPE_SYNC (1 << 27) -#define GPMC_CONFIG1_CLKACTIVATIONTIME(val) ((val & 3) << 25) -#define GPMC_CONFIG1_PAGE_LEN(val) ((val & 3) << 23) -#define GPMC_CONFIG1_WAIT_READ_MON (1 << 22) -#define GPMC_CONFIG1_WAIT_WRITE_MON (1 << 21) -#define GPMC_CONFIG1_WAIT_MON_IIME(val) ((val & 3) << 18) -#define GPMC_CONFIG1_WAIT_PIN_SEL(val) ((val & 3) << 16) -#define GPMC_CONFIG1_DEVICESIZE(val) ((val & 3) << 12) -#define GPMC_CONFIG1_DEVICESIZE_16 GPMC_CONFIG1_DEVICESIZE(1) -#define GPMC_CONFIG1_DEVICETYPE(val) ((val & 3) << 10) -#define GPMC_CONFIG1_DEVICETYPE_NOR GPMC_CONFIG1_DEVICETYPE(0) -#define GPMC_CONFIG1_DEVICETYPE_NAND GPMC_CONFIG1_DEVICETYPE(1) -#define GPMC_CONFIG1_MUXADDDATA (1 << 9) -#define GPMC_CONFIG1_TIME_PARA_GRAN (1 << 4) -#define GPMC_CONFIG1_FCLK_DIV(val) (val & 3) -#define GPMC_CONFIG1_FCLK_DIV2 (GPMC_CONFIG1_FCLK_DIV(1)) -#define GPMC_CONFIG1_FCLK_DIV3 (GPMC_CONFIG1_FCLK_DIV(2)) -#define GPMC_CONFIG1_FCLK_DIV4 (GPMC_CONFIG1_FCLK_DIV(3)) - -/* - * Note that all values in this struct are in nanoseconds, while - * the register values are in gpmc_fck cycles. - */ -struct gpmc_timings { - /* Minimum clock period for synchronous mode */ - u16 sync_clk; - - /* Chip-select signal timings corresponding to GPMC_CS_CONFIG2 */ - u16 cs_on; /* Assertion time */ - u16 cs_rd_off; /* Read deassertion time */ - u16 cs_wr_off; /* Write deassertion time */ - - /* ADV signal timings corresponding to GPMC_CONFIG3 */ - u16 adv_on; /* Assertion time */ - u16 adv_rd_off; /* Read deassertion time */ - u16 adv_wr_off; /* Write deassertion time */ - - /* WE signals timings corresponding to GPMC_CONFIG4 */ - u16 we_on; /* WE assertion time */ - u16 we_off; /* WE deassertion time */ - - /* OE signals timings corresponding to GPMC_CONFIG4 */ - u16 oe_on; /* OE assertion time */ - u16 oe_off; /* OE deassertion time */ - - /* Access time and cycle time timings corresponding to GPMC_CONFIG5 */ - u16 page_burst_access; /* Multiple access word delay */ - u16 access; /* Start-cycle to first data valid delay */ - u16 rd_cycle; /* Total read cycle time */ - u16 wr_cycle; /* Total write cycle time */ - - /* The following are only on OMAP3430 */ - u16 wr_access; /* WRACCESSTIME */ - u16 wr_data_mux_bus; /* WRDATAONADMUXBUS */ -}; - -extern unsigned int gpmc_ns_to_ticks(unsigned int time_ns); -extern unsigned int gpmc_ticks_to_ns(unsigned int ticks); -extern unsigned int gpmc_round_ns_to_ticks(unsigned int time_ns); -extern unsigned long gpmc_get_fclk_period(void); - -extern void gpmc_cs_write_reg(int cs, int idx, u32 val); -extern u32 gpmc_cs_read_reg(int cs, int idx); -extern int gpmc_cs_calc_divider(int cs, unsigned int sync_clk); -extern int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t); -extern int gpmc_cs_request(int cs, unsigned long size, unsigned long *base); -extern void gpmc_cs_free(int cs); -extern int gpmc_cs_set_reserved(int cs, int reserved); -extern int gpmc_cs_reserved(int cs); -extern int gpmc_prefetch_enable(int cs, int dma_mode, - unsigned int u32_count, int is_write); -extern void gpmc_prefetch_reset(void); -extern int gpmc_prefetch_status(void); -extern void __init gpmc_init(void); - -#endif diff --git a/arch/arm/plat-omap/include/mach/hardware.h b/arch/arm/plat-omap/include/mach/hardware.h deleted file mode 100644 index 26c1fbff08a..00000000000 --- a/arch/arm/plat-omap/include/mach/hardware.h +++ /dev/null @@ -1,290 +0,0 @@ -/* - * arch/arm/plat-omap/include/mach/hardware.h - * - * Hardware definitions for TI OMAP processors and boards - * - * NOTE: Please put device driver specific defines into a separate header - * file for each driver. - * - * Copyright (C) 2001 RidgeRun, Inc. - * Author: RidgeRun, Inc. Greg Lonnon <glonnon@ridgerun.com> - * - * Reorganized for Linux-2.6 by Tony Lindgren <tony@atomide.com> - * and Dirk Behme <dirk.behme@de.bosch.com> - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -#ifndef __ASM_ARCH_OMAP_HARDWARE_H -#define __ASM_ARCH_OMAP_HARDWARE_H - -#include <asm/sizes.h> -#ifndef __ASSEMBLER__ -#include <asm/types.h> -#include <mach/cpu.h> -#endif -#include <mach/serial.h> - -/* - * --------------------------------------------------------------------------- - * Common definitions for all OMAP processors - * NOTE: Put all processor or board specific parts to the special header - * files. - * --------------------------------------------------------------------------- - */ - -/* - * ---------------------------------------------------------------------------- - * Timers - * ---------------------------------------------------------------------------- - */ -#define OMAP_MPU_TIMER1_BASE (0xfffec500) -#define OMAP_MPU_TIMER2_BASE (0xfffec600) -#define OMAP_MPU_TIMER3_BASE (0xfffec700) -#define MPU_TIMER_FREE (1 << 6) -#define MPU_TIMER_CLOCK_ENABLE (1 << 5) -#define MPU_TIMER_AR (1 << 1) -#define MPU_TIMER_ST (1 << 0) - -/* - * ---------------------------------------------------------------------------- - * Clocks - * ---------------------------------------------------------------------------- - */ -#define CLKGEN_REG_BASE (0xfffece00) -#define ARM_CKCTL (CLKGEN_REG_BASE + 0x0) -#define ARM_IDLECT1 (CLKGEN_REG_BASE + 0x4) -#define ARM_IDLECT2 (CLKGEN_REG_BASE + 0x8) -#define ARM_EWUPCT (CLKGEN_REG_BASE + 0xC) -#define ARM_RSTCT1 (CLKGEN_REG_BASE + 0x10) -#define ARM_RSTCT2 (CLKGEN_REG_BASE + 0x14) -#define ARM_SYSST (CLKGEN_REG_BASE + 0x18) -#define ARM_IDLECT3 (CLKGEN_REG_BASE + 0x24) - -#define CK_RATEF 1 -#define CK_IDLEF 2 -#define CK_ENABLEF 4 -#define CK_SELECTF 8 -#define SETARM_IDLE_SHIFT - -/* DPLL control registers */ -#define DPLL_CTL (0xfffecf00) - -/* DSP clock control. Must use __raw_readw() and __raw_writew() with these */ -#define DSP_CONFIG_REG_BASE IOMEM(0xe1008000) -#define DSP_CKCTL (DSP_CONFIG_REG_BASE + 0x0) -#define DSP_IDLECT1 (DSP_CONFIG_REG_BASE + 0x4) -#define DSP_IDLECT2 (DSP_CONFIG_REG_BASE + 0x8) -#define DSP_RSTCT2 (DSP_CONFIG_REG_BASE + 0x14) - -/* - * --------------------------------------------------------------------------- - * UPLD - * --------------------------------------------------------------------------- - */ -#define ULPD_REG_BASE (0xfffe0800) -#define ULPD_IT_STATUS (ULPD_REG_BASE + 0x14) -#define ULPD_SETUP_ANALOG_CELL_3 (ULPD_REG_BASE + 0x24) -#define ULPD_CLOCK_CTRL (ULPD_REG_BASE + 0x30) -# define DIS_USB_PVCI_CLK (1 << 5) /* no USB/FAC synch */ -# define USB_MCLK_EN (1 << 4) /* enable W4_USB_CLKO */ -#define ULPD_SOFT_REQ (ULPD_REG_BASE + 0x34) -# define SOFT_UDC_REQ (1 << 4) -# define SOFT_USB_CLK_REQ (1 << 3) -# define SOFT_DPLL_REQ (1 << 0) -#define ULPD_DPLL_CTRL (ULPD_REG_BASE + 0x3c) -#define ULPD_STATUS_REQ (ULPD_REG_BASE + 0x40) -#define ULPD_APLL_CTRL (ULPD_REG_BASE + 0x4c) -#define ULPD_POWER_CTRL (ULPD_REG_BASE + 0x50) -#define ULPD_SOFT_DISABLE_REQ_REG (ULPD_REG_BASE + 0x68) -# define DIS_MMC2_DPLL_REQ (1 << 11) -# define DIS_MMC1_DPLL_REQ (1 << 10) -# define DIS_UART3_DPLL_REQ (1 << 9) -# define DIS_UART2_DPLL_REQ (1 << 8) -# define DIS_UART1_DPLL_REQ (1 << 7) -# define DIS_USB_HOST_DPLL_REQ (1 << 6) -#define ULPD_SDW_CLK_DIV_CTRL_SEL (ULPD_REG_BASE + 0x74) -#define ULPD_CAM_CLK_CTRL (ULPD_REG_BASE + 0x7c) - -/* - * --------------------------------------------------------------------------- - * Watchdog timer - * --------------------------------------------------------------------------- - */ - -/* Watchdog timer within the OMAP3.2 gigacell */ -#define OMAP_MPU_WATCHDOG_BASE (0xfffec800) -#define OMAP_WDT_TIMER (OMAP_MPU_WATCHDOG_BASE + 0x0) -#define OMAP_WDT_LOAD_TIM (OMAP_MPU_WATCHDOG_BASE + 0x4) -#define OMAP_WDT_READ_TIM (OMAP_MPU_WATCHDOG_BASE + 0x4) -#define OMAP_WDT_TIMER_MODE (OMAP_MPU_WATCHDOG_BASE + 0x8) - -/* - * --------------------------------------------------------------------------- - * Interrupts - * --------------------------------------------------------------------------- - */ -#ifdef CONFIG_ARCH_OMAP1 - -/* - * XXX: These probably want to be moved to arch/arm/mach-omap/omap1/irq.c - * or something similar.. -- PFM. - */ - -#define OMAP_IH1_BASE 0xfffecb00 -#define OMAP_IH2_BASE 0xfffe0000 - -#define OMAP_IH1_ITR (OMAP_IH1_BASE + 0x00) -#define OMAP_IH1_MIR (OMAP_IH1_BASE + 0x04) -#define OMAP_IH1_SIR_IRQ (OMAP_IH1_BASE + 0x10) -#define OMAP_IH1_SIR_FIQ (OMAP_IH1_BASE + 0x14) -#define OMAP_IH1_CONTROL (OMAP_IH1_BASE + 0x18) -#define OMAP_IH1_ILR0 (OMAP_IH1_BASE + 0x1c) -#define OMAP_IH1_ISR (OMAP_IH1_BASE + 0x9c) - -#define OMAP_IH2_ITR (OMAP_IH2_BASE + 0x00) -#define OMAP_IH2_MIR (OMAP_IH2_BASE + 0x04) -#define OMAP_IH2_SIR_IRQ (OMAP_IH2_BASE + 0x10) -#define OMAP_IH2_SIR_FIQ (OMAP_IH2_BASE + 0x14) -#define OMAP_IH2_CONTROL (OMAP_IH2_BASE + 0x18) -#define OMAP_IH2_ILR0 (OMAP_IH2_BASE + 0x1c) -#define OMAP_IH2_ISR (OMAP_IH2_BASE + 0x9c) - -#define IRQ_ITR_REG_OFFSET 0x00 -#define IRQ_MIR_REG_OFFSET 0x04 -#define IRQ_SIR_IRQ_REG_OFFSET 0x10 -#define IRQ_SIR_FIQ_REG_OFFSET 0x14 -#define IRQ_CONTROL_REG_OFFSET 0x18 -#define IRQ_ISR_REG_OFFSET 0x9c -#define IRQ_ILR0_REG_OFFSET 0x1c -#define IRQ_GMR_REG_OFFSET 0xa0 - -#endif - -/* - * ---------------------------------------------------------------------------- - * System control registers - * ---------------------------------------------------------------------------- - */ -#define MOD_CONF_CTRL_0 0xfffe1080 -#define MOD_CONF_CTRL_1 0xfffe1110 - -/* - * ---------------------------------------------------------------------------- - * Pin multiplexing registers - * ---------------------------------------------------------------------------- - */ -#define FUNC_MUX_CTRL_0 0xfffe1000 -#define FUNC_MUX_CTRL_1 0xfffe1004 -#define FUNC_MUX_CTRL_2 0xfffe1008 -#define COMP_MODE_CTRL_0 0xfffe100c -#define FUNC_MUX_CTRL_3 0xfffe1010 -#define FUNC_MUX_CTRL_4 0xfffe1014 -#define FUNC_MUX_CTRL_5 0xfffe1018 -#define FUNC_MUX_CTRL_6 0xfffe101C -#define FUNC_MUX_CTRL_7 0xfffe1020 -#define FUNC_MUX_CTRL_8 0xfffe1024 -#define FUNC_MUX_CTRL_9 0xfffe1028 -#define FUNC_MUX_CTRL_A 0xfffe102C -#define FUNC_MUX_CTRL_B 0xfffe1030 -#define FUNC_MUX_CTRL_C 0xfffe1034 -#define FUNC_MUX_CTRL_D 0xfffe1038 -#define PULL_DWN_CTRL_0 0xfffe1040 -#define PULL_DWN_CTRL_1 0xfffe1044 -#define PULL_DWN_CTRL_2 0xfffe1048 -#define PULL_DWN_CTRL_3 0xfffe104c -#define PULL_DWN_CTRL_4 0xfffe10ac - -/* OMAP-1610 specific multiplexing registers */ -#define FUNC_MUX_CTRL_E 0xfffe1090 -#define FUNC_MUX_CTRL_F 0xfffe1094 -#define FUNC_MUX_CTRL_10 0xfffe1098 -#define FUNC_MUX_CTRL_11 0xfffe109c -#define FUNC_MUX_CTRL_12 0xfffe10a0 -#define PU_PD_SEL_0 0xfffe10b4 -#define PU_PD_SEL_1 0xfffe10b8 -#define PU_PD_SEL_2 0xfffe10bc -#define PU_PD_SEL_3 0xfffe10c0 -#define PU_PD_SEL_4 0xfffe10c4 - -/* Timer32K for 1610 and 1710*/ -#define OMAP_TIMER32K_BASE 0xFFFBC400 - -/* - * --------------------------------------------------------------------------- - * TIPB bus interface - * --------------------------------------------------------------------------- - */ -#define TIPB_PUBLIC_CNTL_BASE 0xfffed300 -#define MPU_PUBLIC_TIPB_CNTL (TIPB_PUBLIC_CNTL_BASE + 0x8) -#define TIPB_PRIVATE_CNTL_BASE 0xfffeca00 -#define MPU_PRIVATE_TIPB_CNTL (TIPB_PRIVATE_CNTL_BASE + 0x8) - -/* - * ---------------------------------------------------------------------------- - * MPUI interface - * ---------------------------------------------------------------------------- - */ -#define MPUI_BASE (0xfffec900) -#define MPUI_CTRL (MPUI_BASE + 0x0) -#define MPUI_DEBUG_ADDR (MPUI_BASE + 0x4) -#define MPUI_DEBUG_DATA (MPUI_BASE + 0x8) -#define MPUI_DEBUG_FLAG (MPUI_BASE + 0xc) -#define MPUI_STATUS_REG (MPUI_BASE + 0x10) -#define MPUI_DSP_STATUS (MPUI_BASE + 0x14) -#define MPUI_DSP_BOOT_CONFIG (MPUI_BASE + 0x18) -#define MPUI_DSP_API_CONFIG (MPUI_BASE + 0x1c) - -/* - * ---------------------------------------------------------------------------- - * LED Pulse Generator - * ---------------------------------------------------------------------------- - */ -#define OMAP_LPG1_BASE 0xfffbd000 -#define OMAP_LPG2_BASE 0xfffbd800 -#define OMAP_LPG1_LCR (OMAP_LPG1_BASE + 0x00) -#define OMAP_LPG1_PMR (OMAP_LPG1_BASE + 0x04) -#define OMAP_LPG2_LCR (OMAP_LPG2_BASE + 0x00) -#define OMAP_LPG2_PMR (OMAP_LPG2_BASE + 0x04) - -/* - * ---------------------------------------------------------------------------- - * Pulse-Width Light - * ---------------------------------------------------------------------------- - */ -#define OMAP_PWL_BASE 0xfffb5800 -#define OMAP_PWL_ENABLE (OMAP_PWL_BASE + 0x00) -#define OMAP_PWL_CLK_ENABLE (OMAP_PWL_BASE + 0x04) - -/* - * --------------------------------------------------------------------------- - * Processor specific defines - * --------------------------------------------------------------------------- - */ - -#include "omap730.h" -#include "omap1510.h" -#include "omap16xx.h" -#include "omap24xx.h" -#include "omap34xx.h" -#include "omap44xx.h" - -#endif /* __ASM_ARCH_OMAP_HARDWARE_H */ diff --git a/arch/arm/plat-omap/include/mach/hwa742.h b/arch/arm/plat-omap/include/mach/hwa742.h deleted file mode 100644 index 886248d32b4..00000000000 --- a/arch/arm/plat-omap/include/mach/hwa742.h +++ /dev/null @@ -1,8 +0,0 @@ -#ifndef _HWA742_H -#define _HWA742_H - -struct hwa742_platform_data { - unsigned te_connected:1; -}; - -#endif diff --git a/arch/arm/plat-omap/include/mach/io.h b/arch/arm/plat-omap/include/mach/io.h deleted file mode 100644 index 8d32df32b0b..00000000000 --- a/arch/arm/plat-omap/include/mach/io.h +++ /dev/null @@ -1,241 +0,0 @@ -/* - * arch/arm/plat-omap/include/mach/io.h - * - * IO definitions for TI OMAP processors and boards - * - * Copied from arch/arm/mach-sa1100/include/mach/io.h - * Copyright (C) 1997-1999 Russell King - * - * Copyright (C) 2009 Texas Instruments - * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - * - * Modifications: - * 06-12-1997 RMK Created. - * 07-04-1999 RMK Major cleanup - */ - -#ifndef __ASM_ARM_ARCH_IO_H -#define __ASM_ARM_ARCH_IO_H - -#include <mach/hardware.h> - -#define IO_SPACE_LIMIT 0xffffffff - -/* - * We don't actually have real ISA nor PCI buses, but there is so many - * drivers out there that might just work if we fake them... - */ -#define __io(a) __typesafe_io(a) -#define __mem_pci(a) (a) - -/* - * ---------------------------------------------------------------------------- - * I/O mapping - * ---------------------------------------------------------------------------- - */ - -#ifdef __ASSEMBLER__ -#define IOMEM(x) (x) -#else -#define IOMEM(x) ((void __force __iomem *)(x)) -#endif - -#define OMAP1_IO_OFFSET 0x01000000 /* Virtual IO = 0xfefb0000 */ -#define OMAP1_IO_ADDRESS(pa) IOMEM((pa) - OMAP1_IO_OFFSET) - -#define OMAP2_IO_OFFSET 0x90000000 -#define OMAP2_IO_ADDRESS(pa) IOMEM((pa) + OMAP2_IO_OFFSET) /* L3 and L4 */ - -/* - * ---------------------------------------------------------------------------- - * Omap1 specific IO mapping - * ---------------------------------------------------------------------------- - */ - -#define OMAP1_IO_PHYS 0xFFFB0000 -#define OMAP1_IO_SIZE 0x40000 -#define OMAP1_IO_VIRT (OMAP1_IO_PHYS - OMAP1_IO_OFFSET) - -/* - * ---------------------------------------------------------------------------- - * Omap2 specific IO mapping - * ---------------------------------------------------------------------------- - */ - -/* We map both L3 and L4 on OMAP2 */ -#define L3_24XX_PHYS L3_24XX_BASE /* 0x68000000 */ -#define L3_24XX_VIRT 0xf8000000 -#define L3_24XX_SIZE SZ_1M /* 44kB of 128MB used, want 1MB sect */ -#define L4_24XX_PHYS L4_24XX_BASE /* 0x48000000 */ -#define L4_24XX_VIRT 0xd8000000 -#define L4_24XX_SIZE SZ_1M /* 1MB of 128MB used, want 1MB sect */ - -#define L4_WK_243X_PHYS L4_WK_243X_BASE /* 0x49000000 */ -#define L4_WK_243X_VIRT 0xd9000000 -#define L4_WK_243X_SIZE SZ_1M -#define OMAP243X_GPMC_PHYS OMAP243X_GPMC_BASE /* 0x49000000 */ -#define OMAP243X_GPMC_VIRT 0xFE000000 -#define OMAP243X_GPMC_SIZE SZ_1M -#define OMAP243X_SDRC_PHYS OMAP243X_SDRC_BASE -#define OMAP243X_SDRC_VIRT 0xFD000000 -#define OMAP243X_SDRC_SIZE SZ_1M -#define OMAP243X_SMS_PHYS OMAP243X_SMS_BASE -#define OMAP243X_SMS_VIRT 0xFC000000 -#define OMAP243X_SMS_SIZE SZ_1M - -/* DSP */ -#define DSP_MEM_24XX_PHYS OMAP2420_DSP_MEM_BASE /* 0x58000000 */ -#define DSP_MEM_24XX_VIRT 0xe0000000 -#define DSP_MEM_24XX_SIZE 0x28000 -#define DSP_IPI_24XX_PHYS OMAP2420_DSP_IPI_BASE /* 0x59000000 */ -#define DSP_IPI_24XX_VIRT 0xe1000000 -#define DSP_IPI_24XX_SIZE SZ_4K -#define DSP_MMU_24XX_PHYS OMAP2420_DSP_MMU_BASE /* 0x5a000000 */ -#define DSP_MMU_24XX_VIRT 0xe2000000 -#define DSP_MMU_24XX_SIZE SZ_4K - -/* - * ---------------------------------------------------------------------------- - * Omap3 specific IO mapping - * ---------------------------------------------------------------------------- - */ - -/* We map both L3 and L4 on OMAP3 */ -#define L3_34XX_PHYS L3_34XX_BASE /* 0x68000000 */ -#define L3_34XX_VIRT 0xf8000000 -#define L3_34XX_SIZE SZ_1M /* 44kB of 128MB used, want 1MB sect */ - -#define L4_34XX_PHYS L4_34XX_BASE /* 0x48000000 */ -#define L4_34XX_VIRT 0xd8000000 -#define L4_34XX_SIZE SZ_4M /* 1MB of 128MB used, want 1MB sect */ - -/* - * Need to look at the Size 4M for L4. - * VPOM3430 was not working for Int controller - */ - -#define L4_WK_34XX_PHYS L4_WK_34XX_BASE /* 0x48300000 */ -#define L4_WK_34XX_VIRT 0xd8300000 -#define L4_WK_34XX_SIZE SZ_1M - -#define L4_PER_34XX_PHYS L4_PER_34XX_BASE /* 0x49000000 */ -#define L4_PER_34XX_VIRT 0xd9000000 -#define L4_PER_34XX_SIZE SZ_1M - -#define L4_EMU_34XX_PHYS L4_EMU_34XX_BASE /* 0x54000000 */ -#define L4_EMU_34XX_VIRT 0xe4000000 -#define L4_EMU_34XX_SIZE SZ_64M - -#define OMAP34XX_GPMC_PHYS OMAP34XX_GPMC_BASE /* 0x6E000000 */ -#define OMAP34XX_GPMC_VIRT 0xFE000000 -#define OMAP34XX_GPMC_SIZE SZ_1M - -#define OMAP343X_SMS_PHYS OMAP343X_SMS_BASE /* 0x6C000000 */ -#define OMAP343X_SMS_VIRT 0xFC000000 -#define OMAP343X_SMS_SIZE SZ_1M - -#define OMAP343X_SDRC_PHYS OMAP343X_SDRC_BASE /* 0x6D000000 */ -#define OMAP343X_SDRC_VIRT 0xFD000000 -#define OMAP343X_SDRC_SIZE SZ_1M - -/* DSP */ -#define DSP_MEM_34XX_PHYS OMAP34XX_DSP_MEM_BASE /* 0x58000000 */ -#define DSP_MEM_34XX_VIRT 0xe0000000 -#define DSP_MEM_34XX_SIZE 0x28000 -#define DSP_IPI_34XX_PHYS OMAP34XX_DSP_IPI_BASE /* 0x59000000 */ -#define DSP_IPI_34XX_VIRT 0xe1000000 -#define DSP_IPI_34XX_SIZE SZ_4K -#define DSP_MMU_34XX_PHYS OMAP34XX_DSP_MMU_BASE /* 0x5a000000 */ -#define DSP_MMU_34XX_VIRT 0xe2000000 -#define DSP_MMU_34XX_SIZE SZ_4K - -/* - * ---------------------------------------------------------------------------- - * Omap4 specific IO mapping - * ---------------------------------------------------------------------------- - */ - -/* We map both L3 and L4 on OMAP4 */ -#define L3_44XX_PHYS L3_44XX_BASE -#define L3_44XX_VIRT 0xd4000000 -#define L3_44XX_SIZE SZ_1M - -#define L4_44XX_PHYS L4_44XX_BASE -#define L4_44XX_VIRT 0xda000000 -#define L4_44XX_SIZE SZ_4M - - -#define L4_WK_44XX_PHYS L4_WK_44XX_BASE -#define L4_WK_44XX_VIRT 0xda300000 -#define L4_WK_44XX_SIZE SZ_1M - -#define L4_PER_44XX_PHYS L4_PER_44XX_BASE -#define L4_PER_44XX_VIRT 0xd8000000 -#define L4_PER_44XX_SIZE SZ_4M - -#define L4_EMU_44XX_PHYS L4_EMU_44XX_BASE -#define L4_EMU_44XX_VIRT 0xe4000000 -#define L4_EMU_44XX_SIZE SZ_64M - -#define OMAP44XX_GPMC_PHYS OMAP44XX_GPMC_BASE -#define OMAP44XX_GPMC_VIRT 0xe0000000 -#define OMAP44XX_GPMC_SIZE SZ_1M - - -/* - * ---------------------------------------------------------------------------- - * Omap specific register access - * ---------------------------------------------------------------------------- - */ - -#ifndef __ASSEMBLER__ - -/* - * NOTE: Please use ioremap + __raw_read/write where possible instead of these - */ - -extern u8 omap_readb(u32 pa); -extern u16 omap_readw(u32 pa); -extern u32 omap_readl(u32 pa); -extern void omap_writeb(u8 v, u32 pa); -extern void omap_writew(u16 v, u32 pa); -extern void omap_writel(u32 v, u32 pa); - -struct omap_sdrc_params; - -extern void omap1_map_common_io(void); -extern void omap1_init_common_hw(void); - -extern void omap2_map_common_io(void); -extern void omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0, - struct omap_sdrc_params *sdrc_cs1); - -#define __arch_ioremap(p,s,t) omap_ioremap(p,s,t) -#define __arch_iounmap(v) omap_iounmap(v) - -void __iomem *omap_ioremap(unsigned long phys, size_t size, unsigned int type); -void omap_iounmap(volatile void __iomem *addr); - -#endif - -#endif diff --git a/arch/arm/plat-omap/include/mach/iommu.h b/arch/arm/plat-omap/include/mach/iommu.h deleted file mode 100644 index 46d41ac83db..00000000000 --- a/arch/arm/plat-omap/include/mach/iommu.h +++ /dev/null @@ -1,168 +0,0 @@ -/* - * omap iommu: main structures - * - * Copyright (C) 2008-2009 Nokia Corporation - * - * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef __MACH_IOMMU_H -#define __MACH_IOMMU_H - -struct iotlb_entry { - u32 da; - u32 pa; - u32 pgsz, prsvd, valid; - union { - u16 ap; - struct { - u32 endian, elsz, mixed; - }; - }; -}; - -struct iommu { - const char *name; - struct module *owner; - struct clk *clk; - void __iomem *regbase; - struct device *dev; - - unsigned int refcount; - struct mutex iommu_lock; /* global for this whole object */ - - /* - * We don't change iopgd for a situation like pgd for a task, - * but share it globally for each iommu. - */ - u32 *iopgd; - spinlock_t page_table_lock; /* protect iopgd */ - - int nr_tlb_entries; - - struct list_head mmap; - struct mutex mmap_lock; /* protect mmap */ - - int (*isr)(struct iommu *obj); - - void *ctx; /* iommu context: registres saved area */ -}; - -struct cr_regs { - union { - struct { - u16 cam_l; - u16 cam_h; - }; - u32 cam; - }; - union { - struct { - u16 ram_l; - u16 ram_h; - }; - u32 ram; - }; -}; - -struct iotlb_lock { - short base; - short vict; -}; - -/* architecture specific functions */ -struct iommu_functions { - unsigned long version; - - int (*enable)(struct iommu *obj); - void (*disable)(struct iommu *obj); - u32 (*fault_isr)(struct iommu *obj, u32 *ra); - - void (*tlb_read_cr)(struct iommu *obj, struct cr_regs *cr); - void (*tlb_load_cr)(struct iommu *obj, struct cr_regs *cr); - - struct cr_regs *(*alloc_cr)(struct iommu *obj, struct iotlb_entry *e); - int (*cr_valid)(struct cr_regs *cr); - u32 (*cr_to_virt)(struct cr_regs *cr); - void (*cr_to_e)(struct cr_regs *cr, struct iotlb_entry *e); - ssize_t (*dump_cr)(struct iommu *obj, struct cr_regs *cr, char *buf); - - u32 (*get_pte_attr)(struct iotlb_entry *e); - - void (*save_ctx)(struct iommu *obj); - void (*restore_ctx)(struct iommu *obj); - ssize_t (*dump_ctx)(struct iommu *obj, char *buf, ssize_t len); -}; - -struct iommu_platform_data { - const char *name; - const char *clk_name; - const int nr_tlb_entries; -}; - -#if defined(CONFIG_ARCH_OMAP1) -#error "iommu for this processor not implemented yet" -#else -#include <mach/iommu2.h> -#endif - -/* - * utilities for super page(16MB, 1MB, 64KB and 4KB) - */ - -#define iopgsz_max(bytes) \ - (((bytes) >= SZ_16M) ? SZ_16M : \ - ((bytes) >= SZ_1M) ? SZ_1M : \ - ((bytes) >= SZ_64K) ? SZ_64K : \ - ((bytes) >= SZ_4K) ? SZ_4K : 0) - -#define bytes_to_iopgsz(bytes) \ - (((bytes) == SZ_16M) ? MMU_CAM_PGSZ_16M : \ - ((bytes) == SZ_1M) ? MMU_CAM_PGSZ_1M : \ - ((bytes) == SZ_64K) ? MMU_CAM_PGSZ_64K : \ - ((bytes) == SZ_4K) ? MMU_CAM_PGSZ_4K : -1) - -#define iopgsz_to_bytes(iopgsz) \ - (((iopgsz) == MMU_CAM_PGSZ_16M) ? SZ_16M : \ - ((iopgsz) == MMU_CAM_PGSZ_1M) ? SZ_1M : \ - ((iopgsz) == MMU_CAM_PGSZ_64K) ? SZ_64K : \ - ((iopgsz) == MMU_CAM_PGSZ_4K) ? SZ_4K : 0) - -#define iopgsz_ok(bytes) (bytes_to_iopgsz(bytes) >= 0) - -/* - * global functions - */ -extern u32 iommu_arch_version(void); - -extern void iotlb_cr_to_e(struct cr_regs *cr, struct iotlb_entry *e); -extern u32 iotlb_cr_to_virt(struct cr_regs *cr); - -extern int load_iotlb_entry(struct iommu *obj, struct iotlb_entry *e); -extern void flush_iotlb_page(struct iommu *obj, u32 da); -extern void flush_iotlb_range(struct iommu *obj, u32 start, u32 end); -extern void flush_iotlb_all(struct iommu *obj); - -extern int iopgtable_store_entry(struct iommu *obj, struct iotlb_entry *e); -extern size_t iopgtable_clear_entry(struct iommu *obj, u32 iova); - -extern struct iommu *iommu_get(const char *name); -extern void iommu_put(struct iommu *obj); - -extern void iommu_save_ctx(struct iommu *obj); -extern void iommu_restore_ctx(struct iommu *obj); - -extern int install_iommu_arch(const struct iommu_functions *ops); -extern void uninstall_iommu_arch(const struct iommu_functions *ops); - -extern int foreach_iommu_device(void *data, - int (*fn)(struct device *, void *)); - -extern ssize_t iommu_dump_ctx(struct iommu *obj, char *buf, ssize_t len); -extern size_t dump_tlb_entries(struct iommu *obj, char *buf, ssize_t len); - -#endif /* __MACH_IOMMU_H */ diff --git a/arch/arm/plat-omap/include/mach/iommu2.h b/arch/arm/plat-omap/include/mach/iommu2.h deleted file mode 100644 index 10ad05f410e..00000000000 --- a/arch/arm/plat-omap/include/mach/iommu2.h +++ /dev/null @@ -1,96 +0,0 @@ -/* - * omap iommu: omap2 architecture specific definitions - * - * Copyright (C) 2008-2009 Nokia Corporation - * - * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef __MACH_IOMMU2_H -#define __MACH_IOMMU2_H - -#include <linux/io.h> - -/* - * MMU Register offsets - */ -#define MMU_REVISION 0x00 -#define MMU_SYSCONFIG 0x10 -#define MMU_SYSSTATUS 0x14 -#define MMU_IRQSTATUS 0x18 -#define MMU_IRQENABLE 0x1c -#define MMU_WALKING_ST 0x40 -#define MMU_CNTL 0x44 -#define MMU_FAULT_AD 0x48 -#define MMU_TTB 0x4c -#define MMU_LOCK 0x50 -#define MMU_LD_TLB 0x54 -#define MMU_CAM 0x58 -#define MMU_RAM 0x5c -#define MMU_GFLUSH 0x60 -#define MMU_FLUSH_ENTRY 0x64 -#define MMU_READ_CAM 0x68 -#define MMU_READ_RAM 0x6c -#define MMU_EMU_FAULT_AD 0x70 - -#define MMU_REG_SIZE 256 - -/* - * MMU Register bit definitions - */ -#define MMU_LOCK_BASE_SHIFT 10 -#define MMU_LOCK_BASE_MASK (0x1f << MMU_LOCK_BASE_SHIFT) -#define MMU_LOCK_BASE(x) \ - ((x & MMU_LOCK_BASE_MASK) >> MMU_LOCK_BASE_SHIFT) - -#define MMU_LOCK_VICT_SHIFT 4 -#define MMU_LOCK_VICT_MASK (0x1f << MMU_LOCK_VICT_SHIFT) -#define MMU_LOCK_VICT(x) \ - ((x & MMU_LOCK_VICT_MASK) >> MMU_LOCK_VICT_SHIFT) - -#define MMU_CAM_VATAG_SHIFT 12 -#define MMU_CAM_VATAG_MASK \ - ((~0UL >> MMU_CAM_VATAG_SHIFT) << MMU_CAM_VATAG_SHIFT) -#define MMU_CAM_P (1 << 3) -#define MMU_CAM_V (1 << 2) -#define MMU_CAM_PGSZ_MASK 3 -#define MMU_CAM_PGSZ_1M (0 << 0) -#define MMU_CAM_PGSZ_64K (1 << 0) -#define MMU_CAM_PGSZ_4K (2 << 0) -#define MMU_CAM_PGSZ_16M (3 << 0) - -#define MMU_RAM_PADDR_SHIFT 12 -#define MMU_RAM_PADDR_MASK \ - ((~0UL >> MMU_RAM_PADDR_SHIFT) << MMU_RAM_PADDR_SHIFT) -#define MMU_RAM_ENDIAN_SHIFT 9 -#define MMU_RAM_ENDIAN_MASK (1 << MMU_RAM_ENDIAN_SHIFT) -#define MMU_RAM_ENDIAN_BIG (1 << MMU_RAM_ENDIAN_SHIFT) -#define MMU_RAM_ENDIAN_LITTLE (0 << MMU_RAM_ENDIAN_SHIFT) -#define MMU_RAM_ELSZ_SHIFT 7 -#define MMU_RAM_ELSZ_MASK (3 << MMU_RAM_ELSZ_SHIFT) -#define MMU_RAM_ELSZ_8 (0 << MMU_RAM_ELSZ_SHIFT) -#define MMU_RAM_ELSZ_16 (1 << MMU_RAM_ELSZ_SHIFT) -#define MMU_RAM_ELSZ_32 (2 << MMU_RAM_ELSZ_SHIFT) -#define MMU_RAM_ELSZ_NONE (3 << MMU_RAM_ELSZ_SHIFT) -#define MMU_RAM_MIXED_SHIFT 6 -#define MMU_RAM_MIXED_MASK (1 << MMU_RAM_MIXED_SHIFT) -#define MMU_RAM_MIXED MMU_RAM_MIXED_MASK - -/* - * register accessors - */ -static inline u32 iommu_read_reg(struct iommu *obj, size_t offs) -{ - return __raw_readl(obj->regbase + offs); -} - -static inline void iommu_write_reg(struct iommu *obj, u32 val, size_t offs) -{ - __raw_writel(val, obj->regbase + offs); -} - -#endif /* __MACH_IOMMU2_H */ diff --git a/arch/arm/plat-omap/include/mach/iovmm.h b/arch/arm/plat-omap/include/mach/iovmm.h deleted file mode 100644 index bdc7ce5d7a4..00000000000 --- a/arch/arm/plat-omap/include/mach/iovmm.h +++ /dev/null @@ -1,94 +0,0 @@ -/* - * omap iommu: simple virtual address space management - * - * Copyright (C) 2008-2009 Nokia Corporation - * - * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef __IOMMU_MMAP_H -#define __IOMMU_MMAP_H - -struct iovm_struct { - struct iommu *iommu; /* iommu object which this belongs to */ - u32 da_start; /* area definition */ - u32 da_end; - u32 flags; /* IOVMF_: see below */ - struct list_head list; /* linked in ascending order */ - const struct sg_table *sgt; /* keep 'page' <-> 'da' mapping */ - void *va; /* mpu side mapped address */ -}; - -/* - * IOVMF_FLAGS: attribute for iommu virtual memory area(iovma) - * - * lower 16 bit is used for h/w and upper 16 bit is for s/w. - */ -#define IOVMF_SW_SHIFT 16 -#define IOVMF_HW_SIZE (1 << IOVMF_SW_SHIFT) -#define IOVMF_HW_MASK (IOVMF_HW_SIZE - 1) -#define IOVMF_SW_MASK (~IOVMF_HW_MASK)UL - -/* - * iovma: h/w flags derived from cam and ram attribute - */ -#define IOVMF_CAM_MASK (~((1 << 10) - 1)) -#define IOVMF_RAM_MASK (~IOVMF_CAM_MASK) - -#define IOVMF_PGSZ_MASK (3 << 0) -#define IOVMF_PGSZ_1M MMU_CAM_PGSZ_1M -#define IOVMF_PGSZ_64K MMU_CAM_PGSZ_64K -#define IOVMF_PGSZ_4K MMU_CAM_PGSZ_4K -#define IOVMF_PGSZ_16M MMU_CAM_PGSZ_16M - -#define IOVMF_ENDIAN_MASK (1 << 9) -#define IOVMF_ENDIAN_BIG MMU_RAM_ENDIAN_BIG -#define IOVMF_ENDIAN_LITTLE MMU_RAM_ENDIAN_LITTLE - -#define IOVMF_ELSZ_MASK (3 << 7) -#define IOVMF_ELSZ_8 MMU_RAM_ELSZ_8 -#define IOVMF_ELSZ_16 MMU_RAM_ELSZ_16 -#define IOVMF_ELSZ_32 MMU_RAM_ELSZ_32 -#define IOVMF_ELSZ_NONE MMU_RAM_ELSZ_NONE - -#define IOVMF_MIXED_MASK (1 << 6) -#define IOVMF_MIXED MMU_RAM_MIXED - -/* - * iovma: s/w flags, used for mapping and umapping internally. - */ -#define IOVMF_MMIO (1 << IOVMF_SW_SHIFT) -#define IOVMF_ALLOC (2 << IOVMF_SW_SHIFT) -#define IOVMF_ALLOC_MASK (3 << IOVMF_SW_SHIFT) - -/* "superpages" is supported just with physically linear pages */ -#define IOVMF_DISCONT (1 << (2 + IOVMF_SW_SHIFT)) -#define IOVMF_LINEAR (2 << (2 + IOVMF_SW_SHIFT)) -#define IOVMF_LINEAR_MASK (3 << (2 + IOVMF_SW_SHIFT)) - -#define IOVMF_DA_FIXED (1 << (4 + IOVMF_SW_SHIFT)) -#define IOVMF_DA_ANON (2 << (4 + IOVMF_SW_SHIFT)) -#define IOVMF_DA_MASK (3 << (4 + IOVMF_SW_SHIFT)) - - -extern struct iovm_struct *find_iovm_area(struct iommu *obj, u32 da); -extern u32 iommu_vmap(struct iommu *obj, u32 da, - const struct sg_table *sgt, u32 flags); -extern struct sg_table *iommu_vunmap(struct iommu *obj, u32 da); -extern u32 iommu_vmalloc(struct iommu *obj, u32 da, size_t bytes, - u32 flags); -extern void iommu_vfree(struct iommu *obj, const u32 da); -extern u32 iommu_kmap(struct iommu *obj, u32 da, u32 pa, size_t bytes, - u32 flags); -extern void iommu_kunmap(struct iommu *obj, u32 da); -extern u32 iommu_kmalloc(struct iommu *obj, u32 da, size_t bytes, - u32 flags); -extern void iommu_kfree(struct iommu *obj, u32 da); - -extern void *da_to_va(struct iommu *obj, u32 da); - -#endif /* __IOMMU_MMAP_H */ diff --git a/arch/arm/plat-omap/include/mach/irda.h b/arch/arm/plat-omap/include/mach/irda.h deleted file mode 100644 index 40f60339d1c..00000000000 --- a/arch/arm/plat-omap/include/mach/irda.h +++ /dev/null @@ -1,33 +0,0 @@ -/* - * arch/arm/plat-omap/include/mach/irda.h - * - * Copyright (C) 2005-2006 Komal Shah <komal_shah802003@yahoo.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#ifndef ASMARM_ARCH_IRDA_H -#define ASMARM_ARCH_IRDA_H - -/* board specific transceiver capabilities */ - -#define IR_SEL 1 /* Selects IrDA */ -#define IR_SIRMODE 2 -#define IR_FIRMODE 4 -#define IR_MIRMODE 8 - -struct omap_irda_config { - int transceiver_cap; - int (*transceiver_mode)(struct device *dev, int mode); - int (*select_irda)(struct device *dev, int state); - int rx_channel; - int tx_channel; - unsigned long dest_start; - unsigned long src_start; - int tx_trigger; - int rx_trigger; - int mode; -}; - -#endif diff --git a/arch/arm/plat-omap/include/mach/irqs.h b/arch/arm/plat-omap/include/mach/irqs.h deleted file mode 100644 index 28a165058b6..00000000000 --- a/arch/arm/plat-omap/include/mach/irqs.h +++ /dev/null @@ -1,568 +0,0 @@ -/* - * arch/arm/plat-omap/include/mach/irqs.h - * - * Copyright (C) Greg Lonnon 2001 - * Updated for OMAP-1610 by Tony Lindgren <tony@atomide.com> - * - * Copyright (C) 2009 Texas Instruments - * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - * - * NOTE: The interrupt vectors for the OMAP-1509, OMAP-1510, and OMAP-1610 - * are different. - */ - -#ifndef __ASM_ARCH_OMAP15XX_IRQS_H -#define __ASM_ARCH_OMAP15XX_IRQS_H - -/* - * IRQ numbers for interrupt handler 1 - * - * NOTE: See also the OMAP-1510 and 1610 specific IRQ numbers below - * - */ -#define INT_CAMERA 1 -#define INT_FIQ 3 -#define INT_RTDX 6 -#define INT_DSP_MMU_ABORT 7 -#define INT_HOST 8 -#define INT_ABORT 9 -#define INT_BRIDGE_PRIV 13 -#define INT_GPIO_BANK1 14 -#define INT_UART3 15 -#define INT_TIMER3 16 -#define INT_DMA_CH0_6 19 -#define INT_DMA_CH1_7 20 -#define INT_DMA_CH2_8 21 -#define INT_DMA_CH3 22 -#define INT_DMA_CH4 23 -#define INT_DMA_CH5 24 -#define INT_DMA_LCD 25 -#define INT_TIMER1 26 -#define INT_WD_TIMER 27 -#define INT_BRIDGE_PUB 28 -#define INT_TIMER2 30 -#define INT_LCD_CTRL 31 - -/* - * OMAP-1510 specific IRQ numbers for interrupt handler 1 - */ -#define INT_1510_IH2_IRQ 0 -#define INT_1510_RES2 2 -#define INT_1510_SPI_TX 4 -#define INT_1510_SPI_RX 5 -#define INT_1510_DSP_MAILBOX1 10 -#define INT_1510_DSP_MAILBOX2 11 -#define INT_1510_RES12 12 -#define INT_1510_LB_MMU 17 -#define INT_1510_RES18 18 -#define INT_1510_LOCAL_BUS 29 - -/* - * OMAP-1610 specific IRQ numbers for interrupt handler 1 - */ -#define INT_1610_IH2_IRQ 0 -#define INT_1610_IH2_FIQ 2 -#define INT_1610_McBSP2_TX 4 -#define INT_1610_McBSP2_RX 5 -#define INT_1610_DSP_MAILBOX1 10 -#define INT_1610_DSP_MAILBOX2 11 -#define INT_1610_LCD_LINE 12 -#define INT_1610_GPTIMER1 17 -#define INT_1610_GPTIMER2 18 -#define INT_1610_SSR_FIFO_0 29 - -/* - * OMAP-730 specific IRQ numbers for interrupt handler 1 - */ -#define INT_730_IH2_FIQ 0 -#define INT_730_IH2_IRQ 1 -#define INT_730_USB_NON_ISO 2 -#define INT_730_USB_ISO 3 -#define INT_730_ICR 4 -#define INT_730_EAC 5 -#define INT_730_GPIO_BANK1 6 -#define INT_730_GPIO_BANK2 7 -#define INT_730_GPIO_BANK3 8 -#define INT_730_McBSP2TX 10 -#define INT_730_McBSP2RX 11 -#define INT_730_McBSP2RX_OVF 12 -#define INT_730_LCD_LINE 14 -#define INT_730_GSM_PROTECT 15 -#define INT_730_TIMER3 16 -#define INT_730_GPIO_BANK5 17 -#define INT_730_GPIO_BANK6 18 -#define INT_730_SPGIO_WR 29 - -/* - * OMAP-850 specific IRQ numbers for interrupt handler 1 - */ -#define INT_850_IH2_FIQ 0 -#define INT_850_IH2_IRQ 1 -#define INT_850_USB_NON_ISO 2 -#define INT_850_USB_ISO 3 -#define INT_850_ICR 4 -#define INT_850_EAC 5 -#define INT_850_GPIO_BANK1 6 -#define INT_850_GPIO_BANK2 7 -#define INT_850_GPIO_BANK3 8 -#define INT_850_McBSP2TX 10 -#define INT_850_McBSP2RX 11 -#define INT_850_McBSP2RX_OVF 12 -#define INT_850_LCD_LINE 14 -#define INT_850_GSM_PROTECT 15 -#define INT_850_TIMER3 16 -#define INT_850_GPIO_BANK5 17 -#define INT_850_GPIO_BANK6 18 -#define INT_850_SPGIO_WR 29 - - -/* - * IRQ numbers for interrupt handler 2 - * - * NOTE: See also the OMAP-1510 and 1610 specific IRQ numbers below - */ -#define IH2_BASE 32 - -#define INT_KEYBOARD (1 + IH2_BASE) -#define INT_uWireTX (2 + IH2_BASE) -#define INT_uWireRX (3 + IH2_BASE) -#define INT_I2C (4 + IH2_BASE) -#define INT_MPUIO (5 + IH2_BASE) -#define INT_USB_HHC_1 (6 + IH2_BASE) -#define INT_McBSP3TX (10 + IH2_BASE) -#define INT_McBSP3RX (11 + IH2_BASE) -#define INT_McBSP1TX (12 + IH2_BASE) -#define INT_McBSP1RX (13 + IH2_BASE) -#define INT_UART1 (14 + IH2_BASE) -#define INT_UART2 (15 + IH2_BASE) -#define INT_BT_MCSI1TX (16 + IH2_BASE) -#define INT_BT_MCSI1RX (17 + IH2_BASE) -#define INT_SOSSI_MATCH (19 + IH2_BASE) -#define INT_USB_W2FC (20 + IH2_BASE) -#define INT_1WIRE (21 + IH2_BASE) -#define INT_OS_TIMER (22 + IH2_BASE) -#define INT_MMC (23 + IH2_BASE) -#define INT_GAUGE_32K (24 + IH2_BASE) -#define INT_RTC_TIMER (25 + IH2_BASE) -#define INT_RTC_ALARM (26 + IH2_BASE) -#define INT_MEM_STICK (27 + IH2_BASE) - -/* - * OMAP-1510 specific IRQ numbers for interrupt handler 2 - */ -#define INT_1510_DSP_MMU (28 + IH2_BASE) -#define INT_1510_COM_SPI_RO (31 + IH2_BASE) - -/* - * OMAP-1610 specific IRQ numbers for interrupt handler 2 - */ -#define INT_1610_FAC (0 + IH2_BASE) -#define INT_1610_USB_HHC_2 (7 + IH2_BASE) -#define INT_1610_USB_OTG (8 + IH2_BASE) -#define INT_1610_SoSSI (9 + IH2_BASE) -#define INT_1610_SoSSI_MATCH (19 + IH2_BASE) -#define INT_1610_DSP_MMU (28 + IH2_BASE) -#define INT_1610_McBSP2RX_OF (31 + IH2_BASE) -#define INT_1610_STI (32 + IH2_BASE) -#define INT_1610_STI_WAKEUP (33 + IH2_BASE) -#define INT_1610_GPTIMER3 (34 + IH2_BASE) -#define INT_1610_GPTIMER4 (35 + IH2_BASE) -#define INT_1610_GPTIMER5 (36 + IH2_BASE) -#define INT_1610_GPTIMER6 (37 + IH2_BASE) -#define INT_1610_GPTIMER7 (38 + IH2_BASE) -#define INT_1610_GPTIMER8 (39 + IH2_BASE) -#define INT_1610_GPIO_BANK2 (40 + IH2_BASE) -#define INT_1610_GPIO_BANK3 (41 + IH2_BASE) -#define INT_1610_MMC2 (42 + IH2_BASE) -#define INT_1610_CF (43 + IH2_BASE) -#define INT_1610_WAKE_UP_REQ (46 + IH2_BASE) -#define INT_1610_GPIO_BANK4 (48 + IH2_BASE) -#define INT_1610_SPI (49 + IH2_BASE) -#define INT_1610_DMA_CH6 (53 + IH2_BASE) -#define INT_1610_DMA_CH7 (54 + IH2_BASE) -#define INT_1610_DMA_CH8 (55 + IH2_BASE) -#define INT_1610_DMA_CH9 (56 + IH2_BASE) -#define INT_1610_DMA_CH10 (57 + IH2_BASE) -#define INT_1610_DMA_CH11 (58 + IH2_BASE) -#define INT_1610_DMA_CH12 (59 + IH2_BASE) -#define INT_1610_DMA_CH13 (60 + IH2_BASE) -#define INT_1610_DMA_CH14 (61 + IH2_BASE) -#define INT_1610_DMA_CH15 (62 + IH2_BASE) -#define INT_1610_NAND (63 + IH2_BASE) -#define INT_1610_SHA1MD5 (91 + IH2_BASE) - -/* - * OMAP-730 specific IRQ numbers for interrupt handler 2 - */ -#define INT_730_HW_ERRORS (0 + IH2_BASE) -#define INT_730_NFIQ_PWR_FAIL (1 + IH2_BASE) -#define INT_730_CFCD (2 + IH2_BASE) -#define INT_730_CFIREQ (3 + IH2_BASE) -#define INT_730_I2C (4 + IH2_BASE) -#define INT_730_PCC (5 + IH2_BASE) -#define INT_730_MPU_EXT_NIRQ (6 + IH2_BASE) -#define INT_730_SPI_100K_1 (7 + IH2_BASE) -#define INT_730_SYREN_SPI (8 + IH2_BASE) -#define INT_730_VLYNQ (9 + IH2_BASE) -#define INT_730_GPIO_BANK4 (10 + IH2_BASE) -#define INT_730_McBSP1TX (11 + IH2_BASE) -#define INT_730_McBSP1RX (12 + IH2_BASE) -#define INT_730_McBSP1RX_OF (13 + IH2_BASE) -#define INT_730_UART_MODEM_IRDA_2 (14 + IH2_BASE) -#define INT_730_UART_MODEM_1 (15 + IH2_BASE) -#define INT_730_MCSI (16 + IH2_BASE) -#define INT_730_uWireTX (17 + IH2_BASE) -#define INT_730_uWireRX (18 + IH2_BASE) -#define INT_730_SMC_CD (19 + IH2_BASE) -#define INT_730_SMC_IREQ (20 + IH2_BASE) -#define INT_730_HDQ_1WIRE (21 + IH2_BASE) -#define INT_730_TIMER32K (22 + IH2_BASE) -#define INT_730_MMC_SDIO (23 + IH2_BASE) -#define INT_730_UPLD (24 + IH2_BASE) -#define INT_730_USB_HHC_1 (27 + IH2_BASE) -#define INT_730_USB_HHC_2 (28 + IH2_BASE) -#define INT_730_USB_GENI (29 + IH2_BASE) -#define INT_730_USB_OTG (30 + IH2_BASE) -#define INT_730_CAMERA_IF (31 + IH2_BASE) -#define INT_730_RNG (32 + IH2_BASE) -#define INT_730_DUAL_MODE_TIMER (33 + IH2_BASE) -#define INT_730_DBB_RF_EN (34 + IH2_BASE) -#define INT_730_MPUIO_KEYPAD (35 + IH2_BASE) -#define INT_730_SHA1_MD5 (36 + IH2_BASE) -#define INT_730_SPI_100K_2 (37 + IH2_BASE) -#define INT_730_RNG_IDLE (38 + IH2_BASE) -#define INT_730_MPUIO (39 + IH2_BASE) -#define INT_730_LLPC_LCD_CTRL_CAN_BE_OFF (40 + IH2_BASE) -#define INT_730_LLPC_OE_FALLING (41 + IH2_BASE) -#define INT_730_LLPC_OE_RISING (42 + IH2_BASE) -#define INT_730_LLPC_VSYNC (43 + IH2_BASE) -#define INT_730_WAKE_UP_REQ (46 + IH2_BASE) -#define INT_730_DMA_CH6 (53 + IH2_BASE) -#define INT_730_DMA_CH7 (54 + IH2_BASE) -#define INT_730_DMA_CH8 (55 + IH2_BASE) -#define INT_730_DMA_CH9 (56 + IH2_BASE) -#define INT_730_DMA_CH10 (57 + IH2_BASE) -#define INT_730_DMA_CH11 (58 + IH2_BASE) -#define INT_730_DMA_CH12 (59 + IH2_BASE) -#define INT_730_DMA_CH13 (60 + IH2_BASE) -#define INT_730_DMA_CH14 (61 + IH2_BASE) -#define INT_730_DMA_CH15 (62 + IH2_BASE) -#define INT_730_NAND (63 + IH2_BASE) - -/* - * OMAP-850 specific IRQ numbers for interrupt handler 2 - */ -#define INT_850_HW_ERRORS (0 + IH2_BASE) -#define INT_850_NFIQ_PWR_FAIL (1 + IH2_BASE) -#define INT_850_CFCD (2 + IH2_BASE) -#define INT_850_CFIREQ (3 + IH2_BASE) -#define INT_850_I2C (4 + IH2_BASE) -#define INT_850_PCC (5 + IH2_BASE) -#define INT_850_MPU_EXT_NIRQ (6 + IH2_BASE) -#define INT_850_SPI_100K_1 (7 + IH2_BASE) -#define INT_850_SYREN_SPI (8 + IH2_BASE) -#define INT_850_VLYNQ (9 + IH2_BASE) -#define INT_850_GPIO_BANK4 (10 + IH2_BASE) -#define INT_850_McBSP1TX (11 + IH2_BASE) -#define INT_850_McBSP1RX (12 + IH2_BASE) -#define INT_850_McBSP1RX_OF (13 + IH2_BASE) -#define INT_850_UART_MODEM_IRDA_2 (14 + IH2_BASE) -#define INT_850_UART_MODEM_1 (15 + IH2_BASE) -#define INT_850_MCSI (16 + IH2_BASE) -#define INT_850_uWireTX (17 + IH2_BASE) -#define INT_850_uWireRX (18 + IH2_BASE) -#define INT_850_SMC_CD (19 + IH2_BASE) -#define INT_850_SMC_IREQ (20 + IH2_BASE) -#define INT_850_HDQ_1WIRE (21 + IH2_BASE) -#define INT_850_TIMER32K (22 + IH2_BASE) -#define INT_850_MMC_SDIO (23 + IH2_BASE) -#define INT_850_UPLD (24 + IH2_BASE) -#define INT_850_USB_HHC_1 (27 + IH2_BASE) -#define INT_850_USB_HHC_2 (28 + IH2_BASE) -#define INT_850_USB_GENI (29 + IH2_BASE) -#define INT_850_USB_OTG (30 + IH2_BASE) -#define INT_850_CAMERA_IF (31 + IH2_BASE) -#define INT_850_RNG (32 + IH2_BASE) -#define INT_850_DUAL_MODE_TIMER (33 + IH2_BASE) -#define INT_850_DBB_RF_EN (34 + IH2_BASE) -#define INT_850_MPUIO_KEYPAD (35 + IH2_BASE) -#define INT_850_SHA1_MD5 (36 + IH2_BASE) -#define INT_850_SPI_100K_2 (37 + IH2_BASE) -#define INT_850_RNG_IDLE (38 + IH2_BASE) -#define INT_850_MPUIO (39 + IH2_BASE) -#define INT_850_LLPC_LCD_CTRL_CAN_BE_OFF (40 + IH2_BASE) -#define INT_850_LLPC_OE_FALLING (41 + IH2_BASE) -#define INT_850_LLPC_OE_RISING (42 + IH2_BASE) -#define INT_850_LLPC_VSYNC (43 + IH2_BASE) -#define INT_850_WAKE_UP_REQ (46 + IH2_BASE) -#define INT_850_DMA_CH6 (53 + IH2_BASE) -#define INT_850_DMA_CH7 (54 + IH2_BASE) -#define INT_850_DMA_CH8 (55 + IH2_BASE) -#define INT_850_DMA_CH9 (56 + IH2_BASE) -#define INT_850_DMA_CH10 (57 + IH2_BASE) -#define INT_850_DMA_CH11 (58 + IH2_BASE) -#define INT_850_DMA_CH12 (59 + IH2_BASE) -#define INT_850_DMA_CH13 (60 + IH2_BASE) -#define INT_850_DMA_CH14 (61 + IH2_BASE) -#define INT_850_DMA_CH15 (62 + IH2_BASE) -#define INT_850_NAND (63 + IH2_BASE) - -#define INT_24XX_SYS_NIRQ 7 -#define INT_24XX_SDMA_IRQ0 12 -#define INT_24XX_SDMA_IRQ1 13 -#define INT_24XX_SDMA_IRQ2 14 -#define INT_24XX_SDMA_IRQ3 15 -#define INT_24XX_CAM_IRQ 24 -#define INT_24XX_DSS_IRQ 25 -#define INT_24XX_MAIL_U0_MPU 26 -#define INT_24XX_DSP_UMA 27 -#define INT_24XX_DSP_MMU 28 -#define INT_24XX_GPIO_BANK1 29 -#define INT_24XX_GPIO_BANK2 30 -#define INT_24XX_GPIO_BANK3 31 -#define INT_24XX_GPIO_BANK4 32 -#define INT_24XX_GPIO_BANK5 33 -#define INT_24XX_MAIL_U3_MPU 34 -#define INT_24XX_GPTIMER1 37 -#define INT_24XX_GPTIMER2 38 -#define INT_24XX_GPTIMER3 39 -#define INT_24XX_GPTIMER4 40 -#define INT_24XX_GPTIMER5 41 -#define INT_24XX_GPTIMER6 42 -#define INT_24XX_GPTIMER7 43 -#define INT_24XX_GPTIMER8 44 -#define INT_24XX_GPTIMER9 45 -#define INT_24XX_GPTIMER10 46 -#define INT_24XX_GPTIMER11 47 -#define INT_24XX_GPTIMER12 48 -#define INT_24XX_SHA1MD5 51 -#define INT_24XX_MCBSP4_IRQ_TX 54 -#define INT_24XX_MCBSP4_IRQ_RX 55 -#define INT_24XX_I2C1_IRQ 56 -#define INT_24XX_I2C2_IRQ 57 -#define INT_24XX_HDQ_IRQ 58 -#define INT_24XX_MCBSP1_IRQ_TX 59 -#define INT_24XX_MCBSP1_IRQ_RX 60 -#define INT_24XX_MCBSP2_IRQ_TX 62 -#define INT_24XX_MCBSP2_IRQ_RX 63 -#define INT_24XX_SPI1_IRQ 65 -#define INT_24XX_SPI2_IRQ 66 -#define INT_24XX_UART1_IRQ 72 -#define INT_24XX_UART2_IRQ 73 -#define INT_24XX_UART3_IRQ 74 -#define INT_24XX_USB_IRQ_GEN 75 -#define INT_24XX_USB_IRQ_NISO 76 -#define INT_24XX_USB_IRQ_ISO 77 -#define INT_24XX_USB_IRQ_HGEN 78 -#define INT_24XX_USB_IRQ_HSOF 79 -#define INT_24XX_USB_IRQ_OTG 80 -#define INT_24XX_MCBSP5_IRQ_TX 81 -#define INT_24XX_MCBSP5_IRQ_RX 82 -#define INT_24XX_MMC_IRQ 83 -#define INT_24XX_MMC2_IRQ 86 -#define INT_24XX_MCBSP3_IRQ_TX 89 -#define INT_24XX_MCBSP3_IRQ_RX 90 -#define INT_24XX_SPI3_IRQ 91 - -#define INT_243X_MCBSP2_IRQ 16 -#define INT_243X_MCBSP3_IRQ 17 -#define INT_243X_MCBSP4_IRQ 18 -#define INT_243X_MCBSP5_IRQ 19 -#define INT_243X_MCBSP1_IRQ 64 -#define INT_243X_HS_USB_MC 92 -#define INT_243X_HS_USB_DMA 93 -#define INT_243X_CARKIT_IRQ 94 - -#define INT_34XX_BENCH_MPU_EMUL 3 -#define INT_34XX_ST_MCBSP2_IRQ 4 -#define INT_34XX_ST_MCBSP3_IRQ 5 -#define INT_34XX_SSM_ABORT_IRQ 6 -#define INT_34XX_SYS_NIRQ 7 -#define INT_34XX_D2D_FW_IRQ 8 -#define INT_34XX_PRCM_MPU_IRQ 11 -#define INT_34XX_MCBSP1_IRQ 16 -#define INT_34XX_MCBSP2_IRQ 17 -#define INT_34XX_MCBSP3_IRQ 22 -#define INT_34XX_MCBSP4_IRQ 23 -#define INT_34XX_CAM_IRQ 24 -#define INT_34XX_MCBSP5_IRQ 27 -#define INT_34XX_GPIO_BANK1 29 -#define INT_34XX_GPIO_BANK2 30 -#define INT_34XX_GPIO_BANK3 31 -#define INT_34XX_GPIO_BANK4 32 -#define INT_34XX_GPIO_BANK5 33 -#define INT_34XX_GPIO_BANK6 34 -#define INT_34XX_USIM_IRQ 35 -#define INT_34XX_WDT3_IRQ 36 -#define INT_34XX_SPI4_IRQ 48 -#define INT_34XX_SHA1MD52_IRQ 49 -#define INT_34XX_FPKA_READY_IRQ 50 -#define INT_34XX_SHA1MD51_IRQ 51 -#define INT_34XX_RNG_IRQ 52 -#define INT_34XX_I2C3_IRQ 61 -#define INT_34XX_FPKA_ERROR_IRQ 64 -#define INT_34XX_PBIAS_IRQ 75 -#define INT_34XX_OHCI_IRQ 76 -#define INT_34XX_EHCI_IRQ 77 -#define INT_34XX_TLL_IRQ 78 -#define INT_34XX_PARTHASH_IRQ 79 -#define INT_34XX_MMC3_IRQ 94 -#define INT_34XX_GPT12_IRQ 95 - -#define INT_34XX_BENCH_MPU_EMUL 3 - - -#define IRQ_GIC_START 32 -#define INT_44XX_LOCALTIMER_IRQ 29 -#define INT_44XX_LOCALWDT_IRQ 30 - -#define INT_44XX_BENCH_MPU_EMUL (3 + IRQ_GIC_START) -#define INT_44XX_SSM_ABORT_IRQ (6 + IRQ_GIC_START) -#define INT_44XX_SYS_NIRQ (7 + IRQ_GIC_START) -#define INT_44XX_D2D_FW_IRQ (8 + IRQ_GIC_START) -#define INT_44XX_PRCM_MPU_IRQ (11 + IRQ_GIC_START) -#define INT_44XX_SDMA_IRQ0 (12 + IRQ_GIC_START) -#define INT_44XX_SDMA_IRQ1 (13 + IRQ_GIC_START) -#define INT_44XX_SDMA_IRQ2 (14 + IRQ_GIC_START) -#define INT_44XX_SDMA_IRQ3 (15 + IRQ_GIC_START) -#define INT_44XX_ISS_IRQ (24 + IRQ_GIC_START) -#define INT_44XX_DSS_IRQ (25 + IRQ_GIC_START) -#define INT_44XX_MAIL_U0_MPU (26 + IRQ_GIC_START) -#define INT_44XX_DSP_MMU (28 + IRQ_GIC_START) -#define INT_44XX_GPTIMER1 (37 + IRQ_GIC_START) -#define INT_44XX_GPTIMER2 (38 + IRQ_GIC_START) -#define INT_44XX_GPTIMER3 (39 + IRQ_GIC_START) -#define INT_44XX_GPTIMER4 (40 + IRQ_GIC_START) -#define INT_44XX_GPTIMER5 (41 + IRQ_GIC_START) -#define INT_44XX_GPTIMER6 (42 + IRQ_GIC_START) -#define INT_44XX_GPTIMER7 (43 + IRQ_GIC_START) -#define INT_44XX_GPTIMER8 (44 + IRQ_GIC_START) -#define INT_44XX_GPTIMER9 (45 + IRQ_GIC_START) -#define INT_44XX_GPTIMER10 (46 + IRQ_GIC_START) -#define INT_44XX_GPTIMER11 (47 + IRQ_GIC_START) -#define INT_44XX_GPTIMER12 (95 + IRQ_GIC_START) -#define INT_44XX_SHA1MD5 (51 + IRQ_GIC_START) -#define INT_44XX_I2C1_IRQ (56 + IRQ_GIC_START) -#define INT_44XX_I2C2_IRQ (57 + IRQ_GIC_START) -#define INT_44XX_HDQ_IRQ (58 + IRQ_GIC_START) -#define INT_44XX_SPI1_IRQ (65 + IRQ_GIC_START) -#define INT_44XX_SPI2_IRQ (66 + IRQ_GIC_START) -#define INT_44XX_HSI_1_IRQ0 (67 + IRQ_GIC_START) -#define INT_44XX_HSI_2_IRQ1 (68 + IRQ_GIC_START) -#define INT_44XX_HSI_1_DMAIRQ (71 + IRQ_GIC_START) -#define INT_44XX_UART1_IRQ (72 + IRQ_GIC_START) -#define INT_44XX_UART2_IRQ (73 + IRQ_GIC_START) -#define INT_44XX_UART3_IRQ (74 + IRQ_GIC_START) -#define INT_44XX_UART4_IRQ (70 + IRQ_GIC_START) -#define INT_44XX_USB_IRQ_NISO (76 + IRQ_GIC_START) -#define INT_44XX_USB_IRQ_ISO (77 + IRQ_GIC_START) -#define INT_44XX_USB_IRQ_HGEN (78 + IRQ_GIC_START) -#define INT_44XX_USB_IRQ_HSOF (79 + IRQ_GIC_START) -#define INT_44XX_USB_IRQ_OTG (80 + IRQ_GIC_START) -#define INT_44XX_MCBSP4_IRQ_TX (81 + IRQ_GIC_START) -#define INT_44XX_MCBSP4_IRQ_RX (82 + IRQ_GIC_START) -#define INT_44XX_MMC_IRQ (83 + IRQ_GIC_START) -#define INT_44XX_MMC2_IRQ (86 + IRQ_GIC_START) -#define INT_44XX_MCBSP2_IRQ_TX (89 + IRQ_GIC_START) -#define INT_44XX_MCBSP2_IRQ_RX (90 + IRQ_GIC_START) -#define INT_44XX_SPI3_IRQ (91 + IRQ_GIC_START) -#define INT_44XX_SPI5_IRQ (69 + IRQ_GIC_START) - -#define INT_44XX_MCBSP5_IRQ (16 + IRQ_GIC_START) -#define INT_44xX_MCBSP1_IRQ (17 + IRQ_GIC_START) -#define INT_44XX_MCBSP2_IRQ (22 + IRQ_GIC_START) -#define INT_44XX_MCBSP3_IRQ (23 + IRQ_GIC_START) -#define INT_44XX_MCBSP4_IRQ (27 + IRQ_GIC_START) -#define INT_44XX_HS_USB_MC (92 + IRQ_GIC_START) -#define INT_44XX_HS_USB_DMA (93 + IRQ_GIC_START) - -#define INT_44XX_GPIO_BANK1 (29 + IRQ_GIC_START) -#define INT_44XX_GPIO_BANK2 (30 + IRQ_GIC_START) -#define INT_44XX_GPIO_BANK3 (31 + IRQ_GIC_START) -#define INT_44XX_GPIO_BANK4 (32 + IRQ_GIC_START) -#define INT_44XX_GPIO_BANK5 (33 + IRQ_GIC_START) -#define INT_44XX_GPIO_BANK6 (34 + IRQ_GIC_START) -#define INT_44XX_USIM_IRQ (35 + IRQ_GIC_START) -#define INT_44XX_WDT3_IRQ (36 + IRQ_GIC_START) -#define INT_44XX_SPI4_IRQ (48 + IRQ_GIC_START) -#define INT_44XX_SHA1MD52_IRQ (49 + IRQ_GIC_START) -#define INT_44XX_FPKA_READY_IRQ (50 + IRQ_GIC_START) -#define INT_44XX_SHA1MD51_IRQ (51 + IRQ_GIC_START) -#define INT_44XX_RNG_IRQ (52 + IRQ_GIC_START) -#define INT_44XX_MMC5_IRQ (59 + IRQ_GIC_START) -#define INT_44XX_I2C3_IRQ (61 + IRQ_GIC_START) -#define INT_44XX_FPKA_ERROR_IRQ (64 + IRQ_GIC_START) -#define INT_44XX_PBIAS_IRQ (75 + IRQ_GIC_START) -#define INT_44XX_OHCI_IRQ (76 + IRQ_GIC_START) -#define INT_44XX_EHCI_IRQ (77 + IRQ_GIC_START) -#define INT_44XX_TLL_IRQ (78 + IRQ_GIC_START) -#define INT_44XX_PARTHASH_IRQ (79 + IRQ_GIC_START) -#define INT_44XX_MMC3_IRQ (94 + IRQ_GIC_START) -#define INT_44XX_MMC4_IRQ (96 + IRQ_GIC_START) - - -/* Max. 128 level 2 IRQs (OMAP1610), 192 GPIOs (OMAP730/850) and - * 16 MPUIO lines */ -#define OMAP_MAX_GPIO_LINES 192 -#define IH_GPIO_BASE (128 + IH2_BASE) -#define IH_MPUIO_BASE (OMAP_MAX_GPIO_LINES + IH_GPIO_BASE) -#define OMAP_IRQ_END (IH_MPUIO_BASE + 16) - -/* External FPGA handles interrupts on Innovator boards */ -#define OMAP_FPGA_IRQ_BASE (OMAP_IRQ_END) -#ifdef CONFIG_MACH_OMAP_INNOVATOR -#define OMAP_FPGA_NR_IRQS 24 -#else -#define OMAP_FPGA_NR_IRQS 0 -#endif -#define OMAP_FPGA_IRQ_END (OMAP_FPGA_IRQ_BASE + OMAP_FPGA_NR_IRQS) - -/* External TWL4030 can handle interrupts on 2430 and 34xx boards */ -#define TWL4030_IRQ_BASE (OMAP_FPGA_IRQ_END) -#ifdef CONFIG_TWL4030_CORE -#define TWL4030_BASE_NR_IRQS 8 -#define TWL4030_PWR_NR_IRQS 8 -#else -#define TWL4030_BASE_NR_IRQS 0 -#define TWL4030_PWR_NR_IRQS 0 -#endif -#define TWL4030_IRQ_END (TWL4030_IRQ_BASE + TWL4030_BASE_NR_IRQS) -#define TWL4030_PWR_IRQ_BASE TWL4030_IRQ_END -#define TWL4030_PWR_IRQ_END (TWL4030_PWR_IRQ_BASE + TWL4030_PWR_NR_IRQS) - -/* External TWL4030 gpio interrupts are optional */ -#define TWL4030_GPIO_IRQ_BASE TWL4030_PWR_IRQ_END -#ifdef CONFIG_GPIO_TWL4030 -#define TWL4030_GPIO_NR_IRQS 18 -#else -#define TWL4030_GPIO_NR_IRQS 0 -#endif -#define TWL4030_GPIO_IRQ_END (TWL4030_GPIO_IRQ_BASE + TWL4030_GPIO_NR_IRQS) - -/* Total number of interrupts depends on the enabled blocks above */ -#define NR_IRQS TWL4030_GPIO_IRQ_END - -#define OMAP_IRQ_BIT(irq) (1 << ((irq) % 32)) - -#ifndef __ASSEMBLY__ -extern void omap_init_irq(void); -extern int omap_irq_pending(void); -#endif - -#include <mach/hardware.h> - -#endif diff --git a/arch/arm/plat-omap/include/mach/keypad.h b/arch/arm/plat-omap/include/mach/keypad.h deleted file mode 100644 index d91b9be334f..00000000000 --- a/arch/arm/plat-omap/include/mach/keypad.h +++ /dev/null @@ -1,42 +0,0 @@ -/* - * arch/arm/plat-omap/include/mach/keypad.h - * - * Copyright (C) 2006 Komal Shah <komal_shah802003@yahoo.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#ifndef ASMARM_ARCH_KEYPAD_H -#define ASMARM_ARCH_KEYPAD_H - -#include <linux/input/matrix_keypad.h> - -struct omap_kp_platform_data { - int rows; - int cols; - int *keymap; - unsigned int keymapsize; - unsigned int rep:1; - unsigned long delay; - unsigned int dbounce:1; - /* specific to OMAP242x*/ - unsigned int *row_gpios; - unsigned int *col_gpios; -}; - -/* Group (0..3) -- when multiple keys are pressed, only the - * keys pressed in the same group are considered as pressed. This is - * in order to workaround certain crappy HW designs that produce ghost - * keypresses. */ -#define GROUP_0 (0 << 16) -#define GROUP_1 (1 << 16) -#define GROUP_2 (2 << 16) -#define GROUP_3 (3 << 16) -#define GROUP_MASK GROUP_3 - -#define KEY_PERSISTENT 0x00800000 -#define KEYNUM_MASK 0x00EFFFFF - -#endif - diff --git a/arch/arm/plat-omap/include/mach/lcd_mipid.h b/arch/arm/plat-omap/include/mach/lcd_mipid.h deleted file mode 100644 index 8e52c657228..00000000000 --- a/arch/arm/plat-omap/include/mach/lcd_mipid.h +++ /dev/null @@ -1,29 +0,0 @@ -#ifndef __LCD_MIPID_H -#define __LCD_MIPID_H - -enum mipid_test_num { - MIPID_TEST_RGB_LINES, -}; - -enum mipid_test_result { - MIPID_TEST_SUCCESS, - MIPID_TEST_INVALID, - MIPID_TEST_FAILED, -}; - -#ifdef __KERNEL__ - -struct mipid_platform_data { - int nreset_gpio; - int data_lines; - - void (*shutdown)(struct mipid_platform_data *pdata); - void (*set_bklight_level)(struct mipid_platform_data *pdata, - int level); - int (*get_bklight_level)(struct mipid_platform_data *pdata); - int (*get_bklight_max)(struct mipid_platform_data *pdata); -}; - -#endif - -#endif diff --git a/arch/arm/plat-omap/include/mach/led.h b/arch/arm/plat-omap/include/mach/led.h deleted file mode 100644 index 25e451e7e2f..00000000000 --- a/arch/arm/plat-omap/include/mach/led.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * arch/arm/plat-omap/include/mach/led.h - * - * Copyright (C) 2006 Samsung Electronics - * Kyungmin Park <kyungmin.park@samsung.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#ifndef ASMARM_ARCH_LED_H -#define ASMARM_ARCH_LED_H - -struct omap_led_config { - struct led_classdev cdev; - s16 gpio; -}; - -struct omap_led_platform_data { - s16 nr_leds; - struct omap_led_config *leds; -}; - -#endif diff --git a/arch/arm/plat-omap/include/mach/mailbox.h b/arch/arm/plat-omap/include/mach/mailbox.h deleted file mode 100644 index b7a6991814e..00000000000 --- a/arch/arm/plat-omap/include/mach/mailbox.h +++ /dev/null @@ -1,96 +0,0 @@ -/* mailbox.h */ - -#ifndef MAILBOX_H -#define MAILBOX_H - -#include <linux/wait.h> -#include <linux/workqueue.h> -#include <linux/blkdev.h> - -typedef u32 mbox_msg_t; -typedef void (mbox_receiver_t)(mbox_msg_t msg); -struct omap_mbox; - -typedef int __bitwise omap_mbox_irq_t; -#define IRQ_TX ((__force omap_mbox_irq_t) 1) -#define IRQ_RX ((__force omap_mbox_irq_t) 2) - -typedef int __bitwise omap_mbox_type_t; -#define OMAP_MBOX_TYPE1 ((__force omap_mbox_type_t) 1) -#define OMAP_MBOX_TYPE2 ((__force omap_mbox_type_t) 2) - -struct omap_mbox_ops { - omap_mbox_type_t type; - int (*startup)(struct omap_mbox *mbox); - void (*shutdown)(struct omap_mbox *mbox); - /* fifo */ - mbox_msg_t (*fifo_read)(struct omap_mbox *mbox); - void (*fifo_write)(struct omap_mbox *mbox, mbox_msg_t msg); - int (*fifo_empty)(struct omap_mbox *mbox); - int (*fifo_full)(struct omap_mbox *mbox); - /* irq */ - void (*enable_irq)(struct omap_mbox *mbox, omap_mbox_irq_t irq); - void (*disable_irq)(struct omap_mbox *mbox, omap_mbox_irq_t irq); - void (*ack_irq)(struct omap_mbox *mbox, omap_mbox_irq_t irq); - int (*is_irq)(struct omap_mbox *mbox, omap_mbox_irq_t irq); - /* ctx */ - void (*save_ctx)(struct omap_mbox *mbox); - void (*restore_ctx)(struct omap_mbox *mbox); -}; - -struct omap_mbox_queue { - spinlock_t lock; - struct request_queue *queue; - struct work_struct work; - int (*callback)(void *); - struct omap_mbox *mbox; -}; - -struct omap_mbox { - char *name; - unsigned int irq; - - struct omap_mbox_queue *txq, *rxq; - - struct omap_mbox_ops *ops; - - mbox_msg_t seq_snd, seq_rcv; - - struct device *dev; - - struct omap_mbox *next; - void *priv; - - void (*err_notify)(void); -}; - -int omap_mbox_msg_send(struct omap_mbox *, mbox_msg_t msg, void *); -void omap_mbox_init_seq(struct omap_mbox *); - -struct omap_mbox *omap_mbox_get(const char *); -void omap_mbox_put(struct omap_mbox *); - -int omap_mbox_register(struct device *parent, struct omap_mbox *); -int omap_mbox_unregister(struct omap_mbox *); - -static inline void omap_mbox_save_ctx(struct omap_mbox *mbox) -{ - if (!mbox->ops->save_ctx) { - dev_err(mbox->dev, "%s:\tno save\n", __func__); - return; - } - - mbox->ops->save_ctx(mbox); -} - -static inline void omap_mbox_restore_ctx(struct omap_mbox *mbox) -{ - if (!mbox->ops->restore_ctx) { - dev_err(mbox->dev, "%s:\tno restore\n", __func__); - return; - } - - mbox->ops->restore_ctx(mbox); -} - -#endif /* MAILBOX_H */ diff --git a/arch/arm/plat-omap/include/mach/mcbsp.h b/arch/arm/plat-omap/include/mach/mcbsp.h deleted file mode 100644 index e0d6eca222c..00000000000 --- a/arch/arm/plat-omap/include/mach/mcbsp.h +++ /dev/null @@ -1,462 +0,0 @@ -/* - * arch/arm/plat-omap/include/mach/mcbsp.h - * - * Defines for Multi-Channel Buffered Serial Port - * - * Copyright (C) 2002 RidgeRun, Inc. - * Author: Steve Johnson - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - * - */ -#ifndef __ASM_ARCH_OMAP_MCBSP_H -#define __ASM_ARCH_OMAP_MCBSP_H - -#include <linux/completion.h> -#include <linux/spinlock.h> - -#include <mach/hardware.h> -#include <mach/clock.h> - -#define OMAP730_MCBSP1_BASE 0xfffb1000 -#define OMAP730_MCBSP2_BASE 0xfffb1800 - -#define OMAP1510_MCBSP1_BASE 0xe1011800 -#define OMAP1510_MCBSP2_BASE 0xfffb1000 -#define OMAP1510_MCBSP3_BASE 0xe1017000 - -#define OMAP1610_MCBSP1_BASE 0xe1011800 -#define OMAP1610_MCBSP2_BASE 0xfffb1000 -#define OMAP1610_MCBSP3_BASE 0xe1017000 - -#define OMAP24XX_MCBSP1_BASE 0x48074000 -#define OMAP24XX_MCBSP2_BASE 0x48076000 -#define OMAP2430_MCBSP3_BASE 0x4808c000 -#define OMAP2430_MCBSP4_BASE 0x4808e000 -#define OMAP2430_MCBSP5_BASE 0x48096000 - -#define OMAP34XX_MCBSP1_BASE 0x48074000 -#define OMAP34XX_MCBSP2_BASE 0x49022000 -#define OMAP34XX_MCBSP3_BASE 0x49024000 -#define OMAP34XX_MCBSP4_BASE 0x49026000 -#define OMAP34XX_MCBSP5_BASE 0x48096000 - -#define OMAP44XX_MCBSP1_BASE 0x49022000 -#define OMAP44XX_MCBSP2_BASE 0x49024000 -#define OMAP44XX_MCBSP3_BASE 0x49026000 -#define OMAP44XX_MCBSP4_BASE 0x48074000 - -#if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP730) - -#define OMAP_MCBSP_REG_DRR2 0x00 -#define OMAP_MCBSP_REG_DRR1 0x02 -#define OMAP_MCBSP_REG_DXR2 0x04 -#define OMAP_MCBSP_REG_DXR1 0x06 -#define OMAP_MCBSP_REG_SPCR2 0x08 -#define OMAP_MCBSP_REG_SPCR1 0x0a -#define OMAP_MCBSP_REG_RCR2 0x0c -#define OMAP_MCBSP_REG_RCR1 0x0e -#define OMAP_MCBSP_REG_XCR2 0x10 -#define OMAP_MCBSP_REG_XCR1 0x12 -#define OMAP_MCBSP_REG_SRGR2 0x14 -#define OMAP_MCBSP_REG_SRGR1 0x16 -#define OMAP_MCBSP_REG_MCR2 0x18 -#define OMAP_MCBSP_REG_MCR1 0x1a -#define OMAP_MCBSP_REG_RCERA 0x1c -#define OMAP_MCBSP_REG_RCERB 0x1e -#define OMAP_MCBSP_REG_XCERA 0x20 -#define OMAP_MCBSP_REG_XCERB 0x22 -#define OMAP_MCBSP_REG_PCR0 0x24 -#define OMAP_MCBSP_REG_RCERC 0x26 -#define OMAP_MCBSP_REG_RCERD 0x28 -#define OMAP_MCBSP_REG_XCERC 0x2A -#define OMAP_MCBSP_REG_XCERD 0x2C -#define OMAP_MCBSP_REG_RCERE 0x2E -#define OMAP_MCBSP_REG_RCERF 0x30 -#define OMAP_MCBSP_REG_XCERE 0x32 -#define OMAP_MCBSP_REG_XCERF 0x34 -#define OMAP_MCBSP_REG_RCERG 0x36 -#define OMAP_MCBSP_REG_RCERH 0x38 -#define OMAP_MCBSP_REG_XCERG 0x3A -#define OMAP_MCBSP_REG_XCERH 0x3C - -/* Dummy defines, these are not available on omap1 */ -#define OMAP_MCBSP_REG_XCCR 0x00 -#define OMAP_MCBSP_REG_RCCR 0x00 - -#define AUDIO_MCBSP_DATAWRITE (OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1) -#define AUDIO_MCBSP_DATAREAD (OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DRR1) - -#define AUDIO_MCBSP OMAP_MCBSP1 -#define AUDIO_DMA_TX OMAP_DMA_MCBSP1_TX -#define AUDIO_DMA_RX OMAP_DMA_MCBSP1_RX - -#elif defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \ - defined(CONFIG_ARCH_OMAP4) - -#define OMAP_MCBSP_REG_DRR2 0x00 -#define OMAP_MCBSP_REG_DRR1 0x04 -#define OMAP_MCBSP_REG_DXR2 0x08 -#define OMAP_MCBSP_REG_DXR1 0x0C -#define OMAP_MCBSP_REG_DRR 0x00 -#define OMAP_MCBSP_REG_DXR 0x08 -#define OMAP_MCBSP_REG_SPCR2 0x10 -#define OMAP_MCBSP_REG_SPCR1 0x14 -#define OMAP_MCBSP_REG_RCR2 0x18 -#define OMAP_MCBSP_REG_RCR1 0x1C -#define OMAP_MCBSP_REG_XCR2 0x20 -#define OMAP_MCBSP_REG_XCR1 0x24 -#define OMAP_MCBSP_REG_SRGR2 0x28 -#define OMAP_MCBSP_REG_SRGR1 0x2C -#define OMAP_MCBSP_REG_MCR2 0x30 -#define OMAP_MCBSP_REG_MCR1 0x34 -#define OMAP_MCBSP_REG_RCERA 0x38 -#define OMAP_MCBSP_REG_RCERB 0x3C -#define OMAP_MCBSP_REG_XCERA 0x40 -#define OMAP_MCBSP_REG_XCERB 0x44 -#define OMAP_MCBSP_REG_PCR0 0x48 -#define OMAP_MCBSP_REG_RCERC 0x4C -#define OMAP_MCBSP_REG_RCERD 0x50 -#define OMAP_MCBSP_REG_XCERC 0x54 -#define OMAP_MCBSP_REG_XCERD 0x58 -#define OMAP_MCBSP_REG_RCERE 0x5C -#define OMAP_MCBSP_REG_RCERF 0x60 -#define OMAP_MCBSP_REG_XCERE 0x64 -#define OMAP_MCBSP_REG_XCERF 0x68 -#define OMAP_MCBSP_REG_RCERG 0x6C -#define OMAP_MCBSP_REG_RCERH 0x70 -#define OMAP_MCBSP_REG_XCERG 0x74 -#define OMAP_MCBSP_REG_XCERH 0x78 -#define OMAP_MCBSP_REG_SYSCON 0x8C -#define OMAP_MCBSP_REG_THRSH2 0x90 -#define OMAP_MCBSP_REG_THRSH1 0x94 -#define OMAP_MCBSP_REG_IRQST 0xA0 -#define OMAP_MCBSP_REG_IRQEN 0xA4 -#define OMAP_MCBSP_REG_WAKEUPEN 0xA8 -#define OMAP_MCBSP_REG_XCCR 0xAC -#define OMAP_MCBSP_REG_RCCR 0xB0 - -#define AUDIO_MCBSP_DATAWRITE (OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR1) -#define AUDIO_MCBSP_DATAREAD (OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR1) - -#define AUDIO_MCBSP OMAP_MCBSP2 -#define AUDIO_DMA_TX OMAP24XX_DMA_MCBSP2_TX -#define AUDIO_DMA_RX OMAP24XX_DMA_MCBSP2_RX - -#endif - -/************************** McBSP SPCR1 bit definitions ***********************/ -#define RRST 0x0001 -#define RRDY 0x0002 -#define RFULL 0x0004 -#define RSYNC_ERR 0x0008 -#define RINTM(value) ((value)<<4) /* bits 4:5 */ -#define ABIS 0x0040 -#define DXENA 0x0080 -#define CLKSTP(value) ((value)<<11) /* bits 11:12 */ -#define RJUST(value) ((value)<<13) /* bits 13:14 */ -#define ALB 0x8000 -#define DLB 0x8000 - -/************************** McBSP SPCR2 bit definitions ***********************/ -#define XRST 0x0001 -#define XRDY 0x0002 -#define XEMPTY 0x0004 -#define XSYNC_ERR 0x0008 -#define XINTM(value) ((value)<<4) /* bits 4:5 */ -#define GRST 0x0040 -#define FRST 0x0080 -#define SOFT 0x0100 -#define FREE 0x0200 - -/************************** McBSP PCR bit definitions *************************/ -#define CLKRP 0x0001 -#define CLKXP 0x0002 -#define FSRP 0x0004 -#define FSXP 0x0008 -#define DR_STAT 0x0010 -#define DX_STAT 0x0020 -#define CLKS_STAT 0x0040 -#define SCLKME 0x0080 -#define CLKRM 0x0100 -#define CLKXM 0x0200 -#define FSRM 0x0400 -#define FSXM 0x0800 -#define RIOEN 0x1000 -#define XIOEN 0x2000 -#define IDLE_EN 0x4000 - -/************************** McBSP RCR1 bit definitions ************************/ -#define RWDLEN1(value) ((value)<<5) /* Bits 5:7 */ -#define RFRLEN1(value) ((value)<<8) /* Bits 8:14 */ - -/************************** McBSP XCR1 bit definitions ************************/ -#define XWDLEN1(value) ((value)<<5) /* Bits 5:7 */ -#define XFRLEN1(value) ((value)<<8) /* Bits 8:14 */ - -/*************************** McBSP RCR2 bit definitions ***********************/ -#define RDATDLY(value) (value) /* Bits 0:1 */ -#define RFIG 0x0004 -#define RCOMPAND(value) ((value)<<3) /* Bits 3:4 */ -#define RWDLEN2(value) ((value)<<5) /* Bits 5:7 */ -#define RFRLEN2(value) ((value)<<8) /* Bits 8:14 */ -#define RPHASE 0x8000 - -/*************************** McBSP XCR2 bit definitions ***********************/ -#define XDATDLY(value) (value) /* Bits 0:1 */ -#define XFIG 0x0004 -#define XCOMPAND(value) ((value)<<3) /* Bits 3:4 */ -#define XWDLEN2(value) ((value)<<5) /* Bits 5:7 */ -#define XFRLEN2(value) ((value)<<8) /* Bits 8:14 */ -#define XPHASE 0x8000 - -/************************* McBSP SRGR1 bit definitions ************************/ -#define CLKGDV(value) (value) /* Bits 0:7 */ -#define FWID(value) ((value)<<8) /* Bits 8:15 */ - -/************************* McBSP SRGR2 bit definitions ************************/ -#define FPER(value) (value) /* Bits 0:11 */ -#define FSGM 0x1000 -#define CLKSM 0x2000 -#define CLKSP 0x4000 -#define GSYNC 0x8000 - -/************************* McBSP MCR1 bit definitions *************************/ -#define RMCM 0x0001 -#define RCBLK(value) ((value)<<2) /* Bits 2:4 */ -#define RPABLK(value) ((value)<<5) /* Bits 5:6 */ -#define RPBBLK(value) ((value)<<7) /* Bits 7:8 */ - -/************************* McBSP MCR2 bit definitions *************************/ -#define XMCM(value) (value) /* Bits 0:1 */ -#define XCBLK(value) ((value)<<2) /* Bits 2:4 */ -#define XPABLK(value) ((value)<<5) /* Bits 5:6 */ -#define XPBBLK(value) ((value)<<7) /* Bits 7:8 */ - -/*********************** McBSP XCCR bit definitions *************************/ -#define EXTCLKGATE 0x8000 -#define PPCONNECT 0x4000 -#define DXENDLY(value) ((value)<<12) /* Bits 12:13 */ -#define XFULL_CYCLE 0x0800 -#define DILB 0x0020 -#define XDMAEN 0x0008 -#define XDISABLE 0x0001 - -/********************** McBSP RCCR bit definitions *************************/ -#define RFULL_CYCLE 0x0800 -#define RDMAEN 0x0008 -#define RDISABLE 0x0001 - -/********************** McBSP SYSCONFIG bit definitions ********************/ -#define CLOCKACTIVITY(value) ((value)<<8) -#define SIDLEMODE(value) ((value)<<3) -#define ENAWAKEUP 0x0004 -#define SOFTRST 0x0002 - -/********************** McBSP DMA operating modes **************************/ -#define MCBSP_DMA_MODE_ELEMENT 0 -#define MCBSP_DMA_MODE_THRESHOLD 1 -#define MCBSP_DMA_MODE_FRAME 2 - -/********************** McBSP WAKEUPEN bit definitions *********************/ -#define XEMPTYEOFEN 0x4000 -#define XRDYEN 0x0400 -#define XEOFEN 0x0200 -#define XFSXEN 0x0100 -#define XSYNCERREN 0x0080 -#define RRDYEN 0x0008 -#define REOFEN 0x0004 -#define RFSREN 0x0002 -#define RSYNCERREN 0x0001 - -/* we don't do multichannel for now */ -struct omap_mcbsp_reg_cfg { - u16 spcr2; - u16 spcr1; - u16 rcr2; - u16 rcr1; - u16 xcr2; - u16 xcr1; - u16 srgr2; - u16 srgr1; - u16 mcr2; - u16 mcr1; - u16 pcr0; - u16 rcerc; - u16 rcerd; - u16 xcerc; - u16 xcerd; - u16 rcere; - u16 rcerf; - u16 xcere; - u16 xcerf; - u16 rcerg; - u16 rcerh; - u16 xcerg; - u16 xcerh; - u16 xccr; - u16 rccr; -}; - -typedef enum { - OMAP_MCBSP1 = 0, - OMAP_MCBSP2, - OMAP_MCBSP3, - OMAP_MCBSP4, - OMAP_MCBSP5 -} omap_mcbsp_id; - -typedef int __bitwise omap_mcbsp_io_type_t; -#define OMAP_MCBSP_IRQ_IO ((__force omap_mcbsp_io_type_t) 1) -#define OMAP_MCBSP_POLL_IO ((__force omap_mcbsp_io_type_t) 2) - -typedef enum { - OMAP_MCBSP_WORD_8 = 0, - OMAP_MCBSP_WORD_12, - OMAP_MCBSP_WORD_16, - OMAP_MCBSP_WORD_20, - OMAP_MCBSP_WORD_24, - OMAP_MCBSP_WORD_32, -} omap_mcbsp_word_length; - -typedef enum { - OMAP_MCBSP_CLK_RISING = 0, - OMAP_MCBSP_CLK_FALLING, -} omap_mcbsp_clk_polarity; - -typedef enum { - OMAP_MCBSP_FS_ACTIVE_HIGH = 0, - OMAP_MCBSP_FS_ACTIVE_LOW, -} omap_mcbsp_fs_polarity; - -typedef enum { - OMAP_MCBSP_CLK_STP_MODE_NO_DELAY = 0, - OMAP_MCBSP_CLK_STP_MODE_DELAY, -} omap_mcbsp_clk_stp_mode; - - -/******* SPI specific mode **********/ -typedef enum { - OMAP_MCBSP_SPI_MASTER = 0, - OMAP_MCBSP_SPI_SLAVE, -} omap_mcbsp_spi_mode; - -struct omap_mcbsp_spi_cfg { - omap_mcbsp_spi_mode spi_mode; - omap_mcbsp_clk_polarity rx_clock_polarity; - omap_mcbsp_clk_polarity tx_clock_polarity; - omap_mcbsp_fs_polarity fsx_polarity; - u8 clk_div; - omap_mcbsp_clk_stp_mode clk_stp_mode; - omap_mcbsp_word_length word_length; -}; - -/* Platform specific configuration */ -struct omap_mcbsp_ops { - void (*request)(unsigned int); - void (*free)(unsigned int); -}; - -struct omap_mcbsp_platform_data { - unsigned long phys_base; - u8 dma_rx_sync, dma_tx_sync; - u16 rx_irq, tx_irq; - struct omap_mcbsp_ops *ops; -#ifdef CONFIG_ARCH_OMAP34XX - u16 buffer_size; -#endif -}; - -struct omap_mcbsp { - struct device *dev; - unsigned long phys_base; - void __iomem *io_base; - u8 id; - u8 free; - omap_mcbsp_word_length rx_word_length; - omap_mcbsp_word_length tx_word_length; - - omap_mcbsp_io_type_t io_type; /* IRQ or poll */ - /* IRQ based TX/RX */ - int rx_irq; - int tx_irq; - - /* DMA stuff */ - u8 dma_rx_sync; - short dma_rx_lch; - u8 dma_tx_sync; - short dma_tx_lch; - - /* Completion queues */ - struct completion tx_irq_completion; - struct completion rx_irq_completion; - struct completion tx_dma_completion; - struct completion rx_dma_completion; - - /* Protect the field .free, while checking if the mcbsp is in use */ - spinlock_t lock; - struct omap_mcbsp_platform_data *pdata; - struct clk *iclk; - struct clk *fclk; -#ifdef CONFIG_ARCH_OMAP34XX - int dma_op_mode; - u16 max_tx_thres; - u16 max_rx_thres; -#endif -}; -extern struct omap_mcbsp **mcbsp_ptr; -extern int omap_mcbsp_count; - -int omap_mcbsp_init(void); -void omap_mcbsp_register_board_cfg(struct omap_mcbsp_platform_data *config, - int size); -void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg * config); -#ifdef CONFIG_ARCH_OMAP34XX -void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold); -void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold); -u16 omap_mcbsp_get_max_tx_threshold(unsigned int id); -u16 omap_mcbsp_get_max_rx_threshold(unsigned int id); -int omap_mcbsp_get_dma_op_mode(unsigned int id); -#else -static inline void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold) -{ } -static inline void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold) -{ } -static inline u16 omap_mcbsp_get_max_tx_threshold(unsigned int id) { return 0; } -static inline u16 omap_mcbsp_get_max_rx_threshold(unsigned int id) { return 0; } -static inline int omap_mcbsp_get_dma_op_mode(unsigned int id) { return 0; } -#endif -int omap_mcbsp_request(unsigned int id); -void omap_mcbsp_free(unsigned int id); -void omap_mcbsp_start(unsigned int id, int tx, int rx); -void omap_mcbsp_stop(unsigned int id, int tx, int rx); -void omap_mcbsp_xmit_word(unsigned int id, u32 word); -u32 omap_mcbsp_recv_word(unsigned int id); - -int omap_mcbsp_xmit_buffer(unsigned int id, dma_addr_t buffer, unsigned int length); -int omap_mcbsp_recv_buffer(unsigned int id, dma_addr_t buffer, unsigned int length); -int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word); -int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 * word); - - -/* SPI specific API */ -void omap_mcbsp_set_spi_mode(unsigned int id, const struct omap_mcbsp_spi_cfg * spi_cfg); - -/* Polled read/write functions */ -int omap_mcbsp_pollread(unsigned int id, u16 * buf); -int omap_mcbsp_pollwrite(unsigned int id, u16 buf); -int omap_mcbsp_set_io_type(unsigned int id, omap_mcbsp_io_type_t io_type); - -#endif diff --git a/arch/arm/plat-omap/include/mach/mcspi.h b/arch/arm/plat-omap/include/mach/mcspi.h deleted file mode 100644 index 1254e4945b6..00000000000 --- a/arch/arm/plat-omap/include/mach/mcspi.h +++ /dev/null @@ -1,15 +0,0 @@ -#ifndef _OMAP2_MCSPI_H -#define _OMAP2_MCSPI_H - -struct omap2_mcspi_platform_config { - unsigned short num_cs; -}; - -struct omap2_mcspi_device_config { - unsigned turbo_mode:1; - - /* Do we want one channel enabled at the same time? */ - unsigned single_channel:1; -}; - -#endif diff --git a/arch/arm/plat-omap/include/mach/memory.h b/arch/arm/plat-omap/include/mach/memory.h deleted file mode 100644 index 9ad41dc484c..00000000000 --- a/arch/arm/plat-omap/include/mach/memory.h +++ /dev/null @@ -1,96 +0,0 @@ -/* - * arch/arm/plat-omap/include/mach/memory.h - * - * Memory map for OMAP-1510 and 1610 - * - * Copyright (C) 2000 RidgeRun, Inc. - * Author: Greg Lonnon <glonnon@ridgerun.com> - * - * This file was derived from arch/arm/mach-intergrator/include/mach/memory.h - * Copyright (C) 1999 ARM Limited - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -#ifndef __ASM_ARCH_MEMORY_H -#define __ASM_ARCH_MEMORY_H - -/* - * Physical DRAM offset. - */ -#if defined(CONFIG_ARCH_OMAP1) -#define PHYS_OFFSET UL(0x10000000) -#elif defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \ - defined(CONFIG_ARCH_OMAP4) -#define PHYS_OFFSET UL(0x80000000) -#endif - -/* - * Bus address is physical address, except for OMAP-1510 Local Bus. - * OMAP-1510 bus address is translated into a Local Bus address if the - * OMAP bus type is lbus. We do the address translation based on the - * device overriding the defaults used in the dma-mapping API. - * Note that the is_lbus_device() test is not very efficient on 1510 - * because of the strncmp(). - */ -#ifdef CONFIG_ARCH_OMAP15XX - -/* - * OMAP-1510 Local Bus address offset - */ -#define OMAP1510_LB_OFFSET UL(0x30000000) - -#define virt_to_lbus(x) ((x) - PAGE_OFFSET + OMAP1510_LB_OFFSET) -#define lbus_to_virt(x) ((x) - OMAP1510_LB_OFFSET + PAGE_OFFSET) -#define is_lbus_device(dev) (cpu_is_omap15xx() && dev && (strncmp(dev_name(dev), "ohci", 4) == 0)) - -#define __arch_page_to_dma(dev, page) \ - ({ dma_addr_t __dma = page_to_phys(page); \ - if (is_lbus_device(dev)) \ - __dma = __dma - PHYS_OFFSET + OMAP1510_LB_OFFSET; \ - __dma; }) - -#define __arch_dma_to_virt(dev, addr) ({ (void *) (is_lbus_device(dev) ? \ - lbus_to_virt(addr) : \ - __phys_to_virt(addr)); }) - -#define __arch_virt_to_dma(dev, addr) ({ unsigned long __addr = (unsigned long)(addr); \ - (dma_addr_t) (is_lbus_device(dev) ? \ - virt_to_lbus(__addr) : \ - __virt_to_phys(__addr)); }) - -#endif /* CONFIG_ARCH_OMAP15XX */ - -/* Override the ARM default */ -#ifdef CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE - -#if (CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE == 0) -#undef CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE -#define CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE 2 -#endif - -#define CONSISTENT_DMA_SIZE \ - (((CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE + 1) & ~1) * 1024 * 1024) - -#endif - -#endif - diff --git a/arch/arm/plat-omap/include/mach/menelaus.h b/arch/arm/plat-omap/include/mach/menelaus.h deleted file mode 100644 index 3122bf68c7c..00000000000 --- a/arch/arm/plat-omap/include/mach/menelaus.h +++ /dev/null @@ -1,49 +0,0 @@ -/* - * arch/arm/plat-omap/include/mach/menelaus.h - * - * Functions to access Menelaus power management chip - */ - -#ifndef __ASM_ARCH_MENELAUS_H -#define __ASM_ARCH_MENELAUS_H - -struct device; - -struct menelaus_platform_data { - int (* late_init)(struct device *dev); -}; - -extern int menelaus_register_mmc_callback(void (*callback)(void *data, u8 card_mask), - void *data); -extern void menelaus_unregister_mmc_callback(void); -extern int menelaus_set_mmc_opendrain(int slot, int enable); -extern int menelaus_set_mmc_slot(int slot, int enable, int power, int cd_on); - -extern int menelaus_set_vmem(unsigned int mV); -extern int menelaus_set_vio(unsigned int mV); -extern int menelaus_set_vmmc(unsigned int mV); -extern int menelaus_set_vaux(unsigned int mV); -extern int menelaus_set_vdcdc(int dcdc, unsigned int mV); -extern int menelaus_set_slot_sel(int enable); -extern int menelaus_get_slot_pin_states(void); -extern int menelaus_set_vcore_sw(unsigned int mV); -extern int menelaus_set_vcore_hw(unsigned int roof_mV, unsigned int floor_mV); - -#define EN_VPLL_SLEEP (1 << 7) -#define EN_VMMC_SLEEP (1 << 6) -#define EN_VAUX_SLEEP (1 << 5) -#define EN_VIO_SLEEP (1 << 4) -#define EN_VMEM_SLEEP (1 << 3) -#define EN_DC3_SLEEP (1 << 2) -#define EN_DC2_SLEEP (1 << 1) -#define EN_VC_SLEEP (1 << 0) - -extern int menelaus_set_regulator_sleep(int enable, u32 val); - -#if defined(CONFIG_ARCH_OMAP24XX) && defined(CONFIG_MENELAUS) -#define omap_has_menelaus() 1 -#else -#define omap_has_menelaus() 0 -#endif - -#endif diff --git a/arch/arm/plat-omap/include/mach/mmc.h b/arch/arm/plat-omap/include/mach/mmc.h deleted file mode 100644 index 7229b959330..00000000000 --- a/arch/arm/plat-omap/include/mach/mmc.h +++ /dev/null @@ -1,157 +0,0 @@ -/* - * MMC definitions for OMAP2 - * - * Copyright (C) 2006 Nokia Corporation - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef __OMAP2_MMC_H -#define __OMAP2_MMC_H - -#include <linux/types.h> -#include <linux/device.h> -#include <linux/mmc/host.h> - -#include <mach/board.h> - -#define OMAP15XX_NR_MMC 1 -#define OMAP16XX_NR_MMC 2 -#define OMAP1_MMC_SIZE 0x080 -#define OMAP1_MMC1_BASE 0xfffb7800 -#define OMAP1_MMC2_BASE 0xfffb7c00 /* omap16xx only */ - -#define OMAP24XX_NR_MMC 2 -#define OMAP34XX_NR_MMC 3 -#define OMAP44XX_NR_MMC 5 -#define OMAP2420_MMC_SIZE OMAP1_MMC_SIZE -#define OMAP3_HSMMC_SIZE 0x200 -#define OMAP4_HSMMC_SIZE 0x1000 -#define OMAP2_MMC1_BASE 0x4809c000 -#define OMAP2_MMC2_BASE 0x480b4000 -#define OMAP3_MMC3_BASE 0x480ad000 -#define OMAP4_MMC4_BASE 0x480d1000 -#define OMAP4_MMC5_BASE 0x480d5000 -#define OMAP4_MMC_REG_OFFSET 0x100 -#define HSMMC5 (1 << 4) -#define HSMMC4 (1 << 3) -#define HSMMC3 (1 << 2) -#define HSMMC2 (1 << 1) -#define HSMMC1 (1 << 0) - -#define OMAP_MMC_MAX_SLOTS 2 - -struct omap_mmc_platform_data { - /* back-link to device */ - struct device *dev; - - /* number of slots per controller */ - unsigned nr_slots:2; - - /* set if your board has components or wiring that limits the - * maximum frequency on the MMC bus */ - unsigned int max_freq; - - /* switch the bus to a new slot */ - int (* switch_slot)(struct device *dev, int slot); - /* initialize board-specific MMC functionality, can be NULL if - * not supported */ - int (* init)(struct device *dev); - void (* cleanup)(struct device *dev); - void (* shutdown)(struct device *dev); - - /* To handle board related suspend/resume functionality for MMC */ - int (*suspend)(struct device *dev, int slot); - int (*resume)(struct device *dev, int slot); - - /* Return context loss count due to PM states changing */ - int (*get_context_loss_count)(struct device *dev); - - u64 dma_mask; - - struct omap_mmc_slot_data { - - /* 4 wire signaling is optional, and is used for SD/SDIO/HSMMC; - * 8 wire signaling is also optional, and is used with HSMMC - */ - u8 wires; - - /* - * nomux means "standard" muxing is wrong on this board, and - * that board-specific code handled it before common init logic. - */ - unsigned nomux:1; - - /* switch pin can be for card detect (default) or card cover */ - unsigned cover:1; - - /* use the internal clock */ - unsigned internal_clock:1; - - /* nonremovable e.g. eMMC */ - unsigned nonremovable:1; - - /* Try to sleep or power off when possible */ - unsigned power_saving:1; - - int switch_pin; /* gpio (card detect) */ - int gpio_wp; /* gpio (write protect) */ - - int (* set_bus_mode)(struct device *dev, int slot, int bus_mode); - int (* set_power)(struct device *dev, int slot, int power_on, int vdd); - int (* get_ro)(struct device *dev, int slot); - int (*set_sleep)(struct device *dev, int slot, int sleep, - int vdd, int cardsleep); - - /* return MMC cover switch state, can be NULL if not supported. - * - * possible return values: - * 0 - closed - * 1 - open - */ - int (* get_cover_state)(struct device *dev, int slot); - - const char *name; - u32 ocr_mask; - - /* Card detection IRQs */ - int card_detect_irq; - int (* card_detect)(int irq); - - unsigned int ban_openended:1; - - } slots[OMAP_MMC_MAX_SLOTS]; -}; - -/* called from board-specific card detection service routine */ -extern void omap_mmc_notify_cover_event(struct device *dev, int slot, int is_closed); - -#if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) || \ - defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE) -void omap1_init_mmc(struct omap_mmc_platform_data **mmc_data, - int nr_controllers); -void omap2_init_mmc(struct omap_mmc_platform_data **mmc_data, - int nr_controllers); -int omap_mmc_add(const char *name, int id, unsigned long base, - unsigned long size, unsigned int irq, - struct omap_mmc_platform_data *data); -#else -static inline void omap1_init_mmc(struct omap_mmc_platform_data **mmc_data, - int nr_controllers) -{ -} -static inline void omap2_init_mmc(struct omap_mmc_platform_data **mmc_data, - int nr_controllers) -{ -} -static inline int omap_mmc_add(const char *name, int id, unsigned long base, - unsigned long size, unsigned int irq, - struct omap_mmc_platform_data *data) -{ - return 0; -} - -#endif -#endif diff --git a/arch/arm/plat-omap/include/mach/mtd-xip.h b/arch/arm/plat-omap/include/mach/mtd-xip.h deleted file mode 100644 index f82a8dcaad9..00000000000 --- a/arch/arm/plat-omap/include/mach/mtd-xip.h +++ /dev/null @@ -1,61 +0,0 @@ -/* - * MTD primitives for XIP support. Architecture specific functions. - * - * Do not include this file directly. It's included from linux/mtd/xip.h - * - * Author: Vladimir Barinov <vbarinov@embeddedalley.com> - * - * (c) 2005 MontaVista Software, Inc. This file is licensed under the - * terms of the GNU General Public License version 2. This program is - * licensed "as is" without any warranty of any kind, whether express or - * implied. - */ - -#ifndef __ARCH_OMAP_MTD_XIP_H__ -#define __ARCH_OMAP_MTD_XIP_H__ - -#include <mach/hardware.h> -#define OMAP_MPU_TIMER_BASE (0xfffec500) -#define OMAP_MPU_TIMER_OFFSET 0x100 - -typedef struct { - u32 cntl; /* CNTL_TIMER, R/W */ - u32 load_tim; /* LOAD_TIM, W */ - u32 read_tim; /* READ_TIM, R */ -} xip_omap_mpu_timer_regs_t; - -#define xip_omap_mpu_timer_base(n) \ -((volatile xip_omap_mpu_timer_regs_t*)OMAP1_IO_ADDRESS(OMAP_MPU_TIMER_BASE + \ - (n)*OMAP_MPU_TIMER_OFFSET)) - -static inline unsigned long xip_omap_mpu_timer_read(int nr) -{ - volatile xip_omap_mpu_timer_regs_t* timer = xip_omap_mpu_timer_base(nr); - return timer->read_tim; -} - -#define xip_irqpending() \ - (omap_readl(OMAP_IH1_ITR) & ~omap_readl(OMAP_IH1_MIR)) -#define xip_currtime() (~xip_omap_mpu_timer_read(0)) - -/* - * It's permitted to do approxmation for xip_elapsed_since macro - * (see linux/mtd/xip.h) - */ - -#ifdef CONFIG_MACH_OMAP_PERSEUS2 -#define xip_elapsed_since(x) (signed)((~xip_omap_mpu_timer_read(0) - (x)) / 7) -#else -#define xip_elapsed_since(x) (signed)((~xip_omap_mpu_timer_read(0) - (x)) / 6) -#endif - -/* - * xip_cpu_idle() is used when waiting for a delay equal or larger than - * the system timer tick period. This should put the CPU into idle mode - * to save power and to be woken up only when some interrupts are pending. - * As above, this should not rely upon standard kernel code. - */ - -#define xip_cpu_idle() asm volatile ("mcr p15, 0, %0, c7, c0, 4" :: "r" (1)) - -#endif /* __ARCH_OMAP_MTD_XIP_H__ */ diff --git a/arch/arm/plat-omap/include/mach/mux.h b/arch/arm/plat-omap/include/mach/mux.h deleted file mode 100644 index 0f49d2d563d..00000000000 --- a/arch/arm/plat-omap/include/mach/mux.h +++ /dev/null @@ -1,914 +0,0 @@ -/* - * arch/arm/plat-omap/include/mach/mux.h - * - * Table of the Omap register configurations for the FUNC_MUX and - * PULL_DWN combinations. - * - * Copyright (C) 2004 - 2008 Texas Instruments Inc. - * Copyright (C) 2003 - 2008 Nokia Corporation - * - * Written by Tony Lindgren - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - * - * NOTE: Please use the following naming style for new pin entries. - * For example, W8_1610_MMC2_DAT0, where: - * - W8 = ball - * - 1610 = 1510 or 1610, none if common for both 1510 and 1610 - * - MMC2_DAT0 = function - */ - -#ifndef __ASM_ARCH_MUX_H -#define __ASM_ARCH_MUX_H - -#define PU_PD_SEL_NA 0 /* No pu_pd reg available */ -#define PULL_DWN_CTRL_NA 0 /* No pull-down control needed */ - -#ifdef CONFIG_OMAP_MUX_DEBUG -#define MUX_REG(reg, mode_offset, mode) .mux_reg_name = "FUNC_MUX_CTRL_"#reg, \ - .mux_reg = FUNC_MUX_CTRL_##reg, \ - .mask_offset = mode_offset, \ - .mask = mode, - -#define PULL_REG(reg, bit, status) .pull_name = "PULL_DWN_CTRL_"#reg, \ - .pull_reg = PULL_DWN_CTRL_##reg, \ - .pull_bit = bit, \ - .pull_val = status, - -#define PU_PD_REG(reg, status) .pu_pd_name = "PU_PD_SEL_"#reg, \ - .pu_pd_reg = PU_PD_SEL_##reg, \ - .pu_pd_val = status, - -#define MUX_REG_730(reg, mode_offset, mode) .mux_reg_name = "OMAP730_IO_CONF_"#reg, \ - .mux_reg = OMAP730_IO_CONF_##reg, \ - .mask_offset = mode_offset, \ - .mask = mode, - -#define PULL_REG_730(reg, bit, status) .pull_name = "OMAP730_IO_CONF_"#reg, \ - .pull_reg = OMAP730_IO_CONF_##reg, \ - .pull_bit = bit, \ - .pull_val = status, - -#define MUX_REG_850(reg, mode_offset, mode) .mux_reg_name = "OMAP850_IO_CONF_"#reg, \ - .mux_reg = OMAP850_IO_CONF_##reg, \ - .mask_offset = mode_offset, \ - .mask = mode, - -#define PULL_REG_850(reg, bit, status) .pull_name = "OMAP850_IO_CONF_"#reg, \ - .pull_reg = OMAP850_IO_CONF_##reg, \ - .pull_bit = bit, \ - .pull_val = status, - -#else - -#define MUX_REG(reg, mode_offset, mode) .mux_reg = FUNC_MUX_CTRL_##reg, \ - .mask_offset = mode_offset, \ - .mask = mode, - -#define PULL_REG(reg, bit, status) .pull_reg = PULL_DWN_CTRL_##reg, \ - .pull_bit = bit, \ - .pull_val = status, - -#define PU_PD_REG(reg, status) .pu_pd_reg = PU_PD_SEL_##reg, \ - .pu_pd_val = status, - -#define MUX_REG_730(reg, mode_offset, mode) \ - .mux_reg = OMAP730_IO_CONF_##reg, \ - .mask_offset = mode_offset, \ - .mask = mode, - -#define PULL_REG_730(reg, bit, status) .pull_reg = OMAP730_IO_CONF_##reg, \ - .pull_bit = bit, \ - .pull_val = status, - -#define MUX_REG_850(reg, mode_offset, mode) \ - .mux_reg = OMAP850_IO_CONF_##reg, \ - .mask_offset = mode_offset, \ - .mask = mode, - -#define PULL_REG_850(reg, bit, status) .pull_reg = OMAP850_IO_CONF_##reg, \ - .pull_bit = bit, \ - .pull_val = status, - -#endif /* CONFIG_OMAP_MUX_DEBUG */ - -#define MUX_CFG(desc, mux_reg, mode_offset, mode, \ - pull_reg, pull_bit, pull_status, \ - pu_pd_reg, pu_pd_status, debug_status) \ -{ \ - .name = desc, \ - .debug = debug_status, \ - MUX_REG(mux_reg, mode_offset, mode) \ - PULL_REG(pull_reg, pull_bit, pull_status) \ - PU_PD_REG(pu_pd_reg, pu_pd_status) \ -}, - - -/* - * OMAP730/850 has a slightly different config for the pin mux. - * - config regs are the OMAP730_IO_CONF_x regs (see omap730.h) regs and - * not the FUNC_MUX_CTRL_x regs from hardware.h - * - for pull-up/down, only has one enable bit which is is in the same register - * as mux config - */ -#define MUX_CFG_730(desc, mux_reg, mode_offset, mode, \ - pull_bit, pull_status, debug_status)\ -{ \ - .name = desc, \ - .debug = debug_status, \ - MUX_REG_730(mux_reg, mode_offset, mode) \ - PULL_REG_730(mux_reg, pull_bit, pull_status) \ - PU_PD_REG(NA, 0) \ -}, - -#define MUX_CFG_850(desc, mux_reg, mode_offset, mode, \ - pull_bit, pull_status, debug_status)\ -{ \ - .name = desc, \ - .debug = debug_status, \ - MUX_REG_850(mux_reg, mode_offset, mode) \ - PULL_REG_850(mux_reg, pull_bit, pull_status) \ - PU_PD_REG(NA, 0) \ -}, - - -#define MUX_CFG_24XX(desc, reg_offset, mode, \ - pull_en, pull_mode, dbg) \ -{ \ - .name = desc, \ - .debug = dbg, \ - .mux_reg = reg_offset, \ - .mask = mode, \ - .pull_val = pull_en, \ - .pu_pd_val = pull_mode, \ -}, - -/* 24xx/34xx mux bit defines */ -#define OMAP2_PULL_ENA (1 << 3) -#define OMAP2_PULL_UP (1 << 4) -#define OMAP2_ALTELECTRICALSEL (1 << 5) - -/* 34xx specific mux bit defines */ -#define OMAP3_INPUT_EN (1 << 8) -#define OMAP3_OFF_EN (1 << 9) -#define OMAP3_OFFOUT_EN (1 << 10) -#define OMAP3_OFFOUT_VAL (1 << 11) -#define OMAP3_OFF_PULL_EN (1 << 12) -#define OMAP3_OFF_PULL_UP (1 << 13) -#define OMAP3_WAKEUP_EN (1 << 14) - -/* 34xx mux mode options for each pin. See TRM for options */ -#define OMAP34XX_MUX_MODE0 0 -#define OMAP34XX_MUX_MODE1 1 -#define OMAP34XX_MUX_MODE2 2 -#define OMAP34XX_MUX_MODE3 3 -#define OMAP34XX_MUX_MODE4 4 -#define OMAP34XX_MUX_MODE5 5 -#define OMAP34XX_MUX_MODE6 6 -#define OMAP34XX_MUX_MODE7 7 - -/* 34xx active pin states */ -#define OMAP34XX_PIN_OUTPUT 0 -#define OMAP34XX_PIN_INPUT OMAP3_INPUT_EN -#define OMAP34XX_PIN_INPUT_PULLUP (OMAP2_PULL_ENA | OMAP3_INPUT_EN \ - | OMAP2_PULL_UP) -#define OMAP34XX_PIN_INPUT_PULLDOWN (OMAP2_PULL_ENA | OMAP3_INPUT_EN) - -/* 34xx off mode states */ -#define OMAP34XX_PIN_OFF_NONE 0 -#define OMAP34XX_PIN_OFF_OUTPUT_HIGH (OMAP3_OFF_EN | OMAP3_OFFOUT_EN \ - | OMAP3_OFFOUT_VAL) -#define OMAP34XX_PIN_OFF_OUTPUT_LOW (OMAP3_OFF_EN | OMAP3_OFFOUT_EN) -#define OMAP34XX_PIN_OFF_INPUT_PULLUP (OMAP3_OFF_EN | OMAP3_OFF_PULL_EN \ - | OMAP3_OFF_PULL_UP) -#define OMAP34XX_PIN_OFF_INPUT_PULLDOWN (OMAP3_OFF_EN | OMAP3_OFF_PULL_EN) -#define OMAP34XX_PIN_OFF_WAKEUPENABLE OMAP3_WAKEUP_EN - -#define MUX_CFG_34XX(desc, reg_offset, mux_value) { \ - .name = desc, \ - .debug = 0, \ - .mux_reg = reg_offset, \ - .mux_val = mux_value \ -}, - -struct pin_config { - char *name; - const unsigned int mux_reg; - unsigned char debug; - -#if defined(CONFIG_ARCH_OMAP34XX) - u16 mux_val; /* Wake-up, off mode, pull, mux mode */ -#endif - -#if defined(CONFIG_ARCH_OMAP1) || defined(CONFIG_ARCH_OMAP24XX) - const unsigned char mask_offset; - const unsigned char mask; - - const char *pull_name; - const unsigned int pull_reg; - const unsigned char pull_val; - const unsigned char pull_bit; - - const char *pu_pd_name; - const unsigned int pu_pd_reg; - const unsigned char pu_pd_val; -#endif - -#if defined(CONFIG_OMAP_MUX_DEBUG) || defined(CONFIG_OMAP_MUX_WARNINGS) - const char *mux_reg_name; -#endif - -}; - -enum omap730_index { - /* OMAP 730 keyboard */ - E2_730_KBR0, - J7_730_KBR1, - E1_730_KBR2, - F3_730_KBR3, - D2_730_KBR4, - C2_730_KBC0, - D3_730_KBC1, - E4_730_KBC2, - F4_730_KBC3, - E3_730_KBC4, - - /* USB */ - AA17_730_USB_DM, - W16_730_USB_PU_EN, - W17_730_USB_VBUSI, -}; - -enum omap850_index { - /* OMAP 850 keyboard */ - E2_850_KBR0, - J7_850_KBR1, - E1_850_KBR2, - F3_850_KBR3, - D2_850_KBR4, - C2_850_KBC0, - D3_850_KBC1, - E4_850_KBC2, - F4_850_KBC3, - E3_850_KBC4, - - /* USB */ - AA17_850_USB_DM, - W16_850_USB_PU_EN, - W17_850_USB_VBUSI, -}; - - -enum omap1xxx_index { - /* UART1 (BT_UART_GATING)*/ - UART1_TX = 0, - UART1_RTS, - - /* UART2 (COM_UART_GATING)*/ - UART2_TX, - UART2_RX, - UART2_CTS, - UART2_RTS, - - /* UART3 (GIGA_UART_GATING) */ - UART3_TX, - UART3_RX, - UART3_CTS, - UART3_RTS, - UART3_CLKREQ, - UART3_BCLK, /* 12MHz clock out */ - Y15_1610_UART3_RTS, - - /* PWT & PWL */ - PWT, - PWL, - - /* USB master generic */ - R18_USB_VBUS, - R18_1510_USB_GPIO0, - W4_USB_PUEN, - W4_USB_CLKO, - W4_USB_HIGHZ, - W4_GPIO58, - - /* USB1 master */ - USB1_SUSP, - USB1_SEO, - W13_1610_USB1_SE0, - USB1_TXEN, - USB1_TXD, - USB1_VP, - USB1_VM, - USB1_RCV, - USB1_SPEED, - R13_1610_USB1_SPEED, - R13_1710_USB1_SE0, - - /* USB2 master */ - USB2_SUSP, - USB2_VP, - USB2_TXEN, - USB2_VM, - USB2_RCV, - USB2_SEO, - USB2_TXD, - - /* OMAP-1510 GPIO */ - R18_1510_GPIO0, - R19_1510_GPIO1, - M14_1510_GPIO2, - - /* OMAP1610 GPIO */ - P18_1610_GPIO3, - Y15_1610_GPIO17, - - /* OMAP-1710 GPIO */ - R18_1710_GPIO0, - V2_1710_GPIO10, - N21_1710_GPIO14, - W15_1710_GPIO40, - - /* MPUIO */ - MPUIO2, - N15_1610_MPUIO2, - MPUIO4, - MPUIO5, - T20_1610_MPUIO5, - W11_1610_MPUIO6, - V10_1610_MPUIO7, - W11_1610_MPUIO9, - V10_1610_MPUIO10, - W10_1610_MPUIO11, - E20_1610_MPUIO13, - U20_1610_MPUIO14, - E19_1610_MPUIO15, - - /* MCBSP2 */ - MCBSP2_CLKR, - MCBSP2_CLKX, - MCBSP2_DR, - MCBSP2_DX, - MCBSP2_FSR, - MCBSP2_FSX, - - /* MCBSP3 */ - MCBSP3_CLKX, - - /* Misc ballouts */ - BALLOUT_V8_ARMIO3, - N20_HDQ, - - /* OMAP-1610 MMC2 */ - W8_1610_MMC2_DAT0, - V8_1610_MMC2_DAT1, - W15_1610_MMC2_DAT2, - R10_1610_MMC2_DAT3, - Y10_1610_MMC2_CLK, - Y8_1610_MMC2_CMD, - V9_1610_MMC2_CMDDIR, - V5_1610_MMC2_DATDIR0, - W19_1610_MMC2_DATDIR1, - R18_1610_MMC2_CLKIN, - - /* OMAP-1610 External Trace Interface */ - M19_1610_ETM_PSTAT0, - L15_1610_ETM_PSTAT1, - L18_1610_ETM_PSTAT2, - L19_1610_ETM_D0, - J19_1610_ETM_D6, - J18_1610_ETM_D7, - - /* OMAP16XX GPIO */ - P20_1610_GPIO4, - V9_1610_GPIO7, - W8_1610_GPIO9, - N20_1610_GPIO11, - N19_1610_GPIO13, - P10_1610_GPIO22, - V5_1610_GPIO24, - AA20_1610_GPIO_41, - W19_1610_GPIO48, - M7_1610_GPIO62, - V14_16XX_GPIO37, - R9_16XX_GPIO18, - L14_16XX_GPIO49, - - /* OMAP-1610 uWire */ - V19_1610_UWIRE_SCLK, - U18_1610_UWIRE_SDI, - W21_1610_UWIRE_SDO, - N14_1610_UWIRE_CS0, - P15_1610_UWIRE_CS3, - N15_1610_UWIRE_CS1, - - /* OMAP-1610 SPI */ - U19_1610_SPIF_SCK, - U18_1610_SPIF_DIN, - P20_1610_SPIF_DIN, - W21_1610_SPIF_DOUT, - R18_1610_SPIF_DOUT, - N14_1610_SPIF_CS0, - N15_1610_SPIF_CS1, - T19_1610_SPIF_CS2, - P15_1610_SPIF_CS3, - - /* OMAP-1610 Flash */ - L3_1610_FLASH_CS2B_OE, - M8_1610_FLASH_CS2B_WE, - - /* First MMC */ - MMC_CMD, - MMC_DAT1, - MMC_DAT2, - MMC_DAT0, - MMC_CLK, - MMC_DAT3, - - /* OMAP-1710 MMC CMDDIR and DATDIR0 */ - M15_1710_MMC_CLKI, - P19_1710_MMC_CMDDIR, - P20_1710_MMC_DATDIR0, - - /* OMAP-1610 USB0 alternate pin configuration */ - W9_USB0_TXEN, - AA9_USB0_VP, - Y5_USB0_RCV, - R9_USB0_VM, - V6_USB0_TXD, - W5_USB0_SE0, - V9_USB0_SPEED, - V9_USB0_SUSP, - - /* USB2 */ - W9_USB2_TXEN, - AA9_USB2_VP, - Y5_USB2_RCV, - R9_USB2_VM, - V6_USB2_TXD, - W5_USB2_SE0, - - /* 16XX UART */ - R13_1610_UART1_TX, - V14_16XX_UART1_RX, - R14_1610_UART1_CTS, - AA15_1610_UART1_RTS, - R9_16XX_UART2_RX, - L14_16XX_UART3_RX, - - /* I2C OMAP-1610 */ - I2C_SCL, - I2C_SDA, - - /* Keypad */ - F18_1610_KBC0, - D20_1610_KBC1, - D19_1610_KBC2, - E18_1610_KBC3, - C21_1610_KBC4, - G18_1610_KBR0, - F19_1610_KBR1, - H14_1610_KBR2, - E20_1610_KBR3, - E19_1610_KBR4, - N19_1610_KBR5, - - /* Power management */ - T20_1610_LOW_PWR, - - /* MCLK Settings */ - V5_1710_MCLK_ON, - V5_1710_MCLK_OFF, - R10_1610_MCLK_ON, - R10_1610_MCLK_OFF, - - /* CompactFlash controller */ - P11_1610_CF_CD2, - R11_1610_CF_IOIS16, - V10_1610_CF_IREQ, - W10_1610_CF_RESET, - W11_1610_CF_CD1, - - /* parallel camera */ - J15_1610_CAM_LCLK, - J18_1610_CAM_D7, - J19_1610_CAM_D6, - J14_1610_CAM_D5, - K18_1610_CAM_D4, - K19_1610_CAM_D3, - K15_1610_CAM_D2, - K14_1610_CAM_D1, - L19_1610_CAM_D0, - L18_1610_CAM_VS, - L15_1610_CAM_HS, - M19_1610_CAM_RSTZ, - Y15_1610_CAM_OUTCLK, - - /* serial camera */ - H19_1610_CAM_EXCLK, - Y12_1610_CCP_CLKP, - W13_1610_CCP_CLKM, - W14_1610_CCP_DATAP, - Y14_1610_CCP_DATAM, - -}; - -enum omap24xx_index { - /* 24xx I2C */ - M19_24XX_I2C1_SCL, - L15_24XX_I2C1_SDA, - J15_24XX_I2C2_SCL, - H19_24XX_I2C2_SDA, - - /* 24xx Menelaus interrupt */ - W19_24XX_SYS_NIRQ, - - /* 24xx clock */ - W14_24XX_SYS_CLKOUT, - - /* 24xx GPMC chipselects, wait pin monitoring */ - E2_GPMC_NCS2, - L2_GPMC_NCS7, - L3_GPMC_WAIT0, - N7_GPMC_WAIT1, - M1_GPMC_WAIT2, - P1_GPMC_WAIT3, - - /* 242X McBSP */ - Y15_24XX_MCBSP2_CLKX, - R14_24XX_MCBSP2_FSX, - W15_24XX_MCBSP2_DR, - V15_24XX_MCBSP2_DX, - - /* 24xx GPIO */ - M21_242X_GPIO11, - P21_242X_GPIO12, - AA10_242X_GPIO13, - AA6_242X_GPIO14, - AA4_242X_GPIO15, - Y11_242X_GPIO16, - AA12_242X_GPIO17, - AA8_242X_GPIO58, - Y20_24XX_GPIO60, - W4__24XX_GPIO74, - N15_24XX_GPIO85, - M15_24XX_GPIO92, - P20_24XX_GPIO93, - P18_24XX_GPIO95, - M18_24XX_GPIO96, - L14_24XX_GPIO97, - J15_24XX_GPIO99, - V14_24XX_GPIO117, - P14_24XX_GPIO125, - - /* 242x DBG GPIO */ - V4_242X_GPIO49, - W2_242X_GPIO50, - U4_242X_GPIO51, - V3_242X_GPIO52, - V2_242X_GPIO53, - V6_242X_GPIO53, - T4_242X_GPIO54, - Y4_242X_GPIO54, - T3_242X_GPIO55, - U2_242X_GPIO56, - - /* 24xx external DMA requests */ - AA10_242X_DMAREQ0, - AA6_242X_DMAREQ1, - E4_242X_DMAREQ2, - G4_242X_DMAREQ3, - D3_242X_DMAREQ4, - E3_242X_DMAREQ5, - - /* UART3 */ - K15_24XX_UART3_TX, - K14_24XX_UART3_RX, - - /* MMC/SDIO */ - G19_24XX_MMC_CLKO, - H18_24XX_MMC_CMD, - F20_24XX_MMC_DAT0, - H14_24XX_MMC_DAT1, - E19_24XX_MMC_DAT2, - D19_24XX_MMC_DAT3, - F19_24XX_MMC_DAT_DIR0, - E20_24XX_MMC_DAT_DIR1, - F18_24XX_MMC_DAT_DIR2, - E18_24XX_MMC_DAT_DIR3, - G18_24XX_MMC_CMD_DIR, - H15_24XX_MMC_CLKI, - - /* Full speed USB */ - J20_24XX_USB0_PUEN, - J19_24XX_USB0_VP, - K20_24XX_USB0_VM, - J18_24XX_USB0_RCV, - K19_24XX_USB0_TXEN, - J14_24XX_USB0_SE0, - K18_24XX_USB0_DAT, - - N14_24XX_USB1_SE0, - W12_24XX_USB1_SE0, - P15_24XX_USB1_DAT, - R13_24XX_USB1_DAT, - W20_24XX_USB1_TXEN, - P13_24XX_USB1_TXEN, - V19_24XX_USB1_RCV, - V12_24XX_USB1_RCV, - - AA10_24XX_USB2_SE0, - Y11_24XX_USB2_DAT, - AA12_24XX_USB2_TXEN, - AA6_24XX_USB2_RCV, - AA4_24XX_USB2_TLLSE0, - - /* Keypad GPIO*/ - T19_24XX_KBR0, - R19_24XX_KBR1, - V18_24XX_KBR2, - M21_24XX_KBR3, - E5__24XX_KBR4, - M18_24XX_KBR5, - R20_24XX_KBC0, - M14_24XX_KBC1, - H19_24XX_KBC2, - V17_24XX_KBC3, - P21_24XX_KBC4, - L14_24XX_KBC5, - N19_24XX_KBC6, - - /* 24xx Menelaus Keypad GPIO */ - B3__24XX_KBR5, - AA4_24XX_KBC2, - B13_24XX_KBC6, - - /* 2430 USB */ - AD9_2430_USB0_PUEN, - Y11_2430_USB0_VP, - AD7_2430_USB0_VM, - AE7_2430_USB0_RCV, - AD4_2430_USB0_TXEN, - AF9_2430_USB0_SE0, - AE6_2430_USB0_DAT, - AD24_2430_USB1_SE0, - AB24_2430_USB1_RCV, - Y25_2430_USB1_TXEN, - AA26_2430_USB1_DAT, - - /* 2430 HS-USB */ - AD9_2430_USB0HS_DATA3, - Y11_2430_USB0HS_DATA4, - AD7_2430_USB0HS_DATA5, - AE7_2430_USB0HS_DATA6, - AD4_2430_USB0HS_DATA2, - AF9_2430_USB0HS_DATA0, - AE6_2430_USB0HS_DATA1, - AE8_2430_USB0HS_CLK, - AD8_2430_USB0HS_DIR, - AE5_2430_USB0HS_STP, - AE9_2430_USB0HS_NXT, - AC7_2430_USB0HS_DATA7, - - /* 2430 McBSP */ - AD6_2430_MCBSP_CLKS, - - AB2_2430_MCBSP1_CLKR, - AD5_2430_MCBSP1_FSR, - AA1_2430_MCBSP1_DX, - AF3_2430_MCBSP1_DR, - AB3_2430_MCBSP1_FSX, - Y9_2430_MCBSP1_CLKX, - - AC10_2430_MCBSP2_FSX, - AD16_2430_MCBSP2_CLX, - AE13_2430_MCBSP2_DX, - AD13_2430_MCBSP2_DR, - AC10_2430_MCBSP2_FSX_OFF, - AD16_2430_MCBSP2_CLX_OFF, - AE13_2430_MCBSP2_DX_OFF, - AD13_2430_MCBSP2_DR_OFF, - - AC9_2430_MCBSP3_CLKX, - AE4_2430_MCBSP3_FSX, - AE2_2430_MCBSP3_DR, - AF4_2430_MCBSP3_DX, - - N3_2430_MCBSP4_CLKX, - AD23_2430_MCBSP4_DR, - AB25_2430_MCBSP4_DX, - AC25_2430_MCBSP4_FSX, - - AE16_2430_MCBSP5_CLKX, - AF12_2430_MCBSP5_FSX, - K7_2430_MCBSP5_DX, - M1_2430_MCBSP5_DR, - - /* 2430 McSPI*/ - Y18_2430_MCSPI1_CLK, - AD15_2430_MCSPI1_SIMO, - AE17_2430_MCSPI1_SOMI, - U1_2430_MCSPI1_CS0, - - /* Touchscreen GPIO */ - AF19_2430_GPIO_85, - -}; - -enum omap34xx_index { - /* 34xx I2C */ - K21_34XX_I2C1_SCL, - J21_34XX_I2C1_SDA, - AF15_34XX_I2C2_SCL, - AE15_34XX_I2C2_SDA, - AF14_34XX_I2C3_SCL, - AG14_34XX_I2C3_SDA, - AD26_34XX_I2C4_SCL, - AE26_34XX_I2C4_SDA, - - /* PHY - HSUSB: 12-pin ULPI PHY: Port 1*/ - Y8_3430_USB1HS_PHY_CLK, - Y9_3430_USB1HS_PHY_STP, - AA14_3430_USB1HS_PHY_DIR, - AA11_3430_USB1HS_PHY_NXT, - W13_3430_USB1HS_PHY_DATA0, - W12_3430_USB1HS_PHY_DATA1, - W11_3430_USB1HS_PHY_DATA2, - Y11_3430_USB1HS_PHY_DATA3, - W9_3430_USB1HS_PHY_DATA4, - Y12_3430_USB1HS_PHY_DATA5, - W8_3430_USB1HS_PHY_DATA6, - Y13_3430_USB1HS_PHY_DATA7, - - /* PHY - HSUSB: 12-pin ULPI PHY: Port 2*/ - AA8_3430_USB2HS_PHY_CLK, - AA10_3430_USB2HS_PHY_STP, - AA9_3430_USB2HS_PHY_DIR, - AB11_3430_USB2HS_PHY_NXT, - AB10_3430_USB2HS_PHY_DATA0, - AB9_3430_USB2HS_PHY_DATA1, - W3_3430_USB2HS_PHY_DATA2, - T4_3430_USB2HS_PHY_DATA3, - T3_3430_USB2HS_PHY_DATA4, - R3_3430_USB2HS_PHY_DATA5, - R4_3430_USB2HS_PHY_DATA6, - T2_3430_USB2HS_PHY_DATA7, - - - /* TLL - HSUSB: 12-pin TLL Port 1*/ - Y8_3430_USB1HS_TLL_CLK, - Y9_3430_USB1HS_TLL_STP, - AA14_3430_USB1HS_TLL_DIR, - AA11_3430_USB1HS_TLL_NXT, - W13_3430_USB1HS_TLL_DATA0, - W12_3430_USB1HS_TLL_DATA1, - W11_3430_USB1HS_TLL_DATA2, - Y11_3430_USB1HS_TLL_DATA3, - W9_3430_USB1HS_TLL_DATA4, - Y12_3430_USB1HS_TLL_DATA5, - W8_3430_USB1HS_TLL_DATA6, - Y13_3430_USB1HS_TLL_DATA7, - - /* TLL - HSUSB: 12-pin TLL Port 2*/ - AA8_3430_USB2HS_TLL_CLK, - AA10_3430_USB2HS_TLL_STP, - AA9_3430_USB2HS_TLL_DIR, - AB11_3430_USB2HS_TLL_NXT, - AB10_3430_USB2HS_TLL_DATA0, - AB9_3430_USB2HS_TLL_DATA1, - W3_3430_USB2HS_TLL_DATA2, - T4_3430_USB2HS_TLL_DATA3, - T3_3430_USB2HS_TLL_DATA4, - R3_3430_USB2HS_TLL_DATA5, - R4_3430_USB2HS_TLL_DATA6, - T2_3430_USB2HS_TLL_DATA7, - - /* TLL - HSUSB: 12-pin TLL Port 3*/ - AA6_3430_USB3HS_TLL_CLK, - AB3_3430_USB3HS_TLL_STP, - AA3_3430_USB3HS_TLL_DIR, - Y3_3430_USB3HS_TLL_NXT, - AA5_3430_USB3HS_TLL_DATA0, - Y4_3430_USB3HS_TLL_DATA1, - Y5_3430_USB3HS_TLL_DATA2, - W5_3430_USB3HS_TLL_DATA3, - AB12_3430_USB3HS_TLL_DATA4, - AB13_3430_USB3HS_TLL_DATA5, - AA13_3430_USB3HS_TLL_DATA6, - AA12_3430_USB3HS_TLL_DATA7, - - /* PHY FSUSB: FS Serial for Port 1 (multiple PHY modes supported) */ - AF10_3430_USB1FS_PHY_MM1_RXDP, - AG9_3430_USB1FS_PHY_MM1_RXDM, - W13_3430_USB1FS_PHY_MM1_RXRCV, - W12_3430_USB1FS_PHY_MM1_TXSE0, - W11_3430_USB1FS_PHY_MM1_TXDAT, - Y11_3430_USB1FS_PHY_MM1_TXEN_N, - - /* PHY FSUSB: FS Serial for Port 2 (multiple PHY modes supported) */ - AF7_3430_USB2FS_PHY_MM2_RXDP, - AH7_3430_USB2FS_PHY_MM2_RXDM, - AB10_3430_USB2FS_PHY_MM2_RXRCV, - AB9_3430_USB2FS_PHY_MM2_TXSE0, - W3_3430_USB2FS_PHY_MM2_TXDAT, - T4_3430_USB2FS_PHY_MM2_TXEN_N, - - /* PHY FSUSB: FS Serial for Port 3 (multiple PHY modes supported) */ - AH3_3430_USB3FS_PHY_MM3_RXDP, - AE3_3430_USB3FS_PHY_MM3_RXDM, - AD1_3430_USB3FS_PHY_MM3_RXRCV, - AE1_3430_USB3FS_PHY_MM3_TXSE0, - AD2_3430_USB3FS_PHY_MM3_TXDAT, - AC1_3430_USB3FS_PHY_MM3_TXEN_N, - - /* 34xx GPIO - * - normally these are bidirectional, no internal pullup/pulldown - * - "_UP" suffix (GPIO3_UP) if internal pullup is configured - * - "_DOWN" suffix (GPIO3_DOWN) with internal pulldown - * - "_OUT" suffix (GPIO3_OUT) for output-only pins (unlike 24xx) - */ - AF26_34XX_GPIO0, - AF22_34XX_GPIO9, - AG9_34XX_GPIO23, - AH8_34XX_GPIO29, - U8_34XX_GPIO54_OUT, - U8_34XX_GPIO54_DOWN, - L8_34XX_GPIO63, - G25_34XX_GPIO86_OUT, - AG4_34XX_GPIO134_OUT, - AF4_34XX_GPIO135_OUT, - AE4_34XX_GPIO136_OUT, - AF6_34XX_GPIO140_UP, - AE6_34XX_GPIO141, - AF5_34XX_GPIO142, - AE5_34XX_GPIO143, - H19_34XX_GPIO164_OUT, - J25_34XX_GPIO170, - - /* OMAP3 SDRC CKE signals to SDR/DDR ram chips */ - H16_34XX_SDRC_CKE0, - H17_34XX_SDRC_CKE1, - - /* MMC1 */ - N28_3430_MMC1_CLK, - M27_3430_MMC1_CMD, - N27_3430_MMC1_DAT0, - N26_3430_MMC1_DAT1, - N25_3430_MMC1_DAT2, - P28_3430_MMC1_DAT3, - P27_3430_MMC1_DAT4, - P26_3430_MMC1_DAT5, - R27_3430_MMC1_DAT6, - R25_3430_MMC1_DAT7, - - /* MMC2 */ - AE2_3430_MMC2_CLK, - AG5_3430_MMC2_CMD, - AH5_3430_MMC2_DAT0, - AH4_3430_MMC2_DAT1, - AG4_3430_MMC2_DAT2, - AF4_3430_MMC2_DAT3, - - /* MMC3 */ - AF10_3430_MMC3_CLK, - AC3_3430_MMC3_CMD, - AE11_3430_MMC3_DAT0, - AH9_3430_MMC3_DAT1, - AF13_3430_MMC3_DAT2, - AF13_3430_MMC3_DAT3, - - /* SYS_NIRQ T2 INT1 */ - AF26_34XX_SYS_NIRQ, -}; - -struct omap_mux_cfg { - struct pin_config *pins; - unsigned long size; - int (*cfg_reg)(const struct pin_config *cfg); -}; - -#ifdef CONFIG_OMAP_MUX -/* setup pin muxing in Linux */ -extern int omap1_mux_init(void); -extern int omap2_mux_init(void); -extern int omap_mux_register(struct omap_mux_cfg *); -extern int omap_cfg_reg(unsigned long reg_cfg); -#else -/* boot loader does it all (no warnings from CONFIG_OMAP_MUX_WARNINGS) */ -static inline int omap1_mux_init(void) { return 0; } -static inline int omap2_mux_init(void) { return 0; } -static inline int omap_cfg_reg(unsigned long reg_cfg) { return 0; } -#endif - -#endif diff --git a/arch/arm/plat-omap/include/mach/nand.h b/arch/arm/plat-omap/include/mach/nand.h deleted file mode 100644 index 631a7bed1ee..00000000000 --- a/arch/arm/plat-omap/include/mach/nand.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * arch/arm/plat-omap/include/mach/nand.h - * - * Copyright (C) 2006 Micron Technology Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include <linux/mtd/partitions.h> - -struct omap_nand_platform_data { - unsigned int options; - int cs; - int gpio_irq; - struct mtd_partition *parts; - int nr_parts; - int (*nand_setup)(void __iomem *); - int (*dev_ready)(struct omap_nand_platform_data *); - int dma_channel; - void __iomem *gpmc_cs_baseaddr; - void __iomem *gpmc_baseaddr; -}; diff --git a/arch/arm/plat-omap/include/mach/omap-alsa.h b/arch/arm/plat-omap/include/mach/omap-alsa.h deleted file mode 100644 index bdf30a0f87f..00000000000 --- a/arch/arm/plat-omap/include/mach/omap-alsa.h +++ /dev/null @@ -1,123 +0,0 @@ -/* - * arch/arm/plat-omap/include/mach/omap-alsa.h - * - * Alsa Driver for AIC23 and TSC2101 codecs on OMAP platform boards. - * - * Copyright (C) 2006 Mika Laitio <lamikr@cc.jyu.fi> - * - * Copyright (C) 2005 Instituto Nokia de Tecnologia - INdT - Manaus Brazil - * Written by Daniel Petrini, David Cohen, Anderson Briglia - * {daniel.petrini, david.cohen, anderson.briglia}@indt.org.br - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - * - * History - * ------- - * - * 2005/07/25 INdT-10LE Kernel Team - Alsa driver for omap osk, - * original version based in sa1100 driver - * and omap oss driver. - */ - -#ifndef __OMAP_ALSA_H -#define __OMAP_ALSA_H - -#include <mach/dma.h> -#include <sound/core.h> -#include <sound/pcm.h> -#include <mach/mcbsp.h> -#include <linux/platform_device.h> - -#define DMA_BUF_SIZE (1024 * 8) - -/* - * Buffer management for alsa and dma - */ -struct audio_stream { - char *id; /* identification string */ - int stream_id; /* numeric identification */ - int dma_dev; /* dma number of that device */ - int *lch; /* Chain of channels this stream is linked to */ - char started; /* to store if the chain was started or not */ - int dma_q_head; /* DMA Channel Q Head */ - int dma_q_tail; /* DMA Channel Q Tail */ - char dma_q_count; /* DMA Channel Q Count */ - int active:1; /* we are using this stream for transfer now */ - int period; /* current transfer period */ - int periods; /* current count of periods registerd in the DMA engine */ - spinlock_t dma_lock; /* for locking in DMA operations */ - struct snd_pcm_substream *stream; /* the pcm stream */ - unsigned linked:1; /* dma channels linked */ - int offset; /* store start position of the last period in the alsa buffer */ - int (*hw_start)(void); /* interface to start HW interface, e.g. McBSP */ - int (*hw_stop)(void); /* interface to stop HW interface, e.g. McBSP */ -}; - -/* - * Alsa card structure for aic23 - */ -struct snd_card_omap_codec { - struct snd_card *card; - struct snd_pcm *pcm; - long samplerate; - struct audio_stream s[2]; /* playback & capture */ -}; - -/* Codec specific information and function pointers. - * Codec (omap-alsa-aic23.c and omap-alsa-tsc2101.c) - * are responsible for defining the function pointers. - */ -struct omap_alsa_codec_config { - char *name; - struct omap_mcbsp_reg_cfg *mcbsp_regs_alsa; - struct snd_pcm_hw_constraint_list *hw_constraints_rates; - struct snd_pcm_hardware *snd_omap_alsa_playback; - struct snd_pcm_hardware *snd_omap_alsa_capture; - void (*codec_configure_dev)(void); - void (*codec_set_samplerate)(long); - void (*codec_clock_setup)(void); - int (*codec_clock_on)(void); - int (*codec_clock_off)(void); - int (*get_default_samplerate)(void); -}; - -/*********** Mixer function prototypes *************************/ -int snd_omap_mixer(struct snd_card_omap_codec *); -void snd_omap_init_mixer(void); - -#ifdef CONFIG_PM -void snd_omap_suspend_mixer(void); -void snd_omap_resume_mixer(void); -#endif - -int snd_omap_alsa_post_probe(struct platform_device *pdev, struct omap_alsa_codec_config *config); -int snd_omap_alsa_remove(struct platform_device *pdev); -#ifdef CONFIG_PM -int snd_omap_alsa_suspend(struct platform_device *pdev, pm_message_t state); -int snd_omap_alsa_resume(struct platform_device *pdev); -#else -#define snd_omap_alsa_suspend NULL -#define snd_omap_alsa_resume NULL -#endif - -void callback_omap_alsa_sound_dma(void *); - -#endif diff --git a/arch/arm/plat-omap/include/mach/omap-pm.h b/arch/arm/plat-omap/include/mach/omap-pm.h deleted file mode 100644 index 3ee41d71149..00000000000 --- a/arch/arm/plat-omap/include/mach/omap-pm.h +++ /dev/null @@ -1,301 +0,0 @@ -/* - * omap-pm.h - OMAP power management interface - * - * Copyright (C) 2008-2009 Texas Instruments, Inc. - * Copyright (C) 2008-2009 Nokia Corporation - * Paul Walmsley - * - * Interface developed by (in alphabetical order): Karthik Dasu, Jouni - * Högander, Tony Lindgren, Rajendra Nayak, Sakari Poussa, - * Veeramanikandan Raju, Anand Sawant, Igor Stoppa, Paul Walmsley, - * Richard Woodruff - */ - -#ifndef ASM_ARM_ARCH_OMAP_OMAP_PM_H -#define ASM_ARM_ARCH_OMAP_OMAP_PM_H - -#include <linux/device.h> -#include <linux/cpufreq.h> - -#include "powerdomain.h" - -/** - * struct omap_opp - clock frequency-to-OPP ID table for DSP, MPU - * @rate: target clock rate - * @opp_id: OPP ID - * @min_vdd: minimum VDD1 voltage (in millivolts) for this OPP - * - * Operating performance point data. Can vary by OMAP chip and board. - */ -struct omap_opp { - unsigned long rate; - u8 opp_id; - u16 min_vdd; -}; - -extern struct omap_opp *mpu_opps; -extern struct omap_opp *dsp_opps; -extern struct omap_opp *l3_opps; - -/* - * agent_id values for use with omap_pm_set_min_bus_tput(): - * - * OCP_INITIATOR_AGENT is only valid for devices that can act as - * initiators -- it represents the device's L3 interconnect - * connection. OCP_TARGET_AGENT represents the device's L4 - * interconnect connection. - */ -#define OCP_TARGET_AGENT 1 -#define OCP_INITIATOR_AGENT 2 - -/** - * omap_pm_if_early_init - OMAP PM init code called before clock fw init - * @mpu_opp_table: array ptr to struct omap_opp for MPU - * @dsp_opp_table: array ptr to struct omap_opp for DSP - * @l3_opp_table : array ptr to struct omap_opp for CORE - * - * Initialize anything that must be configured before the clock - * framework starts. The "_if_" is to avoid name collisions with the - * PM idle-loop code. - */ -int __init omap_pm_if_early_init(struct omap_opp *mpu_opp_table, - struct omap_opp *dsp_opp_table, - struct omap_opp *l3_opp_table); - -/** - * omap_pm_if_init - OMAP PM init code called after clock fw init - * - * The main initialization code. OPP tables are passed in here. The - * "_if_" is to avoid name collisions with the PM idle-loop code. - */ -int __init omap_pm_if_init(void); - -/** - * omap_pm_if_exit - OMAP PM exit code - * - * Exit code; currently unused. The "_if_" is to avoid name - * collisions with the PM idle-loop code. - */ -void omap_pm_if_exit(void); - -/* - * Device-driver-originated constraints (via board-*.c files, platform_data) - */ - - -/** - * omap_pm_set_max_mpu_wakeup_lat - set the maximum MPU wakeup latency - * @dev: struct device * requesting the constraint - * @t: maximum MPU wakeup latency in microseconds - * - * Request that the maximum interrupt latency for the MPU to be no - * greater than 't' microseconds. "Interrupt latency" in this case is - * defined as the elapsed time from the occurrence of a hardware or - * timer interrupt to the time when the device driver's interrupt - * service routine has been entered by the MPU. - * - * It is intended that underlying PM code will use this information to - * determine what power state to put the MPU powerdomain into, and - * possibly the CORE powerdomain as well, since interrupt handling - * code currently runs from SDRAM. Advanced PM or board*.c code may - * also configure interrupt controller priorities, OCP bus priorities, - * CPU speed(s), etc. - * - * This function will not affect device wakeup latency, e.g., time - * elapsed from when a device driver enables a hardware device with - * clk_enable(), to when the device is ready for register access or - * other use. To control this device wakeup latency, use - * set_max_dev_wakeup_lat() - * - * Multiple calls to set_max_mpu_wakeup_lat() will replace the - * previous t value. To remove the latency target for the MPU, call - * with t = -1. - * - * No return value. - */ -void omap_pm_set_max_mpu_wakeup_lat(struct device *dev, long t); - - -/** - * omap_pm_set_min_bus_tput - set minimum bus throughput needed by device - * @dev: struct device * requesting the constraint - * @tbus_id: interconnect to operate on (OCP_{INITIATOR,TARGET}_AGENT) - * @r: minimum throughput (in KiB/s) - * - * Request that the minimum data throughput on the OCP interconnect - * attached to device 'dev' interconnect agent 'tbus_id' be no less - * than 'r' KiB/s. - * - * It is expected that the OMAP PM or bus code will use this - * information to set the interconnect clock to run at the lowest - * possible speed that satisfies all current system users. The PM or - * bus code will adjust the estimate based on its model of the bus, so - * device driver authors should attempt to specify an accurate - * quantity for their device use case, and let the PM or bus code - * overestimate the numbers as necessary to handle request/response - * latency, other competing users on the system, etc. On OMAP2/3, if - * a driver requests a minimum L4 interconnect speed constraint, the - * code will also need to add an minimum L3 interconnect speed - * constraint, - * - * Multiple calls to set_min_bus_tput() will replace the previous rate - * value for this device. To remove the interconnect throughput - * restriction for this device, call with r = 0. - * - * No return value. - */ -void omap_pm_set_min_bus_tput(struct device *dev, u8 agent_id, unsigned long r); - - -/** - * omap_pm_set_max_dev_wakeup_lat - set the maximum device enable latency - * @dev: struct device * - * @t: maximum device wakeup latency in microseconds - * - * Request that the maximum amount of time necessary for a device to - * become accessible after its clocks are enabled should be no greater - * than 't' microseconds. Specifically, this represents the time from - * when a device driver enables device clocks with clk_enable(), to - * when the register reads and writes on the device will succeed. - * This function should be called before clk_disable() is called, - * since the power state transition decision may be made during - * clk_disable(). - * - * It is intended that underlying PM code will use this information to - * determine what power state to put the powerdomain enclosing this - * device into. - * - * Multiple calls to set_max_dev_wakeup_lat() will replace the - * previous wakeup latency values for this device. To remove the wakeup - * latency restriction for this device, call with t = -1. - * - * No return value. - */ -void omap_pm_set_max_dev_wakeup_lat(struct device *dev, long t); - - -/** - * omap_pm_set_max_sdma_lat - set the maximum system DMA transfer start latency - * @dev: struct device * - * @t: maximum DMA transfer start latency in microseconds - * - * Request that the maximum system DMA transfer start latency for this - * device 'dev' should be no greater than 't' microseconds. "DMA - * transfer start latency" here is defined as the elapsed time from - * when a device (e.g., McBSP) requests that a system DMA transfer - * start or continue, to the time at which data starts to flow into - * that device from the system DMA controller. - * - * It is intended that underlying PM code will use this information to - * determine what power state to put the CORE powerdomain into. - * - * Since system DMA transfers may not involve the MPU, this function - * will not affect MPU wakeup latency. Use set_max_cpu_lat() to do - * so. Similarly, this function will not affect device wakeup latency - * -- use set_max_dev_wakeup_lat() to affect that. - * - * Multiple calls to set_max_sdma_lat() will replace the previous t - * value for this device. To remove the maximum DMA latency for this - * device, call with t = -1. - * - * No return value. - */ -void omap_pm_set_max_sdma_lat(struct device *dev, long t); - - -/* - * DSP Bridge-specific constraints - */ - -/** - * omap_pm_dsp_get_opp_table - get OPP->DSP clock frequency table - * - * Intended for use by DSPBridge. Returns an array of OPP->DSP clock - * frequency entries. The final item in the array should have .rate = - * .opp_id = 0. - */ -const struct omap_opp *omap_pm_dsp_get_opp_table(void); - -/** - * omap_pm_dsp_set_min_opp - receive desired OPP target ID from DSP Bridge - * @opp_id: target DSP OPP ID - * - * Set a minimum OPP ID for the DSP. This is intended to be called - * only from the DSP Bridge MPU-side driver. Unfortunately, the only - * information that code receives from the DSP/BIOS load estimator is the - * target OPP ID; hence, this interface. No return value. - */ -void omap_pm_dsp_set_min_opp(u8 opp_id); - -/** - * omap_pm_dsp_get_opp - report the current DSP OPP ID - * - * Report the current OPP for the DSP. Since on OMAP3, the DSP and - * MPU share a single voltage domain, the OPP ID returned back may - * represent a higher DSP speed than the OPP requested via - * omap_pm_dsp_set_min_opp(). - * - * Returns the current VDD1 OPP ID, or 0 upon error. - */ -u8 omap_pm_dsp_get_opp(void); - - -/* - * CPUFreq-originated constraint - * - * In the future, this should be handled by custom OPP clocktype - * functions. - */ - -/** - * omap_pm_cpu_get_freq_table - return a cpufreq_frequency_table array ptr - * - * Provide a frequency table usable by CPUFreq for the current chip/board. - * Returns a pointer to a struct cpufreq_frequency_table array or NULL - * upon error. - */ -struct cpufreq_frequency_table **omap_pm_cpu_get_freq_table(void); - -/** - * omap_pm_cpu_set_freq - set the current minimum MPU frequency - * @f: MPU frequency in Hz - * - * Set the current minimum CPU frequency. The actual CPU frequency - * used could end up higher if the DSP requested a higher OPP. - * Intended to be called by plat-omap/cpu_omap.c:omap_target(). No - * return value. - */ -void omap_pm_cpu_set_freq(unsigned long f); - -/** - * omap_pm_cpu_get_freq - report the current CPU frequency - * - * Returns the current MPU frequency, or 0 upon error. - */ -unsigned long omap_pm_cpu_get_freq(void); - - -/* - * Device context loss tracking - */ - -/** - * omap_pm_get_dev_context_loss_count - return count of times dev has lost ctx - * @dev: struct device * - * - * This function returns the number of times that the device @dev has - * lost its internal context. This generally occurs on a powerdomain - * transition to OFF. Drivers use this as an optimization to avoid restoring - * context if the device hasn't lost it. To use, drivers should initially - * call this in their context save functions and store the result. Early in - * the driver's context restore function, the driver should call this function - * again, and compare the result to the stored counter. If they differ, the - * driver must restore device context. If the number of context losses - * exceeds the maximum positive integer, the function will wrap to 0 and - * continue counting. Returns the number of context losses for this device, - * or -EINVAL upon error. - */ -int omap_pm_get_dev_context_loss_count(struct device *dev); - - -#endif diff --git a/arch/arm/plat-omap/include/mach/omap1510.h b/arch/arm/plat-omap/include/mach/omap1510.h deleted file mode 100644 index d2400466813..00000000000 --- a/arch/arm/plat-omap/include/mach/omap1510.h +++ /dev/null @@ -1,50 +0,0 @@ -/* arch/arm/plat-omap/include/mach/omap1510.h - * - * Hardware definitions for TI OMAP1510 processor. - * - * Cleanup for Linux-2.6 by Dirk Behme <dirk.behme@de.bosch.com> - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -#ifndef __ASM_ARCH_OMAP15XX_H -#define __ASM_ARCH_OMAP15XX_H - -/* - * ---------------------------------------------------------------------------- - * Base addresses - * ---------------------------------------------------------------------------- - */ - -/* Syntax: XX_BASE = Virtual base address, XX_START = Physical base address */ - -#define OMAP1510_DSP_BASE 0xE0000000 -#define OMAP1510_DSP_SIZE 0x28000 -#define OMAP1510_DSP_START 0xE0000000 - -#define OMAP1510_DSPREG_BASE 0xE1000000 -#define OMAP1510_DSPREG_SIZE SZ_128K -#define OMAP1510_DSPREG_START 0xE1000000 - -#define OMAP1510_DSP_MMU_BASE (0xfffed200) - -#endif /* __ASM_ARCH_OMAP15XX_H */ - diff --git a/arch/arm/plat-omap/include/mach/omap16xx.h b/arch/arm/plat-omap/include/mach/omap16xx.h deleted file mode 100644 index 0e69b504c25..00000000000 --- a/arch/arm/plat-omap/include/mach/omap16xx.h +++ /dev/null @@ -1,202 +0,0 @@ -/* arch/arm/plat-omap/include/mach/omap16xx.h - * - * Hardware definitions for TI OMAP1610/5912/1710 processors. - * - * Cleanup for Linux-2.6 by Dirk Behme <dirk.behme@de.bosch.com> - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -#ifndef __ASM_ARCH_OMAP16XX_H -#define __ASM_ARCH_OMAP16XX_H - -/* - * ---------------------------------------------------------------------------- - * Base addresses - * ---------------------------------------------------------------------------- - */ - -/* Syntax: XX_BASE = Virtual base address, XX_START = Physical base address */ - -#define OMAP16XX_DSP_BASE 0xE0000000 -#define OMAP16XX_DSP_SIZE 0x28000 -#define OMAP16XX_DSP_START 0xE0000000 - -#define OMAP16XX_DSPREG_BASE 0xE1000000 -#define OMAP16XX_DSPREG_SIZE SZ_128K -#define OMAP16XX_DSPREG_START 0xE1000000 - -#define OMAP16XX_SEC_BASE 0xFFFE4000 -#define OMAP16XX_SEC_DES (OMAP16XX_SEC_BASE + 0x0000) -#define OMAP16XX_SEC_SHA1MD5 (OMAP16XX_SEC_BASE + 0x0800) -#define OMAP16XX_SEC_RNG (OMAP16XX_SEC_BASE + 0x1000) - -/* - * --------------------------------------------------------------------------- - * Interrupts - * --------------------------------------------------------------------------- - */ -#define OMAP_IH2_0_BASE (0xfffe0000) -#define OMAP_IH2_1_BASE (0xfffe0100) -#define OMAP_IH2_2_BASE (0xfffe0200) -#define OMAP_IH2_3_BASE (0xfffe0300) - -#define OMAP_IH2_0_ITR (OMAP_IH2_0_BASE + 0x00) -#define OMAP_IH2_0_MIR (OMAP_IH2_0_BASE + 0x04) -#define OMAP_IH2_0_SIR_IRQ (OMAP_IH2_0_BASE + 0x10) -#define OMAP_IH2_0_SIR_FIQ (OMAP_IH2_0_BASE + 0x14) -#define OMAP_IH2_0_CONTROL (OMAP_IH2_0_BASE + 0x18) -#define OMAP_IH2_0_ILR0 (OMAP_IH2_0_BASE + 0x1c) -#define OMAP_IH2_0_ISR (OMAP_IH2_0_BASE + 0x9c) - -#define OMAP_IH2_1_ITR (OMAP_IH2_1_BASE + 0x00) -#define OMAP_IH2_1_MIR (OMAP_IH2_1_BASE + 0x04) -#define OMAP_IH2_1_SIR_IRQ (OMAP_IH2_1_BASE + 0x10) -#define OMAP_IH2_1_SIR_FIQ (OMAP_IH2_1_BASE + 0x14) -#define OMAP_IH2_1_CONTROL (OMAP_IH2_1_BASE + 0x18) -#define OMAP_IH2_1_ILR1 (OMAP_IH2_1_BASE + 0x1c) -#define OMAP_IH2_1_ISR (OMAP_IH2_1_BASE + 0x9c) - -#define OMAP_IH2_2_ITR (OMAP_IH2_2_BASE + 0x00) -#define OMAP_IH2_2_MIR (OMAP_IH2_2_BASE + 0x04) -#define OMAP_IH2_2_SIR_IRQ (OMAP_IH2_2_BASE + 0x10) -#define OMAP_IH2_2_SIR_FIQ (OMAP_IH2_2_BASE + 0x14) -#define OMAP_IH2_2_CONTROL (OMAP_IH2_2_BASE + 0x18) -#define OMAP_IH2_2_ILR2 (OMAP_IH2_2_BASE + 0x1c) -#define OMAP_IH2_2_ISR (OMAP_IH2_2_BASE + 0x9c) - -#define OMAP_IH2_3_ITR (OMAP_IH2_3_BASE + 0x00) -#define OMAP_IH2_3_MIR (OMAP_IH2_3_BASE + 0x04) -#define OMAP_IH2_3_SIR_IRQ (OMAP_IH2_3_BASE + 0x10) -#define OMAP_IH2_3_SIR_FIQ (OMAP_IH2_3_BASE + 0x14) -#define OMAP_IH2_3_CONTROL (OMAP_IH2_3_BASE + 0x18) -#define OMAP_IH2_3_ILR3 (OMAP_IH2_3_BASE + 0x1c) -#define OMAP_IH2_3_ISR (OMAP_IH2_3_BASE + 0x9c) - -/* - * ---------------------------------------------------------------------------- - * Clocks - * ---------------------------------------------------------------------------- - */ -#define OMAP16XX_ARM_IDLECT3 (CLKGEN_REG_BASE + 0x24) - -/* - * ---------------------------------------------------------------------------- - * Pin configuration registers - * ---------------------------------------------------------------------------- - */ -#define OMAP16XX_CONF_VOLTAGE_VDDSHV6 (1 << 8) -#define OMAP16XX_CONF_VOLTAGE_VDDSHV7 (1 << 9) -#define OMAP16XX_CONF_VOLTAGE_VDDSHV8 (1 << 10) -#define OMAP16XX_CONF_VOLTAGE_VDDSHV9 (1 << 11) -#define OMAP16XX_SUBLVDS_CONF_VALID (1 << 13) - -/* - * ---------------------------------------------------------------------------- - * System control registers - * ---------------------------------------------------------------------------- - */ -#define OMAP1610_RESET_CONTROL 0xfffe1140 - -/* - * --------------------------------------------------------------------------- - * TIPB bus interface - * --------------------------------------------------------------------------- - */ -#define TIPB_SWITCH_BASE (0xfffbc800) -#define OMAP16XX_MMCSD2_SSW_MPU_CONF (TIPB_SWITCH_BASE + 0x160) - -/* UART3 Registers Maping through MPU bus */ -#define UART3_RHR (OMAP_UART3_BASE + 0) -#define UART3_THR (OMAP_UART3_BASE + 0) -#define UART3_DLL (OMAP_UART3_BASE + 0) -#define UART3_IER (OMAP_UART3_BASE + 4) -#define UART3_DLH (OMAP_UART3_BASE + 4) -#define UART3_IIR (OMAP_UART3_BASE + 8) -#define UART3_FCR (OMAP_UART3_BASE + 8) -#define UART3_EFR (OMAP_UART3_BASE + 8) -#define UART3_LCR (OMAP_UART3_BASE + 0x0C) -#define UART3_MCR (OMAP_UART3_BASE + 0x10) -#define UART3_XON1_ADDR1 (OMAP_UART3_BASE + 0x10) -#define UART3_XON2_ADDR2 (OMAP_UART3_BASE + 0x14) -#define UART3_LSR (OMAP_UART3_BASE + 0x14) -#define UART3_TCR (OMAP_UART3_BASE + 0x18) -#define UART3_MSR (OMAP_UART3_BASE + 0x18) -#define UART3_XOFF1 (OMAP_UART3_BASE + 0x18) -#define UART3_XOFF2 (OMAP_UART3_BASE + 0x1C) -#define UART3_SPR (OMAP_UART3_BASE + 0x1C) -#define UART3_TLR (OMAP_UART3_BASE + 0x1C) -#define UART3_MDR1 (OMAP_UART3_BASE + 0x20) -#define UART3_MDR2 (OMAP_UART3_BASE + 0x24) -#define UART3_SFLSR (OMAP_UART3_BASE + 0x28) -#define UART3_TXFLL (OMAP_UART3_BASE + 0x28) -#define UART3_RESUME (OMAP_UART3_BASE + 0x2C) -#define UART3_TXFLH (OMAP_UART3_BASE + 0x2C) -#define UART3_SFREGL (OMAP_UART3_BASE + 0x30) -#define UART3_RXFLL (OMAP_UART3_BASE + 0x30) -#define UART3_SFREGH (OMAP_UART3_BASE + 0x34) -#define UART3_RXFLH (OMAP_UART3_BASE + 0x34) -#define UART3_BLR (OMAP_UART3_BASE + 0x38) -#define UART3_ACREG (OMAP_UART3_BASE + 0x3C) -#define UART3_DIV16 (OMAP_UART3_BASE + 0x3C) -#define UART3_SCR (OMAP_UART3_BASE + 0x40) -#define UART3_SSR (OMAP_UART3_BASE + 0x44) -#define UART3_EBLR (OMAP_UART3_BASE + 0x48) -#define UART3_OSC_12M_SEL (OMAP_UART3_BASE + 0x4C) -#define UART3_MVR (OMAP_UART3_BASE + 0x50) - -/* - * --------------------------------------------------------------------------- - * Watchdog timer - * --------------------------------------------------------------------------- - */ - -/* 32-bit Watchdog timer in OMAP 16XX */ -#define OMAP_16XX_WATCHDOG_BASE (0xfffeb000) -#define OMAP_16XX_WIDR (OMAP_16XX_WATCHDOG_BASE + 0x00) -#define OMAP_16XX_WD_SYSCONFIG (OMAP_16XX_WATCHDOG_BASE + 0x10) -#define OMAP_16XX_WD_SYSSTATUS (OMAP_16XX_WATCHDOG_BASE + 0x14) -#define OMAP_16XX_WCLR (OMAP_16XX_WATCHDOG_BASE + 0x24) -#define OMAP_16XX_WCRR (OMAP_16XX_WATCHDOG_BASE + 0x28) -#define OMAP_16XX_WLDR (OMAP_16XX_WATCHDOG_BASE + 0x2c) -#define OMAP_16XX_WTGR (OMAP_16XX_WATCHDOG_BASE + 0x30) -#define OMAP_16XX_WWPS (OMAP_16XX_WATCHDOG_BASE + 0x34) -#define OMAP_16XX_WSPR (OMAP_16XX_WATCHDOG_BASE + 0x48) - -#define WCLR_PRE_SHIFT 5 -#define WCLR_PTV_SHIFT 2 - -#define WWPS_W_PEND_WSPR (1 << 4) -#define WWPS_W_PEND_WTGR (1 << 3) -#define WWPS_W_PEND_WLDR (1 << 2) -#define WWPS_W_PEND_WCRR (1 << 1) -#define WWPS_W_PEND_WCLR (1 << 0) - -#define WSPR_ENABLE_0 (0x0000bbbb) -#define WSPR_ENABLE_1 (0x00004444) -#define WSPR_DISABLE_0 (0x0000aaaa) -#define WSPR_DISABLE_1 (0x00005555) - -#define OMAP16XX_DSP_MMU_BASE (0xfffed200) -#define OMAP16XX_MAILBOX_BASE (0xfffcf000) - -#endif /* __ASM_ARCH_OMAP16XX_H */ - diff --git a/arch/arm/plat-omap/include/mach/omap24xx.h b/arch/arm/plat-omap/include/mach/omap24xx.h deleted file mode 100644 index 696edfc145a..00000000000 --- a/arch/arm/plat-omap/include/mach/omap24xx.h +++ /dev/null @@ -1,89 +0,0 @@ -/* - * arch/arm/plat-omap/include/mach/omap24xx.h - * - * This file contains the processor specific definitions - * of the TI OMAP24XX. - * - * Copyright (C) 2007 Texas Instruments. - * Copyright (C) 2007 Nokia Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - * - */ - -#ifndef __ASM_ARCH_OMAP24XX_H -#define __ASM_ARCH_OMAP24XX_H - -/* - * Please place only base defines here and put the rest in device - * specific headers. Note also that some of these defines are needed - * for omap1 to compile without adding ifdefs. - */ - -#define L4_24XX_BASE 0x48000000 -#define L4_WK_243X_BASE 0x49000000 -#define L3_24XX_BASE 0x68000000 - -/* interrupt controller */ -#define OMAP24XX_IC_BASE (L4_24XX_BASE + 0xfe000) -#define OMAP24XX_IVA_INTC_BASE 0x40000000 - -#define OMAP2420_CTRL_BASE L4_24XX_BASE -#define OMAP2420_32KSYNCT_BASE (L4_24XX_BASE + 0x4000) -#define OMAP2420_PRCM_BASE (L4_24XX_BASE + 0x8000) -#define OMAP2420_CM_BASE (L4_24XX_BASE + 0x8000) -#define OMAP2420_PRM_BASE OMAP2420_CM_BASE -#define OMAP2420_SDRC_BASE (L3_24XX_BASE + 0x9000) -#define OMAP2420_SMS_BASE 0x68008000 -#define OMAP2420_GPMC_BASE 0x6800a000 - -#define OMAP2430_32KSYNCT_BASE (L4_WK_243X_BASE + 0x20000) -#define OMAP2430_PRCM_BASE (L4_WK_243X_BASE + 0x6000) -#define OMAP2430_CM_BASE (L4_WK_243X_BASE + 0x6000) -#define OMAP2430_PRM_BASE OMAP2430_CM_BASE - -#define OMAP243X_SMS_BASE 0x6C000000 -#define OMAP243X_SDRC_BASE 0x6D000000 -#define OMAP243X_GPMC_BASE 0x6E000000 -#define OMAP243X_SCM_BASE (L4_WK_243X_BASE + 0x2000) -#define OMAP243X_CTRL_BASE OMAP243X_SCM_BASE -#define OMAP243X_HS_BASE (L4_24XX_BASE + 0x000ac000) - -/* DSP SS */ -#define OMAP2420_DSP_BASE 0x58000000 -#define OMAP2420_DSP_MEM_BASE (OMAP2420_DSP_BASE + 0x0) -#define OMAP2420_DSP_IPI_BASE (OMAP2420_DSP_BASE + 0x1000000) -#define OMAP2420_DSP_MMU_BASE (OMAP2420_DSP_BASE + 0x2000000) - -#define OMAP243X_DSP_BASE 0x5C000000 -#define OMAP243X_DSP_MEM_BASE (OMAP243X_DSP_BASE + 0x0) -#define OMAP243X_DSP_MMU_BASE (OMAP243X_DSP_BASE + 0x1000000) - -/* Mailbox */ -#define OMAP24XX_MAILBOX_BASE (L4_24XX_BASE + 0x94000) - -/* Camera */ -#define OMAP24XX_CAMERA_BASE (L4_24XX_BASE + 0x52000) - -/* Security */ -#define OMAP24XX_SEC_BASE (L4_24XX_BASE + 0xA0000) -#define OMAP24XX_SEC_RNG_BASE (OMAP24XX_SEC_BASE + 0x0000) -#define OMAP24XX_SEC_DES_BASE (OMAP24XX_SEC_BASE + 0x2000) -#define OMAP24XX_SEC_SHA1MD5_BASE (OMAP24XX_SEC_BASE + 0x4000) -#define OMAP24XX_SEC_AES_BASE (OMAP24XX_SEC_BASE + 0x6000) -#define OMAP24XX_SEC_PKA_BASE (OMAP24XX_SEC_BASE + 0x8000) - -#endif /* __ASM_ARCH_OMAP24XX_H */ - diff --git a/arch/arm/plat-omap/include/mach/omap34xx.h b/arch/arm/plat-omap/include/mach/omap34xx.h deleted file mode 100644 index f8d186a7371..00000000000 --- a/arch/arm/plat-omap/include/mach/omap34xx.h +++ /dev/null @@ -1,87 +0,0 @@ -/* - * arch/arm/plat-omap/include/mach/omap34xx.h - * - * This file contains the processor specific definitions of the TI OMAP34XX. - * - * Copyright (C) 2007 Texas Instruments. - * Copyright (C) 2007 Nokia Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ - -#ifndef __ASM_ARCH_OMAP34XX_H -#define __ASM_ARCH_OMAP34XX_H - -/* - * Please place only base defines here and put the rest in device - * specific headers. - */ - -#define L4_34XX_BASE 0x48000000 -#define L4_WK_34XX_BASE 0x48300000 -#define L4_PER_34XX_BASE 0x49000000 -#define L4_EMU_34XX_BASE 0x54000000 -#define L3_34XX_BASE 0x68000000 - -#define OMAP3430_32KSYNCT_BASE 0x48320000 -#define OMAP3430_CM_BASE 0x48004800 -#define OMAP3430_PRM_BASE 0x48306800 -#define OMAP343X_SMS_BASE 0x6C000000 -#define OMAP343X_SDRC_BASE 0x6D000000 -#define OMAP34XX_GPMC_BASE 0x6E000000 -#define OMAP343X_SCM_BASE 0x48002000 -#define OMAP343X_CTRL_BASE OMAP343X_SCM_BASE - -#define OMAP34XX_IC_BASE 0x48200000 - -#define OMAP3430_ISP_BASE (L4_34XX_BASE + 0xBC000) -#define OMAP3430_ISP_CBUFF_BASE (OMAP3430_ISP_BASE + 0x0100) -#define OMAP3430_ISP_CCP2_BASE (OMAP3430_ISP_BASE + 0x0400) -#define OMAP3430_ISP_CCDC_BASE (OMAP3430_ISP_BASE + 0x0600) -#define OMAP3430_ISP_HIST_BASE (OMAP3430_ISP_BASE + 0x0A00) -#define OMAP3430_ISP_H3A_BASE (OMAP3430_ISP_BASE + 0x0C00) -#define OMAP3430_ISP_PREV_BASE (OMAP3430_ISP_BASE + 0x0E00) -#define OMAP3430_ISP_RESZ_BASE (OMAP3430_ISP_BASE + 0x1000) -#define OMAP3430_ISP_SBL_BASE (OMAP3430_ISP_BASE + 0x1200) -#define OMAP3430_ISP_MMU_BASE (OMAP3430_ISP_BASE + 0x1400) -#define OMAP3430_ISP_CSI2A_BASE (OMAP3430_ISP_BASE + 0x1800) -#define OMAP3430_ISP_CSI2PHY_BASE (OMAP3430_ISP_BASE + 0x1970) - -#define OMAP3430_ISP_END (OMAP3430_ISP_BASE + 0x06F) -#define OMAP3430_ISP_CBUFF_END (OMAP3430_ISP_CBUFF_BASE + 0x077) -#define OMAP3430_ISP_CCP2_END (OMAP3430_ISP_CCP2_BASE + 0x1EF) -#define OMAP3430_ISP_CCDC_END (OMAP3430_ISP_CCDC_BASE + 0x0A7) -#define OMAP3430_ISP_HIST_END (OMAP3430_ISP_HIST_BASE + 0x047) -#define OMAP3430_ISP_H3A_END (OMAP3430_ISP_H3A_BASE + 0x05F) -#define OMAP3430_ISP_PREV_END (OMAP3430_ISP_PREV_BASE + 0x09F) -#define OMAP3430_ISP_RESZ_END (OMAP3430_ISP_RESZ_BASE + 0x0AB) -#define OMAP3430_ISP_SBL_END (OMAP3430_ISP_SBL_BASE + 0x0FB) -#define OMAP3430_ISP_MMU_END (OMAP3430_ISP_MMU_BASE + 0x06F) -#define OMAP3430_ISP_CSI2A_END (OMAP3430_ISP_CSI2A_BASE + 0x16F) -#define OMAP3430_ISP_CSI2PHY_END (OMAP3430_ISP_CSI2PHY_BASE + 0x007) - -#define OMAP34XX_IVA_INTC_BASE 0x40000000 -#define OMAP34XX_HSUSB_OTG_BASE (L4_34XX_BASE + 0xAB000) -#define OMAP34XX_HSUSB_HOST_BASE (L4_34XX_BASE + 0x64000) -#define OMAP34XX_USBTLL_BASE (L4_34XX_BASE + 0x62000) - -#define OMAP34XX_MAILBOX_BASE (L4_34XX_BASE + 0x94000) - -#define OMAP34XX_DSP_BASE 0x58000000 -#define OMAP34XX_DSP_MEM_BASE (OMAP34XX_DSP_BASE + 0x0) -#define OMAP34XX_DSP_IPI_BASE (OMAP34XX_DSP_BASE + 0x1000000) -#define OMAP34XX_DSP_MMU_BASE (OMAP34XX_DSP_BASE + 0x2000000) -#endif /* __ASM_ARCH_OMAP34XX_H */ - diff --git a/arch/arm/plat-omap/include/mach/omap44xx.h b/arch/arm/plat-omap/include/mach/omap44xx.h deleted file mode 100644 index b3ba5ac7b4a..00000000000 --- a/arch/arm/plat-omap/include/mach/omap44xx.h +++ /dev/null @@ -1,46 +0,0 @@ -/*: - * Address mappings and base address for OMAP4 interconnects - * and peripherals. - * - * Copyright (C) 2009 Texas Instruments - * - * Author: Santosh Shilimkar <santosh.shilimkar@ti.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#ifndef __ASM_ARCH_OMAP44XX_H -#define __ASM_ARCH_OMAP44XX_H - -/* - * Please place only base defines here and put the rest in device - * specific headers. - */ -#define L4_44XX_BASE 0x4a000000 -#define L4_WK_44XX_BASE 0x4a300000 -#define L4_PER_44XX_BASE 0x48000000 -#define L4_EMU_44XX_BASE 0x54000000 -#define L3_44XX_BASE 0x44000000 -#define OMAP4430_32KSYNCT_BASE 0x4a304000 -#define OMAP4430_CM_BASE 0x4a004000 -#define OMAP4430_PRM_BASE 0x48306000 -#define OMAP44XX_GPMC_BASE 0x50000000 -#define OMAP443X_SCM_BASE 0x4a002000 -#define OMAP443X_CTRL_BASE OMAP443X_SCM_BASE -#define OMAP44XX_IC_BASE 0x48200000 -#define OMAP44XX_IVA_INTC_BASE 0x40000000 -#define IRQ_SIR_IRQ 0x0040 -#define OMAP44XX_GIC_DIST_BASE 0x48241000 -#define OMAP44XX_GIC_CPU_BASE 0x48240100 -#define OMAP44XX_VA_GIC_CPU_BASE OMAP2_IO_ADDRESS(OMAP44XX_GIC_CPU_BASE) -#define OMAP44XX_SCU_BASE 0x48240000 -#define OMAP44XX_VA_SCU_BASE OMAP2_IO_ADDRESS(OMAP44XX_SCU_BASE) -#define OMAP44XX_LOCAL_TWD_BASE 0x48240600 -#define OMAP44XX_VA_LOCAL_TWD_BASE OMAP2_IO_ADDRESS(OMAP44XX_LOCAL_TWD_BASE) -#define OMAP44XX_LOCAL_TWD_SIZE 0x00000100 -#define OMAP44XX_WKUPGEN_BASE 0x48281000 -#define OMAP44XX_VA_WKUPGEN_BASE OMAP2_IO_ADDRESS(OMAP44XX_WKUPGEN_BASE) - -#endif /* __ASM_ARCH_OMAP44XX_H */ - diff --git a/arch/arm/plat-omap/include/mach/omap730.h b/arch/arm/plat-omap/include/mach/omap730.h deleted file mode 100644 index 14272bc1a6f..00000000000 --- a/arch/arm/plat-omap/include/mach/omap730.h +++ /dev/null @@ -1,102 +0,0 @@ -/* arch/arm/plat-omap/include/mach/omap730.h - * - * Hardware definitions for TI OMAP730 processor. - * - * Cleanup for Linux-2.6 by Dirk Behme <dirk.behme@de.bosch.com> - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -#ifndef __ASM_ARCH_OMAP730_H -#define __ASM_ARCH_OMAP730_H - -/* - * ---------------------------------------------------------------------------- - * Base addresses - * ---------------------------------------------------------------------------- - */ - -/* Syntax: XX_BASE = Virtual base address, XX_START = Physical base address */ - -#define OMAP730_DSP_BASE 0xE0000000 -#define OMAP730_DSP_SIZE 0x50000 -#define OMAP730_DSP_START 0xE0000000 - -#define OMAP730_DSPREG_BASE 0xE1000000 -#define OMAP730_DSPREG_SIZE SZ_128K -#define OMAP730_DSPREG_START 0xE1000000 - -/* - * ---------------------------------------------------------------------------- - * OMAP730 specific configuration registers - * ---------------------------------------------------------------------------- - */ -#define OMAP730_CONFIG_BASE 0xfffe1000 -#define OMAP730_IO_CONF_0 0xfffe1070 -#define OMAP730_IO_CONF_1 0xfffe1074 -#define OMAP730_IO_CONF_2 0xfffe1078 -#define OMAP730_IO_CONF_3 0xfffe107c -#define OMAP730_IO_CONF_4 0xfffe1080 -#define OMAP730_IO_CONF_5 0xfffe1084 -#define OMAP730_IO_CONF_6 0xfffe1088 -#define OMAP730_IO_CONF_7 0xfffe108c -#define OMAP730_IO_CONF_8 0xfffe1090 -#define OMAP730_IO_CONF_9 0xfffe1094 -#define OMAP730_IO_CONF_10 0xfffe1098 -#define OMAP730_IO_CONF_11 0xfffe109c -#define OMAP730_IO_CONF_12 0xfffe10a0 -#define OMAP730_IO_CONF_13 0xfffe10a4 - -#define OMAP730_MODE_1 0xfffe1010 -#define OMAP730_MODE_2 0xfffe1014 - -/* CSMI specials: in terms of base + offset */ -#define OMAP730_MODE2_OFFSET 0x14 - -/* - * ---------------------------------------------------------------------------- - * OMAP730 traffic controller configuration registers - * ---------------------------------------------------------------------------- - */ -#define OMAP730_FLASH_CFG_0 0xfffecc10 -#define OMAP730_FLASH_ACFG_0 0xfffecc50 -#define OMAP730_FLASH_CFG_1 0xfffecc14 -#define OMAP730_FLASH_ACFG_1 0xfffecc54 - -/* - * ---------------------------------------------------------------------------- - * OMAP730 DSP control registers - * ---------------------------------------------------------------------------- - */ -#define OMAP730_ICR_BASE 0xfffbb800 -#define OMAP730_DSP_M_CTL 0xfffbb804 -#define OMAP730_DSP_MMU_BASE 0xfffed200 - -/* - * ---------------------------------------------------------------------------- - * OMAP730 PCC_UPLD configuration registers - * ---------------------------------------------------------------------------- - */ -#define OMAP730_PCC_UPLD_CTRL_BASE (0xfffe0900) -#define OMAP730_PCC_UPLD_CTRL (OMAP730_PCC_UPLD_CTRL_BASE + 0x00) - -#endif /* __ASM_ARCH_OMAP730_H */ - diff --git a/arch/arm/plat-omap/include/mach/omap850.h b/arch/arm/plat-omap/include/mach/omap850.h deleted file mode 100644 index c33f6798171..00000000000 --- a/arch/arm/plat-omap/include/mach/omap850.h +++ /dev/null @@ -1,102 +0,0 @@ -/* arch/arm/plat-omap/include/mach/omap850.h - * - * Hardware definitions for TI OMAP850 processor. - * - * Derived from omap730.h by Zebediah C. McClure <zmc@lurian.net> - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -#ifndef __ASM_ARCH_OMAP850_H -#define __ASM_ARCH_OMAP850_H - -/* - * ---------------------------------------------------------------------------- - * Base addresses - * ---------------------------------------------------------------------------- - */ - -/* Syntax: XX_BASE = Virtual base address, XX_START = Physical base address */ - -#define OMAP850_DSP_BASE 0xE0000000 -#define OMAP850_DSP_SIZE 0x50000 -#define OMAP850_DSP_START 0xE0000000 - -#define OMAP850_DSPREG_BASE 0xE1000000 -#define OMAP850_DSPREG_SIZE SZ_128K -#define OMAP850_DSPREG_START 0xE1000000 - -/* - * ---------------------------------------------------------------------------- - * OMAP850 specific configuration registers - * ---------------------------------------------------------------------------- - */ -#define OMAP850_CONFIG_BASE 0xfffe1000 -#define OMAP850_IO_CONF_0 0xfffe1070 -#define OMAP850_IO_CONF_1 0xfffe1074 -#define OMAP850_IO_CONF_2 0xfffe1078 -#define OMAP850_IO_CONF_3 0xfffe107c -#define OMAP850_IO_CONF_4 0xfffe1080 -#define OMAP850_IO_CONF_5 0xfffe1084 -#define OMAP850_IO_CONF_6 0xfffe1088 -#define OMAP850_IO_CONF_7 0xfffe108c -#define OMAP850_IO_CONF_8 0xfffe1090 -#define OMAP850_IO_CONF_9 0xfffe1094 -#define OMAP850_IO_CONF_10 0xfffe1098 -#define OMAP850_IO_CONF_11 0xfffe109c -#define OMAP850_IO_CONF_12 0xfffe10a0 -#define OMAP850_IO_CONF_13 0xfffe10a4 - -#define OMAP850_MODE_1 0xfffe1010 -#define OMAP850_MODE_2 0xfffe1014 - -/* CSMI specials: in terms of base + offset */ -#define OMAP850_MODE2_OFFSET 0x14 - -/* - * ---------------------------------------------------------------------------- - * OMAP850 traffic controller configuration registers - * ---------------------------------------------------------------------------- - */ -#define OMAP850_FLASH_CFG_0 0xfffecc10 -#define OMAP850_FLASH_ACFG_0 0xfffecc50 -#define OMAP850_FLASH_CFG_1 0xfffecc14 -#define OMAP850_FLASH_ACFG_1 0xfffecc54 - -/* - * ---------------------------------------------------------------------------- - * OMAP850 DSP control registers - * ---------------------------------------------------------------------------- - */ -#define OMAP850_ICR_BASE 0xfffbb800 -#define OMAP850_DSP_M_CTL 0xfffbb804 -#define OMAP850_DSP_MMU_BASE 0xfffed200 - -/* - * ---------------------------------------------------------------------------- - * OMAP850 PCC_UPLD configuration registers - * ---------------------------------------------------------------------------- - */ -#define OMAP850_PCC_UPLD_CTRL_BASE (0xfffe0900) -#define OMAP850_PCC_UPLD_CTRL (OMAP850_PCC_UPLD_CTRL_BASE + 0x00) - -#endif /* __ASM_ARCH_OMAP850_H */ - diff --git a/arch/arm/plat-omap/include/mach/omap_device.h b/arch/arm/plat-omap/include/mach/omap_device.h deleted file mode 100644 index bd0e136db33..00000000000 --- a/arch/arm/plat-omap/include/mach/omap_device.h +++ /dev/null @@ -1,141 +0,0 @@ -/* - * omap_device headers - * - * Copyright (C) 2009 Nokia Corporation - * Paul Walmsley - * - * Developed in collaboration with (alphabetical order): Benoit - * Cousson, Kevin Hilman, Tony Lindgren, Rajendra Nayak, Vikram - * Pandita, Sakari Poussa, Anand Sawant, Santosh Shilimkar, Richard - * Woodruff - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * Eventually this type of functionality should either be - * a) implemented via arch-specific pointers in platform_device - * or - * b) implemented as a proper omap_bus/omap_device in Linux, no more - * platform_device - * - * omap_device differs from omap_hwmod in that it includes external - * (e.g., board- and system-level) integration details. omap_hwmod - * stores hardware data that is invariant for a given OMAP chip. - * - * To do: - * - GPIO integration - * - regulator integration - * - */ -#ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_DEVICE_H -#define __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_DEVICE_H - -#include <linux/kernel.h> -#include <linux/platform_device.h> - -#include <mach/omap_hwmod.h> - -/* omap_device._state values */ -#define OMAP_DEVICE_STATE_UNKNOWN 0 -#define OMAP_DEVICE_STATE_ENABLED 1 -#define OMAP_DEVICE_STATE_IDLE 2 -#define OMAP_DEVICE_STATE_SHUTDOWN 3 - -/** - * struct omap_device - omap_device wrapper for platform_devices - * @pdev: platform_device - * @hwmods: (one .. many per omap_device) - * @hwmods_cnt: ARRAY_SIZE() of @hwmods - * @pm_lats: ptr to an omap_device_pm_latency table - * @pm_lats_cnt: ARRAY_SIZE() of what is passed to @pm_lats - * @pm_lat_level: array index of the last odpl entry executed - -1 if never - * @dev_wakeup_lat: dev wakeup latency in microseconds - * @_dev_wakeup_lat_limit: dev wakeup latency limit in usec - set by OMAP PM - * @_state: one of OMAP_DEVICE_STATE_* (see above) - * @flags: device flags - * - * Integrates omap_hwmod data into Linux platform_device. - * - * Field names beginning with underscores are for the internal use of - * the omap_device code. - * - */ -struct omap_device { - struct platform_device pdev; - struct omap_hwmod **hwmods; - struct omap_device_pm_latency *pm_lats; - u32 dev_wakeup_lat; - u32 _dev_wakeup_lat_limit; - u8 pm_lats_cnt; - s8 pm_lat_level; - u8 hwmods_cnt; - u8 _state; -}; - -/* Device driver interface (call via platform_data fn ptrs) */ - -int omap_device_enable(struct platform_device *pdev); -int omap_device_idle(struct platform_device *pdev); -int omap_device_shutdown(struct platform_device *pdev); - -/* Core code interface */ - -int omap_device_count_resources(struct omap_device *od); -int omap_device_fill_resources(struct omap_device *od, struct resource *res); - -struct omap_device *omap_device_build(const char *pdev_name, int pdev_id, - struct omap_hwmod *oh, void *pdata, - int pdata_len, - struct omap_device_pm_latency *pm_lats, - int pm_lats_cnt); - -struct omap_device *omap_device_build_ss(const char *pdev_name, int pdev_id, - struct omap_hwmod **oh, int oh_cnt, - void *pdata, int pdata_len, - struct omap_device_pm_latency *pm_lats, - int pm_lats_cnt); - -int omap_device_register(struct omap_device *od); - -/* OMAP PM interface */ -int omap_device_align_pm_lat(struct platform_device *pdev, - u32 new_wakeup_lat_limit); -struct powerdomain *omap_device_get_pwrdm(struct omap_device *od); - -/* Other */ - -int omap_device_idle_hwmods(struct omap_device *od); -int omap_device_enable_hwmods(struct omap_device *od); - -int omap_device_disable_clocks(struct omap_device *od); -int omap_device_enable_clocks(struct omap_device *od); - - -/* - * Entries should be kept in latency order ascending - * - * deact_lat is the maximum number of microseconds required to complete - * deactivate_func() at the device's slowest OPP. - * - * act_lat is the maximum number of microseconds required to complete - * activate_func() at the device's slowest OPP. - * - * This will result in some suboptimal power management decisions at fast - * OPPs, but avoids having to recompute all device power management decisions - * if the system shifts from a fast OPP to a slow OPP (in order to meet - * latency requirements). - * - * XXX should deactivate_func/activate_func() take platform_device pointers - * rather than omap_device pointers? - */ -struct omap_device_pm_latency { - u32 deactivate_lat; - int (*deactivate_func)(struct omap_device *od); - u32 activate_lat; - int (*activate_func)(struct omap_device *od); -}; - - -#endif - diff --git a/arch/arm/plat-omap/include/mach/omap_hwmod.h b/arch/arm/plat-omap/include/mach/omap_hwmod.h deleted file mode 100644 index 1f79c20e292..00000000000 --- a/arch/arm/plat-omap/include/mach/omap_hwmod.h +++ /dev/null @@ -1,447 +0,0 @@ -/* - * omap_hwmod macros, structures - * - * Copyright (C) 2009 Nokia Corporation - * Paul Walmsley - * - * Created in collaboration with (alphabetical order): Benoit Cousson, - * Kevin Hilman, Tony Lindgren, Rajendra Nayak, Vikram Pandita, Sakari - * Poussa, Anand Sawant, Santosh Shilimkar, Richard Woodruff - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * These headers and macros are used to define OMAP on-chip module - * data and their integration with other OMAP modules and Linux. - * - * References: - * - OMAP2420 Multimedia Processor Silicon Revision 2.1.1, 2.2 (SWPU064) - * - OMAP2430 Multimedia Device POP Silicon Revision 2.1 (SWPU090) - * - OMAP34xx Multimedia Device Silicon Revision 3.1 (SWPU108) - * - OMAP4430 Multimedia Device Silicon Revision 1.0 (SWPU140) - * - Open Core Protocol Specification 2.2 - * - * To do: - * - add interconnect error log structures - * - add pinmuxing - * - init_conn_id_bit (CONNID_BIT_VECTOR) - * - implement default hwmod SMS/SDRC flags? - * - */ -#ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_HWMOD_H -#define __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_HWMOD_H - -#include <linux/kernel.h> -#include <linux/ioport.h> - -#include <mach/cpu.h> - -struct omap_device; - -/* OCP SYSCONFIG bit shifts/masks */ -#define SYSC_MIDLEMODE_SHIFT 12 -#define SYSC_MIDLEMODE_MASK (0x3 << SYSC_MIDLEMODE_SHIFT) -#define SYSC_CLOCKACTIVITY_SHIFT 8 -#define SYSC_CLOCKACTIVITY_MASK (0x3 << SYSC_CLOCKACTIVITY_SHIFT) -#define SYSC_SIDLEMODE_SHIFT 3 -#define SYSC_SIDLEMODE_MASK (0x3 << SYSC_SIDLEMODE_SHIFT) -#define SYSC_ENAWAKEUP_SHIFT 2 -#define SYSC_ENAWAKEUP_MASK (1 << SYSC_ENAWAKEUP_SHIFT) -#define SYSC_SOFTRESET_SHIFT 1 -#define SYSC_SOFTRESET_MASK (1 << SYSC_SOFTRESET_SHIFT) - -/* OCP SYSSTATUS bit shifts/masks */ -#define SYSS_RESETDONE_SHIFT 0 -#define SYSS_RESETDONE_MASK (1 << SYSS_RESETDONE_SHIFT) - -/* Master standby/slave idle mode flags */ -#define HWMOD_IDLEMODE_FORCE (1 << 0) -#define HWMOD_IDLEMODE_NO (1 << 1) -#define HWMOD_IDLEMODE_SMART (1 << 2) - - -/** - * struct omap_hwmod_dma_info - MPU address space handled by the hwmod - * @name: name of the DMA channel (module local name) - * @dma_ch: DMA channel ID - * - * @name should be something short, e.g., "tx" or "rx". It is for use - * by platform_get_resource_byname(). It is defined locally to the - * hwmod. - */ -struct omap_hwmod_dma_info { - const char *name; - u16 dma_ch; -}; - -/** - * struct omap_hwmod_opt_clk - optional clocks used by this hwmod - * @role: "sys", "32k", "tv", etc -- for use in clk_get() - * @clkdev_dev_id: opt clock: clkdev dev_id string - * @clkdev_con_id: opt clock: clkdev con_id string - * @_clk: pointer to the struct clk (filled in at runtime) - * - * The module's interface clock and main functional clock should not - * be added as optional clocks. - */ -struct omap_hwmod_opt_clk { - const char *role; - const char *clkdev_dev_id; - const char *clkdev_con_id; - struct clk *_clk; -}; - - -/* omap_hwmod_omap2_firewall.flags bits */ -#define OMAP_FIREWALL_L3 (1 << 0) -#define OMAP_FIREWALL_L4 (1 << 1) - -/** - * struct omap_hwmod_omap2_firewall - OMAP2/3 device firewall data - * @l3_perm_bit: bit shift for L3_PM_*_PERMISSION_* - * @l4_fw_region: L4 firewall region ID - * @l4_prot_group: L4 protection group ID - * @flags: (see omap_hwmod_omap2_firewall.flags macros above) - */ -struct omap_hwmod_omap2_firewall { - u8 l3_perm_bit; - u8 l4_fw_region; - u8 l4_prot_group; - u8 flags; -}; - - -/* - * omap_hwmod_addr_space.flags bits - * - * ADDR_MAP_ON_INIT: Map this address space during omap_hwmod init. - * ADDR_TYPE_RT: Address space contains module register target data. - */ -#define ADDR_MAP_ON_INIT (1 << 0) -#define ADDR_TYPE_RT (1 << 1) - -/** - * struct omap_hwmod_addr_space - MPU address space handled by the hwmod - * @pa_start: starting physical address - * @pa_end: ending physical address - * @flags: (see omap_hwmod_addr_space.flags macros above) - * - * Address space doesn't necessarily follow physical interconnect - * structure. GPMC is one example. - */ -struct omap_hwmod_addr_space { - u32 pa_start; - u32 pa_end; - u8 flags; -}; - - -/* - * omap_hwmod_ocp_if.user bits: these indicate the initiators that use this - * interface to interact with the hwmod. Used to add sleep dependencies - * when the module is enabled or disabled. - */ -#define OCP_USER_MPU (1 << 0) -#define OCP_USER_SDMA (1 << 1) - -/* omap_hwmod_ocp_if.flags bits */ -#define OCPIF_HAS_IDLEST (1 << 0) -#define OCPIF_SWSUP_IDLE (1 << 1) -#define OCPIF_CAN_BURST (1 << 2) - -/** - * struct omap_hwmod_ocp_if - OCP interface data - * @master: struct omap_hwmod that initiates OCP transactions on this link - * @slave: struct omap_hwmod that responds to OCP transactions on this link - * @addr: address space associated with this link - * @clkdev_dev_id: interface clock: clkdev dev_id string - * @clkdev_con_id: interface clock: clkdev con_id string - * @_clk: pointer to the interface struct clk (filled in at runtime) - * @fw: interface firewall data - * @addr_cnt: ARRAY_SIZE(@addr) - * @width: OCP data width - * @thread_cnt: number of threads - * @max_burst_len: maximum burst length in @width sized words (0 if unlimited) - * @user: initiators using this interface (see OCP_USER_* macros above) - * @flags: OCP interface flags (see OCPIF_* macros above) - * - * It may also be useful to add a tag_cnt field for OCP2.x devices. - * - * Parameter names beginning with an underscore are managed internally by - * the omap_hwmod code and should not be set during initialization. - */ -struct omap_hwmod_ocp_if { - struct omap_hwmod *master; - struct omap_hwmod *slave; - struct omap_hwmod_addr_space *addr; - const char *clkdev_dev_id; - const char *clkdev_con_id; - struct clk *_clk; - union { - struct omap_hwmod_omap2_firewall omap2; - } fw; - u8 addr_cnt; - u8 width; - u8 thread_cnt; - u8 max_burst_len; - u8 user; - u8 flags; -}; - - -/* Macros for use in struct omap_hwmod_sysconfig */ - -/* Flags for use in omap_hwmod_sysconfig.idlemodes */ -#define MASTER_STANDBY_SHIFT 2 -#define SLAVE_IDLE_SHIFT 0 -#define SIDLE_FORCE (HWMOD_IDLEMODE_FORCE << SLAVE_IDLE_SHIFT) -#define SIDLE_NO (HWMOD_IDLEMODE_NO << SLAVE_IDLE_SHIFT) -#define SIDLE_SMART (HWMOD_IDLEMODE_SMART << SLAVE_IDLE_SHIFT) -#define MSTANDBY_FORCE (HWMOD_IDLEMODE_FORCE << MASTER_STANDBY_SHIFT) -#define MSTANDBY_NO (HWMOD_IDLEMODE_NO << MASTER_STANDBY_SHIFT) -#define MSTANDBY_SMART (HWMOD_IDLEMODE_SMART << MASTER_STANDBY_SHIFT) - -/* omap_hwmod_sysconfig.sysc_flags capability flags */ -#define SYSC_HAS_AUTOIDLE (1 << 0) -#define SYSC_HAS_SOFTRESET (1 << 1) -#define SYSC_HAS_ENAWAKEUP (1 << 2) -#define SYSC_HAS_EMUFREE (1 << 3) -#define SYSC_HAS_CLOCKACTIVITY (1 << 4) -#define SYSC_HAS_SIDLEMODE (1 << 5) -#define SYSC_HAS_MIDLEMODE (1 << 6) -#define SYSS_MISSING (1 << 7) - -/* omap_hwmod_sysconfig.clockact flags */ -#define CLOCKACT_TEST_BOTH 0x0 -#define CLOCKACT_TEST_MAIN 0x1 -#define CLOCKACT_TEST_ICLK 0x2 -#define CLOCKACT_TEST_NONE 0x3 - -/** - * struct omap_hwmod_sysconfig - hwmod OCP_SYSCONFIG/OCP_SYSSTATUS data - * @rev_offs: IP block revision register offset (from module base addr) - * @sysc_offs: OCP_SYSCONFIG register offset (from module base addr) - * @syss_offs: OCP_SYSSTATUS register offset (from module base addr) - * @idlemodes: One or more of {SIDLE,MSTANDBY}_{OFF,FORCE,SMART} - * @sysc_flags: SYS{C,S}_HAS* flags indicating SYSCONFIG bits supported - * @clockact: the default value of the module CLOCKACTIVITY bits - * - * @clockact describes to the module which clocks are likely to be - * disabled when the PRCM issues its idle request to the module. Some - * modules have separate clockdomains for the interface clock and main - * functional clock, and can check whether they should acknowledge the - * idle request based on the internal module functionality that has - * been associated with the clocks marked in @clockact. This field is - * only used if HWMOD_SET_DEFAULT_CLOCKACT is set (see below) - * - */ -struct omap_hwmod_sysconfig { - u16 rev_offs; - u16 sysc_offs; - u16 syss_offs; - u8 idlemodes; - u8 sysc_flags; - u8 clockact; -}; - -/** - * struct omap_hwmod_omap2_prcm - OMAP2/3-specific PRCM data - * @module_offs: PRCM submodule offset from the start of the PRM/CM - * @prcm_reg_id: PRCM register ID (e.g., 3 for CM_AUTOIDLE3) - * @module_bit: register bit shift for AUTOIDLE, WKST, WKEN, GRPSEL regs - * @idlest_reg_id: IDLEST register ID (e.g., 3 for CM_IDLEST3) - * @idlest_idle_bit: register bit shift for CM_IDLEST slave idle bit - * @idlest_stdby_bit: register bit shift for CM_IDLEST master standby bit - * - * @prcm_reg_id and @module_bit are specific to the AUTOIDLE, WKST, - * WKEN, GRPSEL registers. In an ideal world, no extra information - * would be needed for IDLEST information, but alas, there are some - * exceptions, so @idlest_reg_id, @idlest_idle_bit, @idlest_stdby_bit - * are needed for the IDLEST registers (c.f. 2430 I2CHS, 3430 USBHOST) - */ -struct omap_hwmod_omap2_prcm { - s16 module_offs; - u8 prcm_reg_id; - u8 module_bit; - u8 idlest_reg_id; - u8 idlest_idle_bit; - u8 idlest_stdby_bit; -}; - - -/** - * struct omap_hwmod_omap4_prcm - OMAP4-specific PRCM data - * @module_offs: PRCM submodule offset from the start of the PRM/CM1/CM2 - * @device_offs: device register offset from @module_offs - * @submodule_wkdep_bit: bit shift of the WKDEP range - */ -struct omap_hwmod_omap4_prcm { - u32 module_offs; - u16 device_offs; - u8 submodule_wkdep_bit; -}; - - -/* - * omap_hwmod.flags definitions - * - * HWMOD_SWSUP_SIDLE: omap_hwmod code should manually bring module in and out - * of idle, rather than relying on module smart-idle - * HWMOD_SWSUP_MSTDBY: omap_hwmod code should manually bring module in and out - * of standby, rather than relying on module smart-standby - * HWMOD_INIT_NO_RESET: don't reset this module at boot - important for - * SDRAM controller, etc. - * HWMOD_INIT_NO_IDLE: don't idle this module at boot - important for SDRAM - * controller, etc. - * HWMOD_SET_DEFAULT_CLOCKACT: program CLOCKACTIVITY bits at startup - */ -#define HWMOD_SWSUP_SIDLE (1 << 0) -#define HWMOD_SWSUP_MSTANDBY (1 << 1) -#define HWMOD_INIT_NO_RESET (1 << 2) -#define HWMOD_INIT_NO_IDLE (1 << 3) -#define HWMOD_SET_DEFAULT_CLOCKACT (1 << 4) - -/* - * omap_hwmod._int_flags definitions - * These are for internal use only and are managed by the omap_hwmod code. - * - * _HWMOD_NO_MPU_PORT: no path exists for the MPU to write to this module - * _HWMOD_WAKEUP_ENABLED: set when the omap_hwmod code has enabled ENAWAKEUP - * _HWMOD_SYSCONFIG_LOADED: set when the OCP_SYSCONFIG value has been cached - */ -#define _HWMOD_NO_MPU_PORT (1 << 0) -#define _HWMOD_WAKEUP_ENABLED (1 << 1) -#define _HWMOD_SYSCONFIG_LOADED (1 << 2) - -/* - * omap_hwmod._state definitions - * - * INITIALIZED: reset (optionally), initialized, enabled, disabled - * (optionally) - * - * - */ -#define _HWMOD_STATE_UNKNOWN 0 -#define _HWMOD_STATE_REGISTERED 1 -#define _HWMOD_STATE_CLKS_INITED 2 -#define _HWMOD_STATE_INITIALIZED 3 -#define _HWMOD_STATE_ENABLED 4 -#define _HWMOD_STATE_IDLE 5 -#define _HWMOD_STATE_DISABLED 6 - -/** - * struct omap_hwmod - integration data for OMAP hardware "modules" (IP blocks) - * @name: name of the hwmod - * @od: struct omap_device currently associated with this hwmod (internal use) - * @mpu_irqs: ptr to an array of MPU IRQs (see also mpu_irqs_cnt) - * @sdma_chs: ptr to an array of SDMA channel IDs (see also sdma_chs_cnt) - * @prcm: PRCM data pertaining to this hwmod - * @clkdev_dev_id: main clock: clkdev dev_id string - * @clkdev_con_id: main clock: clkdev con_id string - * @_clk: pointer to the main struct clk (filled in at runtime) - * @opt_clks: other device clocks that drivers can request (0..*) - * @masters: ptr to array of OCP ifs that this hwmod can initiate on - * @slaves: ptr to array of OCP ifs that this hwmod can respond on - * @sysconfig: device SYSCONFIG/SYSSTATUS register data - * @dev_attr: arbitrary device attributes that can be passed to the driver - * @_sysc_cache: internal-use hwmod flags - * @_rt_va: cached register target start address (internal use) - * @_mpu_port_index: cached MPU register target slave ID (internal use) - * @msuspendmux_reg_id: CONTROL_MSUSPENDMUX register ID (1-6) - * @msuspendmux_shift: CONTROL_MSUSPENDMUX register bit shift - * @mpu_irqs_cnt: number of @mpu_irqs - * @sdma_chs_cnt: number of @sdma_chs - * @opt_clks_cnt: number of @opt_clks - * @master_cnt: number of @master entries - * @slaves_cnt: number of @slave entries - * @response_lat: device OCP response latency (in interface clock cycles) - * @_int_flags: internal-use hwmod flags - * @_state: internal-use hwmod state - * @flags: hwmod flags (documented below) - * @omap_chip: OMAP chips this hwmod is present on - * @node: list node for hwmod list (internal use) - * - * @clkdev_dev_id, @clkdev_con_id, and @clk all refer to this module's "main - * clock," which for our purposes is defined as "the functional clock needed - * for register accesses to complete." Modules may not have a main clock if - * the interface clock also serves as a main clock. - * - * Parameter names beginning with an underscore are managed internally by - * the omap_hwmod code and should not be set during initialization. - */ -struct omap_hwmod { - const char *name; - struct omap_device *od; - u8 *mpu_irqs; - struct omap_hwmod_dma_info *sdma_chs; - union { - struct omap_hwmod_omap2_prcm omap2; - struct omap_hwmod_omap4_prcm omap4; - } prcm; - const char *clkdev_dev_id; - const char *clkdev_con_id; - struct clk *_clk; - struct omap_hwmod_opt_clk *opt_clks; - struct omap_hwmod_ocp_if **masters; /* connect to *_IA */ - struct omap_hwmod_ocp_if **slaves; /* connect to *_TA */ - struct omap_hwmod_sysconfig *sysconfig; - void *dev_attr; - u32 _sysc_cache; - void __iomem *_rt_va; - struct list_head node; - u16 flags; - u8 _mpu_port_index; - u8 msuspendmux_reg_id; - u8 msuspendmux_shift; - u8 response_lat; - u8 mpu_irqs_cnt; - u8 sdma_chs_cnt; - u8 opt_clks_cnt; - u8 masters_cnt; - u8 slaves_cnt; - u8 hwmods_cnt; - u8 _int_flags; - u8 _state; - const struct omap_chip_id omap_chip; -}; - -int omap_hwmod_init(struct omap_hwmod **ohs); -int omap_hwmod_register(struct omap_hwmod *oh); -int omap_hwmod_unregister(struct omap_hwmod *oh); -struct omap_hwmod *omap_hwmod_lookup(const char *name); -int omap_hwmod_for_each(int (*fn)(struct omap_hwmod *oh)); -int omap_hwmod_late_init(void); - -int omap_hwmod_enable(struct omap_hwmod *oh); -int omap_hwmod_idle(struct omap_hwmod *oh); -int omap_hwmod_shutdown(struct omap_hwmod *oh); - -int omap_hwmod_enable_clocks(struct omap_hwmod *oh); -int omap_hwmod_disable_clocks(struct omap_hwmod *oh); - -int omap_hwmod_reset(struct omap_hwmod *oh); -void omap_hwmod_ocp_barrier(struct omap_hwmod *oh); - -void omap_hwmod_writel(u32 v, struct omap_hwmod *oh, u16 reg_offs); -u32 omap_hwmod_readl(struct omap_hwmod *oh, u16 reg_offs); - -int omap_hwmod_count_resources(struct omap_hwmod *oh); -int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res); - -struct powerdomain *omap_hwmod_get_pwrdm(struct omap_hwmod *oh); - -int omap_hwmod_add_initiator_dep(struct omap_hwmod *oh, - struct omap_hwmod *init_oh); -int omap_hwmod_del_initiator_dep(struct omap_hwmod *oh, - struct omap_hwmod *init_oh); - -int omap_hwmod_set_clockact_both(struct omap_hwmod *oh); -int omap_hwmod_set_clockact_main(struct omap_hwmod *oh); -int omap_hwmod_set_clockact_iclk(struct omap_hwmod *oh); -int omap_hwmod_set_clockact_none(struct omap_hwmod *oh); - -int omap_hwmod_enable_wakeup(struct omap_hwmod *oh); -int omap_hwmod_disable_wakeup(struct omap_hwmod *oh); - -#endif diff --git a/arch/arm/plat-omap/include/mach/omapfb.h b/arch/arm/plat-omap/include/mach/omapfb.h deleted file mode 100644 index b226bdf4573..00000000000 --- a/arch/arm/plat-omap/include/mach/omapfb.h +++ /dev/null @@ -1,398 +0,0 @@ -/* - * File: arch/arm/plat-omap/include/mach/omapfb.h - * - * Framebuffer driver for TI OMAP boards - * - * Copyright (C) 2004 Nokia Corporation - * Author: Imre Deak <imre.deak@nokia.com> - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * This program is distributed in the hope that it will be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. - */ - -#ifndef __OMAPFB_H -#define __OMAPFB_H - -#include <asm/ioctl.h> -#include <asm/types.h> - -/* IOCTL commands. */ - -#define OMAP_IOW(num, dtype) _IOW('O', num, dtype) -#define OMAP_IOR(num, dtype) _IOR('O', num, dtype) -#define OMAP_IOWR(num, dtype) _IOWR('O', num, dtype) -#define OMAP_IO(num) _IO('O', num) - -#define OMAPFB_MIRROR OMAP_IOW(31, int) -#define OMAPFB_SYNC_GFX OMAP_IO(37) -#define OMAPFB_VSYNC OMAP_IO(38) -#define OMAPFB_SET_UPDATE_MODE OMAP_IOW(40, int) -#define OMAPFB_GET_CAPS OMAP_IOR(42, struct omapfb_caps) -#define OMAPFB_GET_UPDATE_MODE OMAP_IOW(43, int) -#define OMAPFB_LCD_TEST OMAP_IOW(45, int) -#define OMAPFB_CTRL_TEST OMAP_IOW(46, int) -#define OMAPFB_UPDATE_WINDOW_OLD OMAP_IOW(47, struct omapfb_update_window_old) -#define OMAPFB_SET_COLOR_KEY OMAP_IOW(50, struct omapfb_color_key) -#define OMAPFB_GET_COLOR_KEY OMAP_IOW(51, struct omapfb_color_key) -#define OMAPFB_SETUP_PLANE OMAP_IOW(52, struct omapfb_plane_info) -#define OMAPFB_QUERY_PLANE OMAP_IOW(53, struct omapfb_plane_info) -#define OMAPFB_UPDATE_WINDOW OMAP_IOW(54, struct omapfb_update_window) -#define OMAPFB_SETUP_MEM OMAP_IOW(55, struct omapfb_mem_info) -#define OMAPFB_QUERY_MEM OMAP_IOW(56, struct omapfb_mem_info) - -#define OMAPFB_CAPS_GENERIC_MASK 0x00000fff -#define OMAPFB_CAPS_LCDC_MASK 0x00fff000 -#define OMAPFB_CAPS_PANEL_MASK 0xff000000 - -#define OMAPFB_CAPS_MANUAL_UPDATE 0x00001000 -#define OMAPFB_CAPS_TEARSYNC 0x00002000 -#define OMAPFB_CAPS_PLANE_RELOCATE_MEM 0x00004000 -#define OMAPFB_CAPS_PLANE_SCALE 0x00008000 -#define OMAPFB_CAPS_WINDOW_PIXEL_DOUBLE 0x00010000 -#define OMAPFB_CAPS_WINDOW_SCALE 0x00020000 -#define OMAPFB_CAPS_WINDOW_OVERLAY 0x00040000 -#define OMAPFB_CAPS_WINDOW_ROTATE 0x00080000 -#define OMAPFB_CAPS_SET_BACKLIGHT 0x01000000 - -/* Values from DSP must map to lower 16-bits */ -#define OMAPFB_FORMAT_MASK 0x00ff -#define OMAPFB_FORMAT_FLAG_DOUBLE 0x0100 -#define OMAPFB_FORMAT_FLAG_TEARSYNC 0x0200 -#define OMAPFB_FORMAT_FLAG_FORCE_VSYNC 0x0400 -#define OMAPFB_FORMAT_FLAG_ENABLE_OVERLAY 0x0800 -#define OMAPFB_FORMAT_FLAG_DISABLE_OVERLAY 0x1000 - -#define OMAPFB_EVENT_READY 1 -#define OMAPFB_EVENT_DISABLED 2 - -#define OMAPFB_MEMTYPE_SDRAM 0 -#define OMAPFB_MEMTYPE_SRAM 1 -#define OMAPFB_MEMTYPE_MAX 1 - -enum omapfb_color_format { - OMAPFB_COLOR_RGB565 = 0, - OMAPFB_COLOR_YUV422, - OMAPFB_COLOR_YUV420, - OMAPFB_COLOR_CLUT_8BPP, - OMAPFB_COLOR_CLUT_4BPP, - OMAPFB_COLOR_CLUT_2BPP, - OMAPFB_COLOR_CLUT_1BPP, - OMAPFB_COLOR_RGB444, - OMAPFB_COLOR_YUY422, -}; - -struct omapfb_update_window { - __u32 x, y; - __u32 width, height; - __u32 format; - __u32 out_x, out_y; - __u32 out_width, out_height; - __u32 reserved[8]; -}; - -struct omapfb_update_window_old { - __u32 x, y; - __u32 width, height; - __u32 format; -}; - -enum omapfb_plane { - OMAPFB_PLANE_GFX = 0, - OMAPFB_PLANE_VID1, - OMAPFB_PLANE_VID2, -}; - -enum omapfb_channel_out { - OMAPFB_CHANNEL_OUT_LCD = 0, - OMAPFB_CHANNEL_OUT_DIGIT, -}; - -struct omapfb_plane_info { - __u32 pos_x; - __u32 pos_y; - __u8 enabled; - __u8 channel_out; - __u8 mirror; - __u8 reserved1; - __u32 out_width; - __u32 out_height; - __u32 reserved2[12]; -}; - -struct omapfb_mem_info { - __u32 size; - __u8 type; - __u8 reserved[3]; -}; - -struct omapfb_caps { - __u32 ctrl; - __u32 plane_color; - __u32 wnd_color; -}; - -enum omapfb_color_key_type { - OMAPFB_COLOR_KEY_DISABLED = 0, - OMAPFB_COLOR_KEY_GFX_DST, - OMAPFB_COLOR_KEY_VID_SRC, -}; - -struct omapfb_color_key { - __u8 channel_out; - __u32 background; - __u32 trans_key; - __u8 key_type; -}; - -enum omapfb_update_mode { - OMAPFB_UPDATE_DISABLED = 0, - OMAPFB_AUTO_UPDATE, - OMAPFB_MANUAL_UPDATE -}; - -#ifdef __KERNEL__ - -#include <linux/completion.h> -#include <linux/interrupt.h> -#include <linux/fb.h> -#include <linux/mutex.h> - -#include <mach/board.h> - -#define OMAP_LCDC_INV_VSYNC 0x0001 -#define OMAP_LCDC_INV_HSYNC 0x0002 -#define OMAP_LCDC_INV_PIX_CLOCK 0x0004 -#define OMAP_LCDC_INV_OUTPUT_EN 0x0008 -#define OMAP_LCDC_HSVS_RISING_EDGE 0x0010 -#define OMAP_LCDC_HSVS_OPPOSITE 0x0020 - -#define OMAP_LCDC_SIGNAL_MASK 0x003f - -#define OMAP_LCDC_PANEL_TFT 0x0100 - -#define OMAPFB_PLANE_XRES_MIN 8 -#define OMAPFB_PLANE_YRES_MIN 8 - -#ifdef CONFIG_ARCH_OMAP1 -#define OMAPFB_PLANE_NUM 1 -#else -#define OMAPFB_PLANE_NUM 3 -#endif - -struct omapfb_device; - -struct lcd_panel { - const char *name; - int config; /* TFT/STN, signal inversion */ - int bpp; /* Pixel format in fb mem */ - int data_lines; /* Lines on LCD HW interface */ - - int x_res, y_res; - int pixel_clock; /* In kHz */ - int hsw; /* Horizontal synchronization - pulse width */ - int hfp; /* Horizontal front porch */ - int hbp; /* Horizontal back porch */ - int vsw; /* Vertical synchronization - pulse width */ - int vfp; /* Vertical front porch */ - int vbp; /* Vertical back porch */ - int acb; /* ac-bias pin frequency */ - int pcd; /* pixel clock divider. - Obsolete use pixel_clock instead */ - - int (*init) (struct lcd_panel *panel, - struct omapfb_device *fbdev); - void (*cleanup) (struct lcd_panel *panel); - int (*enable) (struct lcd_panel *panel); - void (*disable) (struct lcd_panel *panel); - unsigned long (*get_caps) (struct lcd_panel *panel); - int (*set_bklight_level)(struct lcd_panel *panel, - unsigned int level); - unsigned int (*get_bklight_level)(struct lcd_panel *panel); - unsigned int (*get_bklight_max) (struct lcd_panel *panel); - int (*run_test) (struct lcd_panel *panel, int test_num); -}; - -struct extif_timings { - int cs_on_time; - int cs_off_time; - int we_on_time; - int we_off_time; - int re_on_time; - int re_off_time; - int we_cycle_time; - int re_cycle_time; - int cs_pulse_width; - int access_time; - - int clk_div; - - u32 tim[5]; /* set by extif->convert_timings */ - - int converted; -}; - -struct lcd_ctrl_extif { - int (*init) (struct omapfb_device *fbdev); - void (*cleanup) (void); - void (*get_clk_info) (u32 *clk_period, u32 *max_clk_div); - unsigned long (*get_max_tx_rate)(void); - int (*convert_timings) (struct extif_timings *timings); - void (*set_timings) (const struct extif_timings *timings); - void (*set_bits_per_cycle)(int bpc); - void (*write_command) (const void *buf, unsigned int len); - void (*read_data) (void *buf, unsigned int len); - void (*write_data) (const void *buf, unsigned int len); - void (*transfer_area) (int width, int height, - void (callback)(void * data), void *data); - int (*setup_tearsync) (unsigned pin_cnt, - unsigned hs_pulse_time, unsigned vs_pulse_time, - int hs_pol_inv, int vs_pol_inv, int div); - int (*enable_tearsync) (int enable, unsigned line); - - unsigned long max_transmit_size; -}; - -struct omapfb_notifier_block { - struct notifier_block nb; - void *data; - int plane_idx; -}; - -typedef int (*omapfb_notifier_callback_t)(struct notifier_block *, - unsigned long event, - void *fbi); - -struct omapfb_mem_region { - u32 paddr; - void __iomem *vaddr; - unsigned long size; - u8 type; /* OMAPFB_PLANE_MEM_* */ - unsigned alloc:1; /* allocated by the driver */ - unsigned map:1; /* kernel mapped by the driver */ -}; - -struct omapfb_mem_desc { - int region_cnt; - struct omapfb_mem_region region[OMAPFB_PLANE_NUM]; -}; - -struct lcd_ctrl { - const char *name; - void *data; - - int (*init) (struct omapfb_device *fbdev, - int ext_mode, - struct omapfb_mem_desc *req_md); - void (*cleanup) (void); - void (*bind_client) (struct omapfb_notifier_block *nb); - void (*get_caps) (int plane, struct omapfb_caps *caps); - int (*set_update_mode)(enum omapfb_update_mode mode); - enum omapfb_update_mode (*get_update_mode)(void); - int (*setup_plane) (int plane, int channel_out, - unsigned long offset, - int screen_width, - int pos_x, int pos_y, int width, - int height, int color_mode); - int (*set_rotate) (int angle); - int (*setup_mem) (int plane, size_t size, - int mem_type, unsigned long *paddr); - int (*mmap) (struct fb_info *info, - struct vm_area_struct *vma); - int (*set_scale) (int plane, - int orig_width, int orig_height, - int out_width, int out_height); - int (*enable_plane) (int plane, int enable); - int (*update_window) (struct fb_info *fbi, - struct omapfb_update_window *win, - void (*callback)(void *), - void *callback_data); - void (*sync) (void); - void (*suspend) (void); - void (*resume) (void); - int (*run_test) (int test_num); - int (*setcolreg) (u_int regno, u16 red, u16 green, - u16 blue, u16 transp, - int update_hw_mem); - int (*set_color_key) (struct omapfb_color_key *ck); - int (*get_color_key) (struct omapfb_color_key *ck); -}; - -enum omapfb_state { - OMAPFB_DISABLED = 0, - OMAPFB_SUSPENDED= 99, - OMAPFB_ACTIVE = 100 -}; - -struct omapfb_plane_struct { - int idx; - struct omapfb_plane_info info; - enum omapfb_color_format color_mode; - struct omapfb_device *fbdev; -}; - -struct omapfb_device { - int state; - int ext_lcdc; /* Using external - LCD controller */ - struct mutex rqueue_mutex; - - int palette_size; - u32 pseudo_palette[17]; - - struct lcd_panel *panel; /* LCD panel */ - const struct lcd_ctrl *ctrl; /* LCD controller */ - const struct lcd_ctrl *int_ctrl; /* internal LCD ctrl */ - struct lcd_ctrl_extif *ext_if; /* LCD ctrl external - interface */ - struct device *dev; - struct fb_var_screeninfo new_var; /* for mode changes */ - - struct omapfb_mem_desc mem_desc; - struct fb_info *fb_info[OMAPFB_PLANE_NUM]; -}; - -struct omapfb_platform_data { - struct omap_lcd_config lcd; - struct omapfb_mem_desc mem_desc; - void *ctrl_platform_data; -}; - -#ifdef CONFIG_ARCH_OMAP1 -extern struct lcd_ctrl omap1_lcd_ctrl; -#else -extern struct lcd_ctrl omap2_disp_ctrl; -#endif - -extern void omapfb_reserve_sdram(void); -extern void omapfb_register_panel(struct lcd_panel *panel); -extern void omapfb_write_first_pixel(struct omapfb_device *fbdev, u16 pixval); -extern void omapfb_notify_clients(struct omapfb_device *fbdev, - unsigned long event); -extern int omapfb_register_client(struct omapfb_notifier_block *nb, - omapfb_notifier_callback_t callback, - void *callback_data); -extern int omapfb_unregister_client(struct omapfb_notifier_block *nb); -extern int omapfb_update_window_async(struct fb_info *fbi, - struct omapfb_update_window *win, - void (*callback)(void *), - void *callback_data); - -/* in arch/arm/plat-omap/fb.c */ -extern void omapfb_set_ctrl_platform_data(void *pdata); - -#endif /* __KERNEL__ */ - -#endif /* __OMAPFB_H */ diff --git a/arch/arm/plat-omap/include/mach/onenand.h b/arch/arm/plat-omap/include/mach/onenand.h deleted file mode 100644 index 72f433d7d82..00000000000 --- a/arch/arm/plat-omap/include/mach/onenand.h +++ /dev/null @@ -1,43 +0,0 @@ -/* - * arch/arm/plat-omap/include/mach/onenand.h - * - * Copyright (C) 2006 Nokia Corporation - * Author: Juha Yrjola - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include <linux/mtd/mtd.h> -#include <linux/mtd/partitions.h> - -#define ONENAND_SYNC_READ (1 << 0) -#define ONENAND_SYNC_READWRITE (1 << 1) - -struct omap_onenand_platform_data { - int cs; - int gpio_irq; - struct mtd_partition *parts; - int nr_parts; - int (*onenand_setup)(void __iomem *, int freq); - int dma_channel; - u8 flags; -}; - -#define ONENAND_MAX_PARTITIONS 8 - -#if defined(CONFIG_MTD_ONENAND_OMAP2) || \ - defined(CONFIG_MTD_ONENAND_OMAP2_MODULE) - -extern void gpmc_onenand_init(struct omap_onenand_platform_data *d); - -#else - -#define board_onenand_data NULL - -static inline void gpmc_onenand_init(struct omap_onenand_platform_data *d) -{ -} - -#endif diff --git a/arch/arm/plat-omap/include/mach/param.h b/arch/arm/plat-omap/include/mach/param.h deleted file mode 100644 index 1eb4dc32697..00000000000 --- a/arch/arm/plat-omap/include/mach/param.h +++ /dev/null @@ -1,8 +0,0 @@ -/* - * arch/arm/plat-omap/include/mach/param.h - * - */ - -#ifdef CONFIG_OMAP_32K_TIMER_HZ -#define HZ CONFIG_OMAP_32K_TIMER_HZ -#endif diff --git a/arch/arm/plat-omap/include/mach/powerdomain.h b/arch/arm/plat-omap/include/mach/powerdomain.h deleted file mode 100644 index fa6461423bd..00000000000 --- a/arch/arm/plat-omap/include/mach/powerdomain.h +++ /dev/null @@ -1,182 +0,0 @@ -/* - * OMAP2/3 powerdomain control - * - * Copyright (C) 2007-8 Texas Instruments, Inc. - * Copyright (C) 2007-8 Nokia Corporation - * - * Written by Paul Walmsley - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef ASM_ARM_ARCH_OMAP_POWERDOMAIN -#define ASM_ARM_ARCH_OMAP_POWERDOMAIN - -#include <linux/types.h> -#include <linux/list.h> - -#include <asm/atomic.h> - -#include <mach/cpu.h> - - -/* Powerdomain basic power states */ -#define PWRDM_POWER_OFF 0x0 -#define PWRDM_POWER_RET 0x1 -#define PWRDM_POWER_INACTIVE 0x2 -#define PWRDM_POWER_ON 0x3 - -/* Powerdomain allowable state bitfields */ -#define PWRSTS_OFF_ON ((1 << PWRDM_POWER_OFF) | \ - (1 << PWRDM_POWER_ON)) - -#define PWRSTS_OFF_RET ((1 << PWRDM_POWER_OFF) | \ - (1 << PWRDM_POWER_RET)) - -#define PWRSTS_OFF_RET_ON (PWRSTS_OFF_RET | (1 << PWRDM_POWER_ON)) - - -/* Powerdomain flags */ -#define PWRDM_HAS_HDWR_SAR (1 << 0) /* hardware save-and-restore support */ - - -/* - * Number of memory banks that are power-controllable. On OMAP3430, the - * maximum is 4. - */ -#define PWRDM_MAX_MEM_BANKS 4 - -/* - * Maximum number of clockdomains that can be associated with a powerdomain. - * CORE powerdomain on OMAP3 is the worst case - */ -#define PWRDM_MAX_CLKDMS 4 - -/* XXX A completely arbitrary number. What is reasonable here? */ -#define PWRDM_TRANSITION_BAILOUT 100000 - -struct clockdomain; -struct powerdomain; - -/* Encodes dependencies between powerdomains - statically defined */ -struct pwrdm_dep { - - /* Powerdomain name */ - const char *pwrdm_name; - - /* Powerdomain pointer - resolved by the powerdomain code */ - struct powerdomain *pwrdm; - - /* Flags to mark OMAP chip restrictions, etc. */ - const struct omap_chip_id omap_chip; - -}; - -struct powerdomain { - - /* Powerdomain name */ - const char *name; - - /* the address offset from CM_BASE/PRM_BASE */ - const s16 prcm_offs; - - /* Used to represent the OMAP chip types containing this pwrdm */ - const struct omap_chip_id omap_chip; - - /* Bit shift of this powerdomain's PM_WKDEP/CM_SLEEPDEP bit */ - const u8 dep_bit; - - /* Powerdomains that can be told to wake this powerdomain up */ - struct pwrdm_dep *wkdep_srcs; - - /* Powerdomains that can be told to keep this pwrdm from inactivity */ - struct pwrdm_dep *sleepdep_srcs; - - /* Possible powerdomain power states */ - const u8 pwrsts; - - /* Possible logic power states when pwrdm in RETENTION */ - const u8 pwrsts_logic_ret; - - /* Powerdomain flags */ - const u8 flags; - - /* Number of software-controllable memory banks in this powerdomain */ - const u8 banks; - - /* Possible memory bank pwrstates when pwrdm in RETENTION */ - const u8 pwrsts_mem_ret[PWRDM_MAX_MEM_BANKS]; - - /* Possible memory bank pwrstates when pwrdm is ON */ - const u8 pwrsts_mem_on[PWRDM_MAX_MEM_BANKS]; - - /* Clockdomains in this powerdomain */ - struct clockdomain *pwrdm_clkdms[PWRDM_MAX_CLKDMS]; - - struct list_head node; - - int state; - unsigned state_counter[4]; - -#ifdef CONFIG_PM_DEBUG - s64 timer; - s64 state_timer[4]; -#endif -}; - - -void pwrdm_init(struct powerdomain **pwrdm_list); - -int pwrdm_register(struct powerdomain *pwrdm); -int pwrdm_unregister(struct powerdomain *pwrdm); -struct powerdomain *pwrdm_lookup(const char *name); - -int pwrdm_for_each(int (*fn)(struct powerdomain *pwrdm, void *user), - void *user); -int pwrdm_for_each_nolock(int (*fn)(struct powerdomain *pwrdm, void *user), - void *user); - -int pwrdm_add_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm); -int pwrdm_del_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm); -int pwrdm_for_each_clkdm(struct powerdomain *pwrdm, - int (*fn)(struct powerdomain *pwrdm, - struct clockdomain *clkdm)); - -int pwrdm_add_wkdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2); -int pwrdm_del_wkdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2); -int pwrdm_read_wkdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2); -int pwrdm_add_sleepdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2); -int pwrdm_del_sleepdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2); -int pwrdm_read_sleepdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2); - -int pwrdm_get_mem_bank_count(struct powerdomain *pwrdm); - -int pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst); -int pwrdm_read_next_pwrst(struct powerdomain *pwrdm); -int pwrdm_read_pwrst(struct powerdomain *pwrdm); -int pwrdm_read_prev_pwrst(struct powerdomain *pwrdm); -int pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm); - -int pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst); -int pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, u8 pwrst); -int pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, u8 pwrst); - -int pwrdm_read_logic_pwrst(struct powerdomain *pwrdm); -int pwrdm_read_prev_logic_pwrst(struct powerdomain *pwrdm); -int pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank); -int pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank); - -int pwrdm_enable_hdwr_sar(struct powerdomain *pwrdm); -int pwrdm_disable_hdwr_sar(struct powerdomain *pwrdm); -bool pwrdm_has_hdwr_sar(struct powerdomain *pwrdm); - -int pwrdm_wait_transition(struct powerdomain *pwrdm); - -int pwrdm_state_switch(struct powerdomain *pwrdm); -int pwrdm_clkdm_state_switch(struct clockdomain *clkdm); -int pwrdm_pre_transition(void); -int pwrdm_post_transition(void); - -#endif diff --git a/arch/arm/plat-omap/include/mach/prcm.h b/arch/arm/plat-omap/include/mach/prcm.h deleted file mode 100644 index cda2a70397b..00000000000 --- a/arch/arm/plat-omap/include/mach/prcm.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * arch/arm/plat-omap/include/mach/prcm.h - * - * Access definations for use in OMAP24XX clock and power management - * - * Copyright (C) 2005 Texas Instruments, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ - -#ifndef __ASM_ARM_ARCH_OMAP_PRCM_H -#define __ASM_ARM_ARCH_OMAP_PRCM_H - -u32 omap_prcm_get_reset_sources(void); -void omap_prcm_arch_reset(char mode); -int omap2_cm_wait_idlest(void __iomem *reg, u32 mask, const char *name); - -#endif - - - - - diff --git a/arch/arm/plat-omap/include/mach/sdrc.h b/arch/arm/plat-omap/include/mach/sdrc.h deleted file mode 100644 index 1c09c78a48f..00000000000 --- a/arch/arm/plat-omap/include/mach/sdrc.h +++ /dev/null @@ -1,143 +0,0 @@ -#ifndef ____ASM_ARCH_SDRC_H -#define ____ASM_ARCH_SDRC_H - -/* - * OMAP2/3 SDRC/SMS register definitions - * - * Copyright (C) 2007-2008 Texas Instruments, Inc. - * Copyright (C) 2007-2008 Nokia Corporation - * - * Tony Lindgren - * Paul Walmsley - * Richard Woodruff - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include <mach/io.h> - -/* SDRC register offsets - read/write with sdrc_{read,write}_reg() */ - -#define SDRC_SYSCONFIG 0x010 -#define SDRC_CS_CFG 0x040 -#define SDRC_SHARING 0x044 -#define SDRC_ERR_TYPE 0x04C -#define SDRC_DLLA_CTRL 0x060 -#define SDRC_DLLA_STATUS 0x064 -#define SDRC_DLLB_CTRL 0x068 -#define SDRC_DLLB_STATUS 0x06C -#define SDRC_POWER 0x070 -#define SDRC_MCFG_0 0x080 -#define SDRC_MR_0 0x084 -#define SDRC_EMR2_0 0x08c -#define SDRC_ACTIM_CTRL_A_0 0x09c -#define SDRC_ACTIM_CTRL_B_0 0x0a0 -#define SDRC_RFR_CTRL_0 0x0a4 -#define SDRC_MANUAL_0 0x0a8 -#define SDRC_MCFG_1 0x0B0 -#define SDRC_MR_1 0x0B4 -#define SDRC_EMR2_1 0x0BC -#define SDRC_ACTIM_CTRL_A_1 0x0C4 -#define SDRC_ACTIM_CTRL_B_1 0x0C8 -#define SDRC_RFR_CTRL_1 0x0D4 -#define SDRC_MANUAL_1 0x0D8 - -/* - * These values represent the number of memory clock cycles between - * autorefresh initiation. They assume 1 refresh per 64 ms (JEDEC), 8192 - * rows per device, and include a subtraction of a 50 cycle window in the - * event that the autorefresh command is delayed due to other SDRC activity. - * The '| 1' sets the ARE field to send one autorefresh when the autorefresh - * counter reaches 0. - * - * These represent optimal values for common parts, it won't work for all. - * As long as you scale down, most parameters are still work, they just - * become sub-optimal. The RFR value goes in the opposite direction. If you - * don't adjust it down as your clock period increases the refresh interval - * will not be met. Setting all parameters for complete worst case may work, - * but may cut memory performance by 2x. Due to errata the DLLs need to be - * unlocked and their value needs run time calibration. A dynamic call is - * need for that as no single right value exists acorss production samples. - * - * Only the FULL speed values are given. Current code is such that rate - * changes must be made at DPLLoutx2. The actual value adjustment for low - * frequency operation will be handled by omap_set_performance() - * - * By having the boot loader boot up in the fastest L4 speed available likely - * will result in something which you can switch between. - */ -#define SDRC_RFR_CTRL_165MHz (0x00044c00 | 1) -#define SDRC_RFR_CTRL_133MHz (0x0003de00 | 1) -#define SDRC_RFR_CTRL_100MHz (0x0002da01 | 1) -#define SDRC_RFR_CTRL_110MHz (0x0002da01 | 1) /* Need to calc */ -#define SDRC_RFR_CTRL_BYPASS (0x00005000 | 1) /* Need to calc */ - - -/* - * SMS register access - */ - -#define OMAP242X_SMS_REGADDR(reg) \ - (void __iomem *)OMAP2_IO_ADDRESS(OMAP2420_SMS_BASE + reg) -#define OMAP243X_SMS_REGADDR(reg) \ - (void __iomem *)OMAP2_IO_ADDRESS(OMAP243X_SMS_BASE + reg) -#define OMAP343X_SMS_REGADDR(reg) \ - (void __iomem *)OMAP2_IO_ADDRESS(OMAP343X_SMS_BASE + reg) - -/* SMS register offsets - read/write with sms_{read,write}_reg() */ - -#define SMS_SYSCONFIG 0x010 -/* REVISIT: fill in other SMS registers here */ - - -#ifndef __ASSEMBLER__ - -/** - * struct omap_sdrc_params - SDRC parameters for a given SDRC clock rate - * @rate: SDRC clock rate (in Hz) - * @actim_ctrla: Value to program to SDRC_ACTIM_CTRLA for this rate - * @actim_ctrlb: Value to program to SDRC_ACTIM_CTRLB for this rate - * @rfr_ctrl: Value to program to SDRC_RFR_CTRL for this rate - * @mr: Value to program to SDRC_MR for this rate - * - * This structure holds a pre-computed set of register values for the - * SDRC for a given SDRC clock rate and SDRAM chip. These are - * intended to be pre-computed and specified in an array in the board-*.c - * files. The structure is keyed off the 'rate' field. - */ -struct omap_sdrc_params { - unsigned long rate; - u32 actim_ctrla; - u32 actim_ctrlb; - u32 rfr_ctrl; - u32 mr; -}; - -void __init omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0, - struct omap_sdrc_params *sdrc_cs1); -int omap2_sdrc_get_params(unsigned long r, - struct omap_sdrc_params **sdrc_cs0, - struct omap_sdrc_params **sdrc_cs1); - -#ifdef CONFIG_ARCH_OMAP2 - -struct memory_timings { - u32 m_type; /* ddr = 1, sdr = 0 */ - u32 dll_mode; /* use lock mode = 1, unlock mode = 0 */ - u32 slow_dll_ctrl; /* unlock mode, dll value for slow speed */ - u32 fast_dll_ctrl; /* unlock mode, dll value for fast speed */ - u32 base_cs; /* base chip select to use for calculations */ -}; - -extern void omap2xxx_sdrc_init_params(u32 force_lock_to_unlock_mode); - -u32 omap2xxx_sdrc_dll_is_unlocked(void); -u32 omap2xxx_sdrc_reprogram(u32 level, u32 force); - -#endif /* CONFIG_ARCH_OMAP2 */ - -#endif /* __ASSEMBLER__ */ - -#endif diff --git a/arch/arm/plat-omap/include/mach/serial.h b/arch/arm/plat-omap/include/mach/serial.h deleted file mode 100644 index e249186d26e..00000000000 --- a/arch/arm/plat-omap/include/mach/serial.h +++ /dev/null @@ -1,68 +0,0 @@ -/* - * arch/arm/plat-omap/include/mach/serial.h - * - * Copyright (C) 2009 Texas Instruments - * Addded OMAP4 support- Santosh Shilimkar <santosh.shilimkar@ti.com> - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __ASM_ARCH_SERIAL_H -#define __ASM_ARCH_SERIAL_H - -#include <linux/init.h> - -#if defined(CONFIG_ARCH_OMAP1) -/* OMAP1 serial ports */ -#define OMAP_UART1_BASE 0xfffb0000 -#define OMAP_UART2_BASE 0xfffb0800 -#define OMAP_UART3_BASE 0xfffb9800 -#define OMAP_MAX_NR_PORTS 3 -#elif defined(CONFIG_ARCH_OMAP2) -/* OMAP2 serial ports */ -#define OMAP_UART1_BASE 0x4806a000 -#define OMAP_UART2_BASE 0x4806c000 -#define OMAP_UART3_BASE 0x4806e000 -#define OMAP_MAX_NR_PORTS 3 -#elif defined(CONFIG_ARCH_OMAP3) -/* OMAP3 serial ports */ -#define OMAP_UART1_BASE 0x4806a000 -#define OMAP_UART2_BASE 0x4806c000 -#define OMAP_UART3_BASE 0x49020000 -#define OMAP_MAX_NR_PORTS 3 -#elif defined(CONFIG_ARCH_OMAP4) -/* OMAP4 serial ports */ -#define OMAP_UART1_BASE 0x4806a000 -#define OMAP_UART2_BASE 0x4806c000 -#define OMAP_UART3_BASE 0x48020000 -#define OMAP_UART4_BASE 0x4806e000 -#define OMAP_MAX_NR_PORTS 4 -#endif - -#define OMAP1510_BASE_BAUD (12000000/16) -#define OMAP16XX_BASE_BAUD (48000000/16) -#define OMAP24XX_BASE_BAUD (48000000/16) - -#define is_omap_port(pt) ({int __ret = 0; \ - if ((pt)->port.mapbase == OMAP_UART1_BASE || \ - (pt)->port.mapbase == OMAP_UART2_BASE || \ - (pt)->port.mapbase == OMAP_UART3_BASE) \ - __ret = 1; \ - __ret; \ - }) - -#ifndef __ASSEMBLER__ -extern void __init omap_serial_early_init(void); -extern void omap_serial_init(void); -extern int omap_uart_can_sleep(void); -extern void omap_uart_check_wakeup(void); -extern void omap_uart_prepare_suspend(void); -extern void omap_uart_prepare_idle(int num); -extern void omap_uart_resume_idle(int num); -extern void omap_uart_enable_irqs(int enable); -#endif - -#endif diff --git a/arch/arm/plat-omap/include/mach/smp.h b/arch/arm/plat-omap/include/mach/smp.h deleted file mode 100644 index dcaa8fde706..00000000000 --- a/arch/arm/plat-omap/include/mach/smp.h +++ /dev/null @@ -1,51 +0,0 @@ -/* - * OMAP4 machine specific smp.h - * - * Copyright (C) 2009 Texas Instruments, Inc. - * - * Author: - * Santosh Shilimkar <santosh.shilimkar@ti.com> - * - * Interface functions needed for the SMP. This file is based on arm - * realview smp platform. - * Copyright (c) 2003 ARM Limited. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#ifndef OMAP_ARCH_SMP_H -#define OMAP_ARCH_SMP_H - -#include <asm/hardware/gic.h> - -/* - * set_event() is used to wake up secondary core from wfe using sev. ROM - * code puts the second core into wfe(standby). - * - */ -#define set_event() __asm__ __volatile__ ("sev" : : : "memory") - -/* Needed for secondary core boot */ -extern void omap_secondary_startup(void); - -/* - * We use Soft IRQ1 as the IPI - */ -static inline void smp_cross_call(const struct cpumask *mask) -{ - gic_raise_softirq(mask, 1); -} - -/* - * Read MPIDR: Multiprocessor affinity register - */ -#define hard_smp_processor_id() \ - ({ \ - unsigned int cpunum; \ - __asm__("mrc p15, 0, %0, c0, c0, 5" \ - : "=r" (cpunum)); \ - cpunum &= 0x0F; \ - }) - -#endif diff --git a/arch/arm/plat-omap/include/mach/sram.h b/arch/arm/plat-omap/include/mach/sram.h deleted file mode 100644 index 8974e3fc269..00000000000 --- a/arch/arm/plat-omap/include/mach/sram.h +++ /dev/null @@ -1,71 +0,0 @@ -/* - * arch/arm/plat-omap/include/mach/sram.h - * - * Interface for functions that need to be run in internal SRAM - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef __ARCH_ARM_OMAP_SRAM_H -#define __ARCH_ARM_OMAP_SRAM_H - -extern int __init omap_sram_init(void); -extern void * omap_sram_push(void * start, unsigned long size); -extern void omap_sram_reprogram_clock(u32 dpllctl, u32 ckctl); - -extern void omap2_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl, - u32 base_cs, u32 force_unlock); -extern void omap2_sram_reprogram_sdrc(u32 perf_level, u32 dll_val, - u32 mem_type); -extern u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass); - -extern u32 omap3_configure_core_dpll( - u32 m2, u32 unlock_dll, u32 f, u32 inc, - u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0, - u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0, - u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1, - u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1); - -/* Do not use these */ -extern void omap1_sram_reprogram_clock(u32 ckctl, u32 dpllctl); -extern unsigned long omap1_sram_reprogram_clock_sz; - -extern void omap24xx_sram_reprogram_clock(u32 ckctl, u32 dpllctl); -extern unsigned long omap24xx_sram_reprogram_clock_sz; - -extern void omap242x_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl, - u32 base_cs, u32 force_unlock); -extern unsigned long omap242x_sram_ddr_init_sz; - -extern u32 omap242x_sram_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, - int bypass); -extern unsigned long omap242x_sram_set_prcm_sz; - -extern void omap242x_sram_reprogram_sdrc(u32 perf_level, u32 dll_val, - u32 mem_type); -extern unsigned long omap242x_sram_reprogram_sdrc_sz; - - -extern void omap243x_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl, - u32 base_cs, u32 force_unlock); -extern unsigned long omap243x_sram_ddr_init_sz; - -extern u32 omap243x_sram_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, - int bypass); -extern unsigned long omap243x_sram_set_prcm_sz; - -extern void omap243x_sram_reprogram_sdrc(u32 perf_level, u32 dll_val, - u32 mem_type); -extern unsigned long omap243x_sram_reprogram_sdrc_sz; - -extern u32 omap3_sram_configure_core_dpll( - u32 m2, u32 unlock_dll, u32 f, u32 inc, - u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0, - u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0, - u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1, - u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1); -extern unsigned long omap3_sram_configure_core_dpll_sz; - -#endif diff --git a/arch/arm/plat-omap/include/mach/system.h b/arch/arm/plat-omap/include/mach/system.h deleted file mode 100644 index ed8ec747726..00000000000 --- a/arch/arm/plat-omap/include/mach/system.h +++ /dev/null @@ -1,51 +0,0 @@ -/* - * Copied from arch/arm/mach-sa1100/include/mach/system.h - * Copyright (c) 1999 Nicolas Pitre <nico@fluxnic.net> - */ -#ifndef __ASM_ARCH_SYSTEM_H -#define __ASM_ARCH_SYSTEM_H -#include <linux/clk.h> - -#include <asm/mach-types.h> -#include <mach/hardware.h> - -#include <mach/prcm.h> - -#ifndef CONFIG_MACH_VOICEBLUE -#define voiceblue_reset() do {} while (0) -#else -extern void voiceblue_reset(void); -#endif - -static inline void arch_idle(void) -{ - cpu_do_idle(); -} - -static inline void omap1_arch_reset(char mode) -{ - /* - * Workaround for 5912/1611b bug mentioned in sprz209d.pdf p. 28 - * "Global Software Reset Affects Traffic Controller Frequency". - */ - if (cpu_is_omap5912()) { - omap_writew(omap_readw(DPLL_CTL) & ~(1 << 4), - DPLL_CTL); - omap_writew(0x8, ARM_RSTCT1); - } - - if (machine_is_voiceblue()) - voiceblue_reset(); - else - omap_writew(1, ARM_RSTCT1); -} - -static inline void arch_reset(char mode, const char *cmd) -{ - if (!cpu_class_is_omap2()) - omap1_arch_reset(mode); - else - omap_prcm_arch_reset(mode); -} - -#endif diff --git a/arch/arm/plat-omap/include/mach/tc.h b/arch/arm/plat-omap/include/mach/tc.h deleted file mode 100644 index d2fcd789bb9..00000000000 --- a/arch/arm/plat-omap/include/mach/tc.h +++ /dev/null @@ -1,106 +0,0 @@ -/* - * arch/arm/plat-omap/include/mach/tc.h - * - * OMAP Traffic Controller - * - * Copyright (C) 2004 Nokia Corporation - * Author: Imre Deak <imre.deak@nokia.com> - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * This program is distributed in the hope that it will be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. - */ - -#ifndef __ASM_ARCH_TC_H -#define __ASM_ARCH_TC_H - -#define TCMIF_BASE 0xfffecc00 -#define OMAP_TC_OCPT1_PRIOR (TCMIF_BASE + 0x00) -#define OMAP_TC_EMIFS_PRIOR (TCMIF_BASE + 0x04) -#define OMAP_TC_EMIFF_PRIOR (TCMIF_BASE + 0x08) -#define EMIFS_CONFIG (TCMIF_BASE + 0x0c) -#define EMIFS_CS0_CONFIG (TCMIF_BASE + 0x10) -#define EMIFS_CS1_CONFIG (TCMIF_BASE + 0x14) -#define EMIFS_CS2_CONFIG (TCMIF_BASE + 0x18) -#define EMIFS_CS3_CONFIG (TCMIF_BASE + 0x1c) -#define EMIFF_SDRAM_CONFIG (TCMIF_BASE + 0x20) -#define EMIFF_MRS (TCMIF_BASE + 0x24) -#define TC_TIMEOUT1 (TCMIF_BASE + 0x28) -#define TC_TIMEOUT2 (TCMIF_BASE + 0x2c) -#define TC_TIMEOUT3 (TCMIF_BASE + 0x30) -#define TC_ENDIANISM (TCMIF_BASE + 0x34) -#define EMIFF_SDRAM_CONFIG_2 (TCMIF_BASE + 0x3c) -#define EMIF_CFG_DYNAMIC_WS (TCMIF_BASE + 0x40) -#define EMIFS_ACS0 (TCMIF_BASE + 0x50) -#define EMIFS_ACS1 (TCMIF_BASE + 0x54) -#define EMIFS_ACS2 (TCMIF_BASE + 0x58) -#define EMIFS_ACS3 (TCMIF_BASE + 0x5c) -#define OMAP_TC_OCPT2_PRIOR (TCMIF_BASE + 0xd0) - -/* external EMIFS chipselect regions */ -#define OMAP_CS0_PHYS 0x00000000 -#define OMAP_CS0_SIZE SZ_64M - -#define OMAP_CS1_PHYS 0x04000000 -#define OMAP_CS1_SIZE SZ_64M - -#define OMAP_CS1A_PHYS OMAP_CS1_PHYS -#define OMAP_CS1A_SIZE SZ_32M - -#define OMAP_CS1B_PHYS (OMAP_CS1A_PHYS + OMAP_CS1A_SIZE) -#define OMAP_CS1B_SIZE SZ_32M - -#define OMAP_CS2_PHYS 0x08000000 -#define OMAP_CS2_SIZE SZ_64M - -#define OMAP_CS2A_PHYS OMAP_CS2_PHYS -#define OMAP_CS2A_SIZE SZ_32M - -#define OMAP_CS2B_PHYS (OMAP_CS2A_PHYS + OMAP_CS2A_SIZE) -#define OMAP_CS2B_SIZE SZ_32M - -#define OMAP_CS3_PHYS 0x0c000000 -#define OMAP_CS3_SIZE SZ_64M - -#ifndef __ASSEMBLER__ - -/* EMIF Slow Interface Configuration Register */ -#define OMAP_EMIFS_CONFIG_FR (1 << 4) -#define OMAP_EMIFS_CONFIG_PDE (1 << 3) -#define OMAP_EMIFS_CONFIG_PWD_EN (1 << 2) -#define OMAP_EMIFS_CONFIG_BM (1 << 1) -#define OMAP_EMIFS_CONFIG_WP (1 << 0) - -#define EMIFS_CCS(n) (EMIFS_CS0_CONFIG + (4 * (n))) -#define EMIFS_ACS(n) (EMIFS_ACS0 + (4 * (n))) - -/* Almost all documentation for chip and board memory maps assumes - * BM is clear. Most devel boards have a switch to control booting - * from NOR flash (using external chipselect 3) rather than mask ROM, - * which uses BM to interchange the physical CS0 and CS3 addresses. - */ -static inline u32 omap_cs0_phys(void) -{ - return (omap_readl(EMIFS_CONFIG) & OMAP_EMIFS_CONFIG_BM) - ? OMAP_CS3_PHYS : 0; -} - -static inline u32 omap_cs3_phys(void) -{ - return (omap_readl(EMIFS_CONFIG) & OMAP_EMIFS_CONFIG_BM) - ? 0 : OMAP_CS3_PHYS; -} - -#endif /* __ASSEMBLER__ */ - -#endif /* __ASM_ARCH_TC_H */ diff --git a/arch/arm/plat-omap/include/mach/timer-gp.h b/arch/arm/plat-omap/include/mach/timer-gp.h deleted file mode 100644 index c88d346b59d..00000000000 --- a/arch/arm/plat-omap/include/mach/timer-gp.h +++ /dev/null @@ -1,17 +0,0 @@ -/* - * OMAP2/3 GPTIMER support.headers - * - * Copyright (C) 2009 Nokia Corporation - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - */ - -#ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_TIMER_GP_H -#define __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_TIMER_GP_H - -int __init omap2_gp_clockevent_set_gptimer(u8 id); - -#endif - diff --git a/arch/arm/plat-omap/include/mach/timex.h b/arch/arm/plat-omap/include/mach/timex.h deleted file mode 100644 index 6d35767bc48..00000000000 --- a/arch/arm/plat-omap/include/mach/timex.h +++ /dev/null @@ -1,41 +0,0 @@ -/* - * arch/arm/plat-omap/include/mach/timex.h - * - * Copyright (C) 2000 RidgeRun, Inc. - * Author: Greg Lonnon <glonnon@ridgerun.com> - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -#if !defined(__ASM_ARCH_OMAP_TIMEX_H) -#define __ASM_ARCH_OMAP_TIMEX_H - -/* - * OMAP 32KHz timer updates time one jiffie at a time from a secondary timer, - * and that's why the CLOCK_TICK_RATE is not 32768. - */ -#ifdef CONFIG_OMAP_32K_TIMER -#define CLOCK_TICK_RATE (CONFIG_OMAP_32K_TIMER_HZ) -#else -#define CLOCK_TICK_RATE (HZ * 100000UL) -#endif - -#endif /* __ASM_ARCH_OMAP_TIMEX_H */ diff --git a/arch/arm/plat-omap/include/mach/uncompress.h b/arch/arm/plat-omap/include/mach/uncompress.h deleted file mode 100644 index 0814c5f210c..00000000000 --- a/arch/arm/plat-omap/include/mach/uncompress.h +++ /dev/null @@ -1,83 +0,0 @@ -/* - * arch/arm/plat-omap/include/mach/uncompress.h - * - * Serial port stubs for kernel decompress status messages - * - * Initially based on: - * linux-2.4.15-rmk1-dsplinux1.6/arch/arm/plat-omap/include/mach1510/uncompress.h - * Copyright (C) 2000 RidgeRun, Inc. - * Author: Greg Lonnon <glonnon@ridgerun.com> - * - * Rewritten by: - * Author: <source@mvista.com> - * 2004 (c) MontaVista Software, Inc. - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. - */ - -#include <linux/types.h> -#include <linux/serial_reg.h> -#include <mach/serial.h> - -unsigned int system_rev; - -#define UART_OMAP_MDR1 0x08 /* mode definition register */ -#define OMAP_ID_730 0x355F -#define ID_MASK 0x7fff -#define check_port(base, shift) ((base[UART_OMAP_MDR1 << shift] & 7) == 0) -#define omap_get_id() ((*(volatile unsigned int *)(0xfffed404)) >> 12) & ID_MASK - -static void putc(int c) -{ - volatile u8 * uart = 0; - int shift = 2; - -#ifdef CONFIG_MACH_OMAP_PALMTE - return; -#endif - -#ifdef CONFIG_ARCH_OMAP -#ifdef CONFIG_OMAP_LL_DEBUG_UART3 - uart = (volatile u8 *)(OMAP_UART3_BASE); -#elif defined(CONFIG_OMAP_LL_DEBUG_UART2) - uart = (volatile u8 *)(OMAP_UART2_BASE); -#else - uart = (volatile u8 *)(OMAP_UART1_BASE); -#endif - -#ifdef CONFIG_ARCH_OMAP1 - /* Determine which serial port to use */ - do { - /* MMU is not on, so cpu_is_omapXXXX() won't work here */ - unsigned int omap_id = omap_get_id(); - - if (omap_id == OMAP_ID_730) - shift = 0; - - if (check_port(uart, shift)) - break; - /* Silent boot if no serial ports are enabled. */ - return; - } while (0); -#endif /* CONFIG_ARCH_OMAP1 */ -#endif - - /* - * Now, xmit each character - */ - while (!(uart[UART_LSR << shift] & UART_LSR_THRE)) - barrier(); - uart[UART_TX << shift] = c; -} - -static inline void flush(void) -{ -} - -/* - * nothing to do - */ -#define arch_decomp_setup() -#define arch_decomp_wdog() diff --git a/arch/arm/plat-omap/include/mach/usb.h b/arch/arm/plat-omap/include/mach/usb.h deleted file mode 100644 index f337e1761e2..00000000000 --- a/arch/arm/plat-omap/include/mach/usb.h +++ /dev/null @@ -1,145 +0,0 @@ -// include/asm-arm/mach-omap/usb.h - -#ifndef __ASM_ARCH_OMAP_USB_H -#define __ASM_ARCH_OMAP_USB_H - -#include <mach/board.h> - -/*-------------------------------------------------------------------------*/ - -#define OMAP1_OTG_BASE 0xfffb0400 -#define OMAP1_UDC_BASE 0xfffb4000 -#define OMAP1_OHCI_BASE 0xfffba000 - -#define OMAP2_OHCI_BASE 0x4805e000 -#define OMAP2_UDC_BASE 0x4805e200 -#define OMAP2_OTG_BASE 0x4805e300 - -#ifdef CONFIG_ARCH_OMAP1 - -#define OTG_BASE OMAP1_OTG_BASE -#define UDC_BASE OMAP1_UDC_BASE -#define OMAP_OHCI_BASE OMAP1_OHCI_BASE - -#else - -#define OTG_BASE OMAP2_OTG_BASE -#define UDC_BASE OMAP2_UDC_BASE -#define OMAP_OHCI_BASE OMAP2_OHCI_BASE - -extern void usb_musb_init(void); - -#endif - -void omap_usb_init(struct omap_usb_config *pdata); - -/*-------------------------------------------------------------------------*/ - -/* - * OTG and transceiver registers, for OMAPs starting with ARM926 - */ -#define OTG_REV (OTG_BASE + 0x00) -#define OTG_SYSCON_1 (OTG_BASE + 0x04) -# define USB2_TRX_MODE(w) (((w)>>24)&0x07) -# define USB1_TRX_MODE(w) (((w)>>20)&0x07) -# define USB0_TRX_MODE(w) (((w)>>16)&0x07) -# define OTG_IDLE_EN (1 << 15) -# define HST_IDLE_EN (1 << 14) -# define DEV_IDLE_EN (1 << 13) -# define OTG_RESET_DONE (1 << 2) -# define OTG_SOFT_RESET (1 << 1) -#define OTG_SYSCON_2 (OTG_BASE + 0x08) -# define OTG_EN (1 << 31) -# define USBX_SYNCHRO (1 << 30) -# define OTG_MST16 (1 << 29) -# define SRP_GPDATA (1 << 28) -# define SRP_GPDVBUS (1 << 27) -# define SRP_GPUVBUS(w) (((w)>>24)&0x07) -# define A_WAIT_VRISE(w) (((w)>>20)&0x07) -# define B_ASE_BRST(w) (((w)>>16)&0x07) -# define SRP_DPW (1 << 14) -# define SRP_DATA (1 << 13) -# define SRP_VBUS (1 << 12) -# define OTG_PADEN (1 << 10) -# define HMC_PADEN (1 << 9) -# define UHOST_EN (1 << 8) -# define HMC_TLLSPEED (1 << 7) -# define HMC_TLLATTACH (1 << 6) -# define OTG_HMC(w) (((w)>>0)&0x3f) -#define OTG_CTRL (OTG_BASE + 0x0c) -# define OTG_USB2_EN (1 << 29) -# define OTG_USB2_DP (1 << 28) -# define OTG_USB2_DM (1 << 27) -# define OTG_USB1_EN (1 << 26) -# define OTG_USB1_DP (1 << 25) -# define OTG_USB1_DM (1 << 24) -# define OTG_USB0_EN (1 << 23) -# define OTG_USB0_DP (1 << 22) -# define OTG_USB0_DM (1 << 21) -# define OTG_ASESSVLD (1 << 20) -# define OTG_BSESSEND (1 << 19) -# define OTG_BSESSVLD (1 << 18) -# define OTG_VBUSVLD (1 << 17) -# define OTG_ID (1 << 16) -# define OTG_DRIVER_SEL (1 << 15) -# define OTG_A_SETB_HNPEN (1 << 12) -# define OTG_A_BUSREQ (1 << 11) -# define OTG_B_HNPEN (1 << 9) -# define OTG_B_BUSREQ (1 << 8) -# define OTG_BUSDROP (1 << 7) -# define OTG_PULLDOWN (1 << 5) -# define OTG_PULLUP (1 << 4) -# define OTG_DRV_VBUS (1 << 3) -# define OTG_PD_VBUS (1 << 2) -# define OTG_PU_VBUS (1 << 1) -# define OTG_PU_ID (1 << 0) -#define OTG_IRQ_EN (OTG_BASE + 0x10) /* 16-bit */ -# define DRIVER_SWITCH (1 << 15) -# define A_VBUS_ERR (1 << 13) -# define A_REQ_TMROUT (1 << 12) -# define A_SRP_DETECT (1 << 11) -# define B_HNP_FAIL (1 << 10) -# define B_SRP_TMROUT (1 << 9) -# define B_SRP_DONE (1 << 8) -# define B_SRP_STARTED (1 << 7) -# define OPRT_CHG (1 << 0) -#define OTG_IRQ_SRC (OTG_BASE + 0x14) /* 16-bit */ - // same bits as in IRQ_EN -#define OTG_OUTCTRL (OTG_BASE + 0x18) /* 16-bit */ -# define OTGVPD (1 << 14) -# define OTGVPU (1 << 13) -# define OTGPUID (1 << 12) -# define USB2VDR (1 << 10) -# define USB2PDEN (1 << 9) -# define USB2PUEN (1 << 8) -# define USB1VDR (1 << 6) -# define USB1PDEN (1 << 5) -# define USB1PUEN (1 << 4) -# define USB0VDR (1 << 2) -# define USB0PDEN (1 << 1) -# define USB0PUEN (1 << 0) -#define OTG_TEST (OTG_BASE + 0x20) /* 16-bit */ -#define OTG_VENDOR_CODE (OTG_BASE + 0xfc) /* 16-bit */ - -/*-------------------------------------------------------------------------*/ - -/* OMAP1 */ -#define USB_TRANSCEIVER_CTRL (0xfffe1000 + 0x0064) -# define CONF_USB2_UNI_R (1 << 8) -# define CONF_USB1_UNI_R (1 << 7) -# define CONF_USB_PORT0_R(x) (((x)>>4)&0x7) -# define CONF_USB0_ISOLATE_R (1 << 3) -# define CONF_USB_PWRDN_DM_R (1 << 2) -# define CONF_USB_PWRDN_DP_R (1 << 1) - -/* OMAP2 */ -# define USB_UNIDIR 0x0 -# define USB_UNIDIR_TLL 0x1 -# define USB_BIDIR 0x2 -# define USB_BIDIR_TLL 0x3 -# define USBTXWRMODEI(port, x) ((x) << (22 - (port * 2))) -# define USBT2TLL5PI (1 << 17) -# define USB0PUENACTLOI (1 << 16) -# define USBSTANDBYCTRL (1 << 15) - -#endif /* __ASM_ARCH_OMAP_USB_H */ diff --git a/arch/arm/plat-omap/include/mach/vmalloc.h b/arch/arm/plat-omap/include/mach/vmalloc.h deleted file mode 100644 index b97dfafeebd..00000000000 --- a/arch/arm/plat-omap/include/mach/vmalloc.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * arch/arm/plat-omap/include/mach/vmalloc.h - * - * Copyright (C) 2000 Russell King. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define VMALLOC_END (PAGE_OFFSET + 0x18000000) - |