diff options
-rw-r--r-- | drivers/gpu/drm/nouveau/Makefile | 4 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/core/engine/disp/nv50.c | 316 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/core/engine/disp/nv50.h | 36 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/core/engine/disp/nv84.c | 81 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/core/engine/disp/nv94.c | 81 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/core/engine/disp/nva0.c | 81 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/core/engine/disp/nva3.c | 81 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/core/include/engine/disp.h | 4 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/core/subdev/device/nv50.c | 26 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/core/subdev/device/nvc0.c | 14 |
10 files changed, 699 insertions, 25 deletions
diff --git a/drivers/gpu/drm/nouveau/Makefile b/drivers/gpu/drm/nouveau/Makefile index b629abf2c28..94ab4bc9d44 100644 --- a/drivers/gpu/drm/nouveau/Makefile +++ b/drivers/gpu/drm/nouveau/Makefile @@ -130,6 +130,10 @@ nouveau-y += core/engine/crypt/nv84.o nouveau-y += core/engine/crypt/nv98.o nouveau-y += core/engine/disp/nv04.o nouveau-y += core/engine/disp/nv50.o +nouveau-y += core/engine/disp/nv84.o +nouveau-y += core/engine/disp/nv94.o +nouveau-y += core/engine/disp/nva0.o +nouveau-y += core/engine/disp/nva3.o nouveau-y += core/engine/disp/nvd0.o nouveau-y += core/engine/disp/vga.o nouveau-y += core/engine/fifo/base.o diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/nv50.c b/drivers/gpu/drm/nouveau/core/engine/disp/nv50.c index 16a9afb1060..b3ad1d09ede 100644 --- a/drivers/gpu/drm/nouveau/core/engine/disp/nv50.c +++ b/drivers/gpu/drm/nouveau/core/engine/disp/nv50.c @@ -25,15 +25,316 @@ #include <engine/software.h> #include <engine/disp.h> -struct nv50_disp_priv { - struct nouveau_disp base; +#include "nv50.h" + +/******************************************************************************* + * EVO channel common helpers + ******************************************************************************/ + +static u32 +nv50_disp_chan_rd32(struct nouveau_object *object, u64 addr) +{ + return 0xdeadcafe; +} + +static void +nv50_disp_chan_wr32(struct nouveau_object *object, u64 addr, u32 data) +{ +} + +/******************************************************************************* + * EVO master channel object + ******************************************************************************/ + +static int +nv50_disp_mast_ctor(struct nouveau_object *parent, + struct nouveau_object *engine, + struct nouveau_oclass *oclass, void *data, u32 size, + struct nouveau_object **pobject) +{ + struct nv50_disp_chan *chan; + int ret; + + ret = nouveau_object_create(parent, engine, oclass, 0, &chan); + *pobject = nv_object(chan); + if (ret) + return ret; + + return 0; +} + +static void +nv50_disp_mast_dtor(struct nouveau_object *object) +{ + struct nv50_disp_chan *chan = (void *)object; + nouveau_object_destroy(&chan->base); +} + +static int +nv50_disp_mast_init(struct nouveau_object *object) +{ + struct nv50_disp_chan *chan = (void *)object; + int ret; + + ret = nouveau_object_init(&chan->base); + if (ret) + return ret; + + return 0; +} + +static int +nv50_disp_mast_fini(struct nouveau_object *object, bool suspend) +{ + struct nv50_disp_chan *chan = (void *)object; + return nouveau_object_fini(&chan->base, suspend); +} + +struct nouveau_ofuncs +nv50_disp_mast_ofuncs = { + .ctor = nv50_disp_mast_ctor, + .dtor = nv50_disp_mast_dtor, + .init = nv50_disp_mast_init, + .fini = nv50_disp_mast_fini, + .rd32 = nv50_disp_chan_rd32, + .wr32 = nv50_disp_chan_wr32, +}; + +/******************************************************************************* + * EVO DMA channel objects (sync, overlay) + ******************************************************************************/ + +static int +nv50_disp_dmac_ctor(struct nouveau_object *parent, + struct nouveau_object *engine, + struct nouveau_oclass *oclass, void *data, u32 size, + struct nouveau_object **pobject) +{ + struct nv50_disp_chan *chan; + int ret; + + ret = nouveau_object_create(parent, engine, oclass, 0, &chan); + *pobject = nv_object(chan); + if (ret) + return ret; + + return 0; +} + +static void +nv50_disp_dmac_dtor(struct nouveau_object *object) +{ + struct nv50_disp_chan *chan = (void *)object; + nouveau_object_destroy(&chan->base); +} + +static int +nv50_disp_dmac_init(struct nouveau_object *object) +{ + struct nv50_disp_chan *chan = (void *)object; + int ret; + + ret = nouveau_object_init(&chan->base); + if (ret) + return ret; + + return 0; +} + +static int +nv50_disp_dmac_fini(struct nouveau_object *object, bool suspend) +{ + struct nv50_disp_chan *chan = (void *)object; + return nouveau_object_fini(&chan->base, suspend); +} + +struct nouveau_ofuncs +nv50_disp_dmac_ofuncs = { + .ctor = nv50_disp_dmac_ctor, + .dtor = nv50_disp_dmac_dtor, + .init = nv50_disp_dmac_init, + .fini = nv50_disp_dmac_fini, + .rd32 = nv50_disp_chan_rd32, + .wr32 = nv50_disp_chan_wr32, +}; + +/******************************************************************************* + * EVO PIO channel objects (cursor, immediate overlay controls) + ******************************************************************************/ + +static int +nv50_disp_pioc_ctor(struct nouveau_object *parent, + struct nouveau_object *engine, + struct nouveau_oclass *oclass, void *data, u32 size, + struct nouveau_object **pobject) +{ + struct nv50_disp_chan *chan; + int ret; + + ret = nouveau_object_create(parent, engine, oclass, 0, &chan); + *pobject = nv_object(chan); + if (ret) + return ret; + + return 0; +} + +static void +nv50_disp_pioc_dtor(struct nouveau_object *object) +{ + struct nv50_disp_chan *chan = (void *)object; + nouveau_object_destroy(&chan->base); +} + +static int +nv50_disp_pioc_init(struct nouveau_object *object) +{ + struct nv50_disp_chan *chan = (void *)object; + int ret; + + ret = nouveau_object_init(&chan->base); + if (ret) + return ret; + + return 0; +} + +static int +nv50_disp_pioc_fini(struct nouveau_object *object, bool suspend) +{ + struct nv50_disp_chan *chan = (void *)object; + return nouveau_object_fini(&chan->base, suspend); +} + +struct nouveau_ofuncs +nv50_disp_pioc_ofuncs = { + .ctor = nv50_disp_pioc_ctor, + .dtor = nv50_disp_pioc_dtor, + .init = nv50_disp_pioc_init, + .fini = nv50_disp_pioc_fini, + .rd32 = nv50_disp_chan_rd32, + .wr32 = nv50_disp_chan_wr32, +}; + +/******************************************************************************* + * Base display object + ******************************************************************************/ + +static int +nv50_disp_base_ctor(struct nouveau_object *parent, + struct nouveau_object *engine, + struct nouveau_oclass *oclass, void *data, u32 size, + struct nouveau_object **pobject) +{ + struct nv50_disp_priv *priv = (void *)engine; + struct nv50_disp_base *base; + int ret; + + ret = nouveau_parent_create(parent, engine, oclass, 0, + priv->sclass, 0, &base); + *pobject = nv_object(base); + if (ret) + return ret; + + return 0; +} + +static void +nv50_disp_base_dtor(struct nouveau_object *object) +{ + struct nv50_disp_base *base = (void *)object; + nouveau_parent_destroy(&base->base); +} + +static int +nv50_disp_base_init(struct nouveau_object *object) +{ + struct nv50_disp_base *base = (void *)object; + int ret; + + ret = nouveau_parent_init(&base->base); + if (ret) + return ret; + + /* caps */ + /* intr 100 */ + /* 6194e8 shit */ + /* intr */ + /* set 610010 from engctx */ + /* acquire mast? */ + return 0; +} + +static int +nv50_disp_base_fini(struct nouveau_object *object, bool suspend) +{ + struct nv50_disp_base *base = (void *)object; + return nouveau_parent_fini(&base->base, suspend); +} + +struct nouveau_ofuncs +nv50_disp_base_ofuncs = { + .ctor = nv50_disp_base_ctor, + .dtor = nv50_disp_base_dtor, + .init = nv50_disp_base_init, + .fini = nv50_disp_base_fini, +}; + +static struct nouveau_oclass +nv50_disp_base_oclass[] = { + { 0x5070, &nv50_disp_base_ofuncs }, }; static struct nouveau_oclass nv50_disp_sclass[] = { - {}, + { 0x507d, &nv50_disp_mast_ofuncs }, /* master */ + { 0x507c, &nv50_disp_dmac_ofuncs }, /* sync */ + { 0x507e, &nv50_disp_dmac_ofuncs }, /* overlay */ + { 0x507b, &nv50_disp_pioc_ofuncs }, /* overlay (pio) */ + { 0x507a, &nv50_disp_pioc_ofuncs }, /* cursor (pio) */ + {} }; +/******************************************************************************* + * Display context, tracks instmem allocation and prevents more than one + * client using the display hardware at any time. + ******************************************************************************/ + +static int +nv50_disp_data_ctor(struct nouveau_object *parent, + struct nouveau_object *engine, + struct nouveau_oclass *oclass, void *data, u32 size, + struct nouveau_object **pobject) +{ + struct nouveau_engctx *ectx; + int ret; + + ret = nouveau_engctx_create(parent, engine, oclass, NULL, 0x10000, + 0x10000, NVOBJ_FLAG_ZERO_ALLOC, &ectx); + *pobject = nv_object(ectx); + if (ret) + return ret; + + return 0; +} + +struct nouveau_oclass +nv50_disp_cclass = { + .handle = NV_ENGCTX(DISP, 0x50), + .ofuncs = &(struct nouveau_ofuncs) { + .ctor = nv50_disp_data_ctor, + .dtor = _nouveau_engctx_dtor, + .init = _nouveau_engctx_init, + .fini = _nouveau_engctx_fini, + .rd32 = _nouveau_engctx_rd32, + .wr32 = _nouveau_engctx_wr32, + }, +}; + +/******************************************************************************* + * Display engine implementation + ******************************************************************************/ + static void nv50_disp_intr_vblank(struct nv50_disp_priv *priv, int crtc) { @@ -71,7 +372,7 @@ nv50_disp_intr_vblank(struct nv50_disp_priv *priv, int crtc) disp->vblank.notify(disp->vblank.data, crtc); } -static void +void nv50_disp_intr(struct nouveau_subdev *subdev) { struct nv50_disp_priv *priv = (void *)subdev; @@ -105,8 +406,13 @@ nv50_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine, if (ret) return ret; - nv_engine(priv)->sclass = nv50_disp_sclass; + nv_engine(priv)->sclass = nv50_disp_base_oclass; + nv_engine(priv)->cclass = &nv50_disp_cclass; nv_subdev(priv)->intr = nv50_disp_intr; + priv->sclass = nv50_disp_sclass; + priv->head.nr = 2; + priv->dac.nr = 3; + priv->sor.nr = 2; INIT_LIST_HEAD(&priv->base.vblank.list); spin_lock_init(&priv->base.vblank.lock); diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/nv50.h b/drivers/gpu/drm/nouveau/core/engine/disp/nv50.h new file mode 100644 index 00000000000..06753f623f2 --- /dev/null +++ b/drivers/gpu/drm/nouveau/core/engine/disp/nv50.h @@ -0,0 +1,36 @@ +#ifndef __NV50_DISP_H__ +#define __NV50_DISP_H__ + +#include <core/parent.h> +#include <engine/disp.h> + +struct nv50_disp_priv { + struct nouveau_disp base; + struct nouveau_oclass *sclass; + struct { + int nr; + } head; + struct { + int nr; + } dac; + struct { + int nr; + } sor; +}; + +struct nv50_disp_base { + struct nouveau_parent base; +}; + +struct nv50_disp_chan { + struct nouveau_object base; +}; + +extern struct nouveau_ofuncs nv50_disp_mast_ofuncs; +extern struct nouveau_ofuncs nv50_disp_dmac_ofuncs; +extern struct nouveau_ofuncs nv50_disp_pioc_ofuncs; +extern struct nouveau_ofuncs nv50_disp_base_ofuncs; +extern struct nouveau_oclass nv50_disp_cclass; +void nv50_disp_intr(struct nouveau_subdev *); + +#endif diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/nv84.c b/drivers/gpu/drm/nouveau/core/engine/disp/nv84.c new file mode 100644 index 00000000000..b262b167062 --- /dev/null +++ b/drivers/gpu/drm/nouveau/core/engine/disp/nv84.c @@ -0,0 +1,81 @@ +/* + * Copyright 2012 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs + */ + +#include <engine/software.h> +#include <engine/disp.h> + +#include "nv50.h" + +static struct nouveau_oclass +nv84_disp_sclass[] = { + { 0x827d, &nv50_disp_mast_ofuncs }, /* master */ + { 0x827c, &nv50_disp_dmac_ofuncs }, /* sync */ + { 0x827e, &nv50_disp_dmac_ofuncs }, /* overlay */ + { 0x827b, &nv50_disp_pioc_ofuncs }, /* overlay (pio) */ + { 0x827a, &nv50_disp_pioc_ofuncs }, /* cursor (pio) */ + {} +}; + +static struct nouveau_oclass +nv84_disp_base_oclass[] = { + { 0x8270, &nv50_disp_base_ofuncs }, +}; + +static int +nv84_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine, + struct nouveau_oclass *oclass, void *data, u32 size, + struct nouveau_object **pobject) +{ + struct nv50_disp_priv *priv; + int ret; + + ret = nouveau_disp_create(parent, engine, oclass, "PDISP", + "display", &priv); + *pobject = nv_object(priv); + if (ret) + return ret; + + nv_engine(priv)->sclass = nv84_disp_base_oclass; + nv_engine(priv)->cclass = &nv50_disp_cclass; + nv_subdev(priv)->intr = nv50_disp_intr; + priv->sclass = nv84_disp_sclass; + priv->head.nr = 2; + priv->dac.nr = 3; + priv->sor.nr = 2; + + INIT_LIST_HEAD(&priv->base.vblank.list); + spin_lock_init(&priv->base.vblank.lock); + return 0; +} + +struct nouveau_oclass +nv84_disp_oclass = { + .handle = NV_ENGINE(DISP, 0x82), + .ofuncs = &(struct nouveau_ofuncs) { + .ctor = nv84_disp_ctor, + .dtor = _nouveau_disp_dtor, + .init = _nouveau_disp_init, + .fini = _nouveau_disp_fini, + }, +}; diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/nv94.c b/drivers/gpu/drm/nouveau/core/engine/disp/nv94.c new file mode 100644 index 00000000000..9d75f060bf0 --- /dev/null +++ b/drivers/gpu/drm/nouveau/core/engine/disp/nv94.c @@ -0,0 +1,81 @@ +/* + * Copyright 2012 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs + */ + +#include <engine/software.h> +#include <engine/disp.h> + +#include "nv50.h" + +static struct nouveau_oclass +nv94_disp_sclass[] = { + { 0x887d, &nv50_disp_mast_ofuncs }, /* master */ + { 0x887c, &nv50_disp_dmac_ofuncs }, /* sync */ + { 0x887e, &nv50_disp_dmac_ofuncs }, /* overlay */ + { 0x887b, &nv50_disp_pioc_ofuncs }, /* overlay (pio) */ + { 0x887a, &nv50_disp_pioc_ofuncs }, /* cursor (pio) */ + {} +}; + +static struct nouveau_oclass +nv94_disp_base_oclass[] = { + { 0x8870, &nv50_disp_base_ofuncs }, +}; + +static int +nv94_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine, + struct nouveau_oclass *oclass, void *data, u32 size, + struct nouveau_object **pobject) +{ + struct nv50_disp_priv *priv; + int ret; + + ret = nouveau_disp_create(parent, engine, oclass, "PDISP", + "display", &priv); + *pobject = nv_object(priv); + if (ret) + return ret; + + nv_engine(priv)->sclass = nv94_disp_base_oclass; + nv_engine(priv)->cclass = &nv50_disp_cclass; + nv_subdev(priv)->intr = nv50_disp_intr; + priv->sclass = nv94_disp_sclass; + priv->head.nr = 2; + priv->dac.nr = 3; + priv->sor.nr = 4; + + INIT_LIST_HEAD(&priv->base.vblank.list); + spin_lock_init(&priv->base.vblank.lock); + return 0; +} + +struct nouveau_oclass +nv94_disp_oclass = { + .handle = NV_ENGINE(DISP, 0x88), + .ofuncs = &(struct nouveau_ofuncs) { + .ctor = nv94_disp_ctor, + .dtor = _nouveau_disp_dtor, + .init = _nouveau_disp_init, + .fini = _nouveau_disp_fini, + }, +}; diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/nva0.c b/drivers/gpu/drm/nouveau/core/engine/disp/nva0.c new file mode 100644 index 00000000000..4fd0e39f59e --- /dev/null +++ b/drivers/gpu/drm/nouveau/core/engine/disp/nva0.c @@ -0,0 +1,81 @@ +/* + * Copyright 2012 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs + */ + +#include <engine/software.h> +#include <engine/disp.h> + +#include "nv50.h" + +static struct nouveau_oclass +nva0_disp_sclass[] = { + { 0x837d, &nv50_disp_mast_ofuncs }, /* master */ + { 0x837c, &nv50_disp_dmac_ofuncs }, /* sync */ + { 0x837e, &nv50_disp_dmac_ofuncs }, /* overlay */ + { 0x837b, &nv50_disp_pioc_ofuncs }, /* overlay (pio) */ + { 0x837a, &nv50_disp_pioc_ofuncs }, /* cursor (pio) */ + {} +}; + +static struct nouveau_oclass +nva0_disp_base_oclass[] = { + { 0x8370, &nv50_disp_base_ofuncs }, +}; + +static int +nva0_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine, + struct nouveau_oclass *oclass, void *data, u32 size, + struct nouveau_object **pobject) +{ + struct nv50_disp_priv *priv; + int ret; + + ret = nouveau_disp_create(parent, engine, oclass, "PDISP", + "display", &priv); + *pobject = nv_object(priv); + if (ret) + return ret; + + nv_engine(priv)->sclass = nva0_disp_base_oclass; + nv_engine(priv)->cclass = &nv50_disp_cclass; + nv_subdev(priv)->intr = nv50_disp_intr; + priv->sclass = nva0_disp_sclass; + priv->head.nr = 2; + priv->dac.nr = 3; + priv->sor.nr = 2; + + INIT_LIST_HEAD(&priv->base.vblank.list); + spin_lock_init(&priv->base.vblank.lock); + return 0; +} + +struct nouveau_oclass +nva0_disp_oclass = { + .handle = NV_ENGINE(DISP, 0x83), + .ofuncs = &(struct nouveau_ofuncs) { + .ctor = nva0_disp_ctor, + .dtor = _nouveau_disp_dtor, + .init = _nouveau_disp_init, + .fini = _nouveau_disp_fini, + }, +}; diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/nva3.c b/drivers/gpu/drm/nouveau/core/engine/disp/nva3.c new file mode 100644 index 00000000000..e8da5e06960 --- /dev/null +++ b/drivers/gpu/drm/nouveau/core/engine/disp/nva3.c @@ -0,0 +1,81 @@ +/* + * Copyright 2012 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs + */ + +#include <engine/software.h> +#include <engine/disp.h> + +#include "nv50.h" + +static struct nouveau_oclass +nva3_disp_sclass[] = { + { 0x857d, &nv50_disp_mast_ofuncs }, /* master */ + { 0x857c, &nv50_disp_dmac_ofuncs }, /* sync */ + { 0x857e, &nv50_disp_dmac_ofuncs }, /* overlay */ + { 0x857b, &nv50_disp_pioc_ofuncs }, /* overlay (pio) */ + { 0x857a, &nv50_disp_pioc_ofuncs }, /* cursor (pio) */ + {} +}; + +static struct nouveau_oclass +nva3_disp_base_oclass[] = { + { 0x8570, &nv50_disp_base_ofuncs }, +}; + +static int +nva3_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine, + struct nouveau_oclass *oclass, void *data, u32 size, + struct nouveau_object **pobject) +{ + struct nv50_disp_priv *priv; + int ret; + + ret = nouveau_disp_create(parent, engine, oclass, "PDISP", + "display", &priv); + *pobject = nv_object(priv); + if (ret) + return ret; + + nv_engine(priv)->sclass = nva3_disp_base_oclass; + nv_engine(priv)->cclass = &nv50_disp_cclass; + nv_subdev(priv)->intr = nv50_disp_intr; + priv->sclass = nva3_disp_sclass; + priv->head.nr = 2; + priv->dac.nr = 3; + priv->sor.nr = 4; + + INIT_LIST_HEAD(&priv->base.vblank.list); + spin_lock_init(&priv->base.vblank.lock); + return 0; +} + +struct nouveau_oclass +nva3_disp_oclass = { + .handle = NV_ENGINE(DISP, 0x85), + .ofuncs = &(struct nouveau_ofuncs) { + .ctor = nva3_disp_ctor, + .dtor = _nouveau_disp_dtor, + .init = _nouveau_disp_init, + .fini = _nouveau_disp_fini, + }, +}; diff --git a/drivers/gpu/drm/nouveau/core/include/engine/disp.h b/drivers/gpu/drm/nouveau/core/include/engine/disp.h index 38ec1252cba..83cdfe190af 100644 --- a/drivers/gpu/drm/nouveau/core/include/engine/disp.h +++ b/drivers/gpu/drm/nouveau/core/include/engine/disp.h @@ -39,6 +39,10 @@ nouveau_disp(void *obj) extern struct nouveau_oclass nv04_disp_oclass; extern struct nouveau_oclass nv50_disp_oclass; +extern struct nouveau_oclass nv84_disp_oclass; +extern struct nouveau_oclass nva0_disp_oclass; +extern struct nouveau_oclass nv94_disp_oclass; +extern struct nouveau_oclass nva3_disp_oclass; extern struct nouveau_oclass nvd0_disp_oclass; #endif diff --git a/drivers/gpu/drm/nouveau/core/subdev/device/nv50.c b/drivers/gpu/drm/nouveau/core/subdev/device/nv50.c index fec3bcc9a6f..6ccfd8585ba 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/device/nv50.c +++ b/drivers/gpu/drm/nouveau/core/subdev/device/nv50.c @@ -98,7 +98,7 @@ nv50_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass; device->oclass[NVDEV_ENGINE_CRYPT ] = &nv84_crypt_oclass; device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass; - device->oclass[NVDEV_ENGINE_DISP ] = &nv50_disp_oclass; + device->oclass[NVDEV_ENGINE_DISP ] = &nv84_disp_oclass; break; case 0x86: device->cname = "G86"; @@ -123,7 +123,7 @@ nv50_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass; device->oclass[NVDEV_ENGINE_CRYPT ] = &nv84_crypt_oclass; device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass; - device->oclass[NVDEV_ENGINE_DISP ] = &nv50_disp_oclass; + device->oclass[NVDEV_ENGINE_DISP ] = &nv84_disp_oclass; break; case 0x92: device->cname = "G92"; @@ -148,7 +148,7 @@ nv50_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass; device->oclass[NVDEV_ENGINE_CRYPT ] = &nv84_crypt_oclass; device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass; - device->oclass[NVDEV_ENGINE_DISP ] = &nv50_disp_oclass; + device->oclass[NVDEV_ENGINE_DISP ] = &nv84_disp_oclass; break; case 0x94: device->cname = "G94"; @@ -173,7 +173,7 @@ nv50_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass; device->oclass[NVDEV_ENGINE_CRYPT ] = &nv84_crypt_oclass; device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass; - device->oclass[NVDEV_ENGINE_DISP ] = &nv50_disp_oclass; + device->oclass[NVDEV_ENGINE_DISP ] = &nv94_disp_oclass; break; case 0x96: device->cname = "G96"; @@ -198,7 +198,7 @@ nv50_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass; device->oclass[NVDEV_ENGINE_CRYPT ] = &nv84_crypt_oclass; device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass; - device->oclass[NVDEV_ENGINE_DISP ] = &nv50_disp_oclass; + device->oclass[NVDEV_ENGINE_DISP ] = &nv94_disp_oclass; break; case 0x98: device->cname = "G98"; @@ -223,7 +223,7 @@ nv50_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_CRYPT ] = &nv98_crypt_oclass; device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass; device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass; - device->oclass[NVDEV_ENGINE_DISP ] = &nv50_disp_oclass; + device->oclass[NVDEV_ENGINE_DISP ] = &nv94_disp_oclass; break; case 0xa0: device->cname = "G200"; @@ -248,7 +248,7 @@ nv50_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass; device->oclass[NVDEV_ENGINE_CRYPT ] = &nv84_crypt_oclass; device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass; - device->oclass[NVDEV_ENGINE_DISP ] = &nv50_disp_oclass; + device->oclass[NVDEV_ENGINE_DISP ] = &nva0_disp_oclass; break; case 0xaa: device->cname = "MCP77/MCP78"; @@ -273,7 +273,7 @@ nv50_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_CRYPT ] = &nv98_crypt_oclass; device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass; device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass; - device->oclass[NVDEV_ENGINE_DISP ] = &nv50_disp_oclass; + device->oclass[NVDEV_ENGINE_DISP ] = &nv94_disp_oclass; break; case 0xac: device->cname = "MCP79/MCP7A"; @@ -298,7 +298,7 @@ nv50_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_CRYPT ] = &nv98_crypt_oclass; device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass; device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass; - device->oclass[NVDEV_ENGINE_DISP ] = &nv50_disp_oclass; + device->oclass[NVDEV_ENGINE_DISP ] = &nv94_disp_oclass; break; case 0xa3: device->cname = "GT215"; @@ -324,7 +324,7 @@ nv50_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass; device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass; device->oclass[NVDEV_ENGINE_COPY0 ] = &nva3_copy_oclass; - device->oclass[NVDEV_ENGINE_DISP ] = &nv50_disp_oclass; + device->oclass[NVDEV_ENGINE_DISP ] = &nva3_disp_oclass; break; case 0xa5: device->cname = "GT216"; @@ -349,7 +349,7 @@ nv50_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass; device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass; device->oclass[NVDEV_ENGINE_COPY0 ] = &nva3_copy_oclass; - device->oclass[NVDEV_ENGINE_DISP ] = &nv50_disp_oclass; + device->oclass[NVDEV_ENGINE_DISP ] = &nva3_disp_oclass; break; case 0xa8: device->cname = "GT218"; @@ -374,7 +374,7 @@ nv50_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass; device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass; device->oclass[NVDEV_ENGINE_COPY0 ] = &nva3_copy_oclass; - device->oclass[NVDEV_ENGINE_DISP ] = &nv50_disp_oclass; + device->oclass[NVDEV_ENGINE_DISP ] = &nva3_disp_oclass; break; case 0xaf: device->cname = "MCP89"; @@ -399,7 +399,7 @@ nv50_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass; device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass; device->oclass[NVDEV_ENGINE_COPY0 ] = &nva3_copy_oclass; - device->oclass[NVDEV_ENGINE_DISP ] = &nv50_disp_oclass; + device->oclass[NVDEV_ENGINE_DISP ] = &nva3_disp_oclass; break; default: nv_fatal(device, "unknown Tesla chipset\n"); diff --git a/drivers/gpu/drm/nouveau/core/subdev/device/nvc0.c b/drivers/gpu/drm/nouveau/core/subdev/device/nvc0.c index 0429ab45036..771df4ee27f 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/device/nvc0.c +++ b/drivers/gpu/drm/nouveau/core/subdev/device/nvc0.c @@ -79,7 +79,7 @@ nvc0_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass; device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass; device->oclass[NVDEV_ENGINE_COPY1 ] = &nvc0_copy1_oclass; - device->oclass[NVDEV_ENGINE_DISP ] = &nv50_disp_oclass; + device->oclass[NVDEV_ENGINE_DISP ] = &nva3_disp_oclass; break; case 0xc4: device->cname = "GF104"; @@ -107,7 +107,7 @@ nvc0_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass; device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass; device->oclass[NVDEV_ENGINE_COPY1 ] = &nvc0_copy1_oclass; - device->oclass[NVDEV_ENGINE_DISP ] = &nv50_disp_oclass; + device->oclass[NVDEV_ENGINE_DISP ] = &nva3_disp_oclass; break; case 0xc3: device->cname = "GF106"; @@ -135,7 +135,7 @@ nvc0_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass; device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass; device->oclass[NVDEV_ENGINE_COPY1 ] = &nvc0_copy1_oclass; - device->oclass[NVDEV_ENGINE_DISP ] = &nv50_disp_oclass; + device->oclass[NVDEV_ENGINE_DISP ] = &nva3_disp_oclass; break; case 0xce: device->cname = "GF114"; @@ -163,7 +163,7 @@ nvc0_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass; device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass; device->oclass[NVDEV_ENGINE_COPY1 ] = &nvc0_copy1_oclass; - device->oclass[NVDEV_ENGINE_DISP ] = &nv50_disp_oclass; + device->oclass[NVDEV_ENGINE_DISP ] = &nva3_disp_oclass; break; case 0xcf: device->cname = "GF116"; @@ -191,7 +191,7 @@ nvc0_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass; device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass; device->oclass[NVDEV_ENGINE_COPY1 ] = &nvc0_copy1_oclass; - device->oclass[NVDEV_ENGINE_DISP ] = &nv50_disp_oclass; + device->oclass[NVDEV_ENGINE_DISP ] = &nva3_disp_oclass; break; case 0xc1: device->cname = "GF108"; @@ -219,7 +219,7 @@ nvc0_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass; device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass; device->oclass[NVDEV_ENGINE_COPY1 ] = &nvc0_copy1_oclass; - device->oclass[NVDEV_ENGINE_DISP ] = &nv50_disp_oclass; + device->oclass[NVDEV_ENGINE_DISP ] = &nva3_disp_oclass; break; case 0xc8: device->cname = "GF110"; @@ -247,7 +247,7 @@ nvc0_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass; device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass; device->oclass[NVDEV_ENGINE_COPY1 ] = &nvc0_copy1_oclass; - device->oclass[NVDEV_ENGINE_DISP ] = &nv50_disp_oclass; + device->oclass[NVDEV_ENGINE_DISP ] = &nva3_disp_oclass; break; case 0xd9: device->cname = "GF119"; |