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| author | Chen Zhen <zhen1.chen@samsung.com> | 2014-05-12 13:51:00 +0800 |
|---|---|---|
| committer | Chanho Park <chanho61.park@samsung.com> | 2014-11-18 11:47:50 +0900 |
| commit | bae0310a4bb0c74a22ae836c75e419887ea7365d (patch) | |
| tree | da7a91cf417243ec9a4897e472024f25244d638f /sound/soc | |
| parent | 15267745f1cefbf3be3fe4d26a59e4f8d7336429 (diff) | |
| download | linux-3.10-bae0310a4bb0c74a22ae836c75e419887ea7365d.tar.gz linux-3.10-bae0310a4bb0c74a22ae836c75e419887ea7365d.tar.bz2 linux-3.10-bae0310a4bb0c74a22ae836c75e419887ea7365d.zip | |
ASoC: Samsung: reset the BUS clock divider ratio from 2 to 10
when codec work at master mode, the CDCLK was used to MCLK for codec,
but previous CDCLK was too big for max98090,so change its divider
ratio from 2 to 10,and now the CDCLK is 19.2MHz.
Change-Id: I6246cdc85e1b33b0c2bc2128135b27bbc7c00ccb
Signed-off-by: Chen Zhen <zhen1.chen@samsung.com>
Diffstat (limited to 'sound/soc')
| -rw-r--r-- | sound/soc/samsung/i2s.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/sound/soc/samsung/i2s.c b/sound/soc/samsung/i2s.c index cd063bca9b1..a486c45b86a 100644 --- a/sound/soc/samsung/i2s.c +++ b/sound/soc/samsung/i2s.c @@ -37,8 +37,8 @@ #define MHZ (1000*1000) #endif -#define TARGET_SRPCLK_RATE (200 * MHZ) -#define TARGET_BUSCLK_RATE (100 * MHZ) +#define TARGET_SRPCLK_RATE (192 * MHZ) +#define TARGET_BUSCLK_RATE (19200000) enum samsung_dai_type { TYPE_PRI, |