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| author | Len Brown <len.brown@intel.com> | 2009-12-16 14:07:29 -0500 |
|---|---|---|
| committer | Len Brown <len.brown@intel.com> | 2009-12-16 14:07:29 -0500 |
| commit | 2900681b25d5a1a1a7b39ab66da3b8c6b1b0b7ad (patch) | |
| tree | 3c6969f0333f1255a4751086dd1131d5bbc5a157 /include | |
| parent | 243e1ef842ef9e24fbf1cc7ddf4fd1c01471544a (diff) | |
| parent | 3563ff964fdc36358cef0330936fdac28e65142a (diff) | |
| download | linux-3.10-2900681b25d5a1a1a7b39ab66da3b8c6b1b0b7ad.tar.gz linux-3.10-2900681b25d5a1a1a7b39ab66da3b8c6b1b0b7ad.tar.bz2 linux-3.10-2900681b25d5a1a1a7b39ab66da3b8c6b1b0b7ad.zip | |
Merge branch 'osc' into release
Diffstat (limited to 'include')
| -rw-r--r-- | include/linux/acpi.h | 21 |
1 files changed, 19 insertions, 2 deletions
diff --git a/include/linux/acpi.h b/include/linux/acpi.h index dfcd920c3e5..e11090d462d 100644 --- a/include/linux/acpi.h +++ b/include/linux/acpi.h @@ -253,10 +253,16 @@ void __init acpi_old_suspend_ordering(void); void __init acpi_s4_no_nvs(void); #endif /* CONFIG_PM_SLEEP */ +struct acpi_osc_context { + char *uuid_str; /* uuid string */ + int rev; + struct acpi_buffer cap; /* arg2/arg3 */ + struct acpi_buffer ret; /* free by caller if success */ +}; + #define OSC_QUERY_TYPE 0 #define OSC_SUPPORT_TYPE 1 #define OSC_CONTROL_TYPE 2 -#define OSC_SUPPORT_MASKS 0x1f /* _OSC DW0 Definition */ #define OSC_QUERY_ENABLE 1 @@ -265,12 +271,23 @@ void __init acpi_s4_no_nvs(void); #define OSC_INVALID_REVISION_ERROR 8 #define OSC_CAPABILITIES_MASK_ERROR 16 +acpi_status acpi_run_osc(acpi_handle handle, struct acpi_osc_context *context); + +/* platform-wide _OSC bits */ +#define OSC_SB_PAD_SUPPORT 1 +#define OSC_SB_PPC_OST_SUPPORT 2 +#define OSC_SB_PR3_SUPPORT 4 +#define OSC_SB_CPUHP_OST_SUPPORT 8 +#define OSC_SB_APEI_SUPPORT 16 + +/* PCI defined _OSC bits */ /* _OSC DW1 Definition (OS Support Fields) */ #define OSC_EXT_PCI_CONFIG_SUPPORT 1 #define OSC_ACTIVE_STATE_PWR_SUPPORT 2 #define OSC_CLOCK_PWR_CAPABILITY_SUPPORT 4 #define OSC_PCI_SEGMENT_GROUPS_SUPPORT 8 #define OSC_MSI_SUPPORT 16 +#define OSC_PCI_SUPPORT_MASKS 0x1f /* _OSC DW1 Definition (OS Control Fields) */ #define OSC_PCI_EXPRESS_NATIVE_HP_CONTROL 1 @@ -279,7 +296,7 @@ void __init acpi_s4_no_nvs(void); #define OSC_PCI_EXPRESS_AER_CONTROL 8 #define OSC_PCI_EXPRESS_CAP_STRUCTURE_CONTROL 16 -#define OSC_CONTROL_MASKS (OSC_PCI_EXPRESS_NATIVE_HP_CONTROL | \ +#define OSC_PCI_CONTROL_MASKS (OSC_PCI_EXPRESS_NATIVE_HP_CONTROL | \ OSC_SHPC_NATIVE_HP_CONTROL | \ OSC_PCI_EXPRESS_PME_CONTROL | \ OSC_PCI_EXPRESS_AER_CONTROL | \ |