summaryrefslogtreecommitdiff
path: root/include/media/saa7115.h
diff options
context:
space:
mode:
authorHans Verkuil <hverkuil@xs4all.nl>2006-04-02 12:50:42 -0300
committerMauro Carvalho Chehab <mchehab@infradead.org>2006-06-25 01:57:36 -0300
commitb7f8292c96463810edfecff70dd4631d47e5a36b (patch)
tree02b1cfb3f753ea82c6fa51c901420074875be355 /include/media/saa7115.h
parent2eb606db1134ce860cc0cbf8b533b6315d182e21 (diff)
downloadlinux-3.10-b7f8292c96463810edfecff70dd4631d47e5a36b.tar.gz
linux-3.10-b7f8292c96463810edfecff70dd4631d47e5a36b.tar.bz2
linux-3.10-b7f8292c96463810edfecff70dd4631d47e5a36b.zip
V4L/DVB (3711): Add support for VIDIOC_INT_S_CRYSTAL_FREQ internal command.
Some saa7115-based cards use a different crystal frequency and a different audio clock generation. Add a new VIDIOC_INT_S_CRYSTAL_FREQ command to be able to set these values. Also change the default APLL setting to 0. It makes no sense to have the audio clock independent from the video clock, this can lead to audio/video synchronization problems. Setting this to 0 is also consistent with the old saa7114.c source and the way the Hauppauge Windows driver sets it. Signed-off-by: Hans Verkuil <hverkuil@xs4all.nl> Signed-off-by: Mauro Carvalho Chehab <mchehab@infradead.org>
Diffstat (limited to 'include/media/saa7115.h')
-rw-r--r--include/media/saa7115.h11
1 files changed, 10 insertions, 1 deletions
diff --git a/include/media/saa7115.h b/include/media/saa7115.h
index 6b4836f3f05..9f0e2285a09 100644
--- a/include/media/saa7115.h
+++ b/include/media/saa7115.h
@@ -1,5 +1,5 @@
/*
- saa7115.h - definition for saa7113/4/5 inputs
+ saa7115.h - definition for saa7113/4/5 inputs and frequency flags
Copyright (C) 2006 Hans Verkuil (hverkuil@xs4all.nl)
@@ -33,5 +33,14 @@
#define SAA7115_SVIDEO2 8
#define SAA7115_SVIDEO3 9
+/* SAA7115 v4l2_crystal_freq frequency values */
+#define SAA7115_FREQ_32_11_MHZ 32110000 /* 32.11 MHz crystal, SAA7114/5 only */
+#define SAA7115_FREQ_24_576_MHZ 24576000 /* 24.576 MHz crystal */
+
+/* SAA7115 v4l2_crystal_freq audio clock control flags */
+#define SAA7115_FREQ_FL_UCGC (1 << 0) /* SA 3A[7], UCGC, SAA7115 only */
+#define SAA7115_FREQ_FL_CGCDIV (1 << 1) /* SA 3A[6], CGCDIV, SAA7115 only */
+#define SAA7115_FREQ_FL_APLL (1 << 2) /* SA 3A[3], APLL, SAA7114/5 only */
+
#endif