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| author | Thomas Gleixner <tglx@linutronix.de> | 2011-02-08 17:28:12 +0100 |
|---|---|---|
| committer | Thomas Gleixner <tglx@linutronix.de> | 2011-02-19 12:58:20 +0100 |
| commit | 876dbd4cc1b35c1a4cb96a2be1d43ea0eabce3b4 (patch) | |
| tree | 9be1e7e4cd4a4c9fadd98a9ac637020417215521 /include/linux/irq.h | |
| parent | 2bdd10558c8d93009cb6c32ce9e30800fbb08add (diff) | |
| download | linux-3.10-876dbd4cc1b35c1a4cb96a2be1d43ea0eabce3b4.tar.gz linux-3.10-876dbd4cc1b35c1a4cb96a2be1d43ea0eabce3b4.tar.bz2 linux-3.10-876dbd4cc1b35c1a4cb96a2be1d43ea0eabce3b4.zip | |
genirq: Mirror irq trigger type bits in irq_data.state
That's the data structure chip functions get provided. Also allow them
to signal the core code that they updated the flags in irq_data.state
by returning IRQ_SET_MASK_OK_NOCOPY. The default is unchanged.
The type bits should be accessed via:
val = irqd_get_trigger_type(irqdata);
and
irqd_set_trigger_type(irqdata, val);
Coders who access them directly will be tracked down and slapped with
stinking trouts.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Diffstat (limited to 'include/linux/irq.h')
| -rw-r--r-- | include/linux/irq.h | 26 |
1 files changed, 25 insertions, 1 deletions
diff --git a/include/linux/irq.h b/include/linux/irq.h index 8da1782ecfc..be73c0a3c19 100644 --- a/include/linux/irq.h +++ b/include/linux/irq.h @@ -46,7 +46,9 @@ typedef void (*irq_flow_handler_t)(unsigned int irq, #define IRQ_TYPE_EDGE_BOTH (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING) #define IRQ_TYPE_LEVEL_HIGH 0x00000004 /* Level high type */ #define IRQ_TYPE_LEVEL_LOW 0x00000008 /* Level low type */ +#define IRQ_TYPE_LEVEL_MASK (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH) #define IRQ_TYPE_SENSE_MASK 0x0000000f /* Mask of the above */ + #define IRQ_TYPE_PROBE 0x00000010 /* Probing in progress */ /* Internal flags */ @@ -131,17 +133,20 @@ struct irq_data { /* * Bit masks for irq_data.state * + * IRQD_TRIGGER_MASK - Mask for the trigger type bits * IRQD_SETAFFINITY_PENDING - Affinity setting is pending * IRQD_NO_BALANCING - Balancing disabled for this IRQ * IRQD_PER_CPU - Interrupt is per cpu * IRQD_AFFINITY_SET - Interrupt affinity was set + * IRQD_LEVEL - Interrupt is level triggered */ enum { - /* Bit 0 - 7 reserved for TYPE will use later */ + IRQD_TRIGGER_MASK = 0xf, IRQD_SETAFFINITY_PENDING = (1 << 8), IRQD_NO_BALANCING = (1 << 10), IRQD_PER_CPU = (1 << 11), IRQD_AFFINITY_SET = (1 << 12), + IRQD_LEVEL = (1 << 13), }; static inline bool irqd_is_setaffinity_pending(struct irq_data *d) @@ -164,6 +169,25 @@ static inline bool irqd_affinity_was_set(struct irq_data *d) return d->state_use_accessors & IRQD_AFFINITY_SET; } +static inline u32 irqd_get_trigger_type(struct irq_data *d) +{ + return d->state_use_accessors & IRQD_TRIGGER_MASK; +} + +/* + * Must only be called inside irq_chip.irq_set_type() functions. + */ +static inline void irqd_set_trigger_type(struct irq_data *d, u32 type) +{ + d->state_use_accessors &= ~IRQD_TRIGGER_MASK; + d->state_use_accessors |= type & IRQD_TRIGGER_MASK; +} + +static inline bool irqd_is_level_type(struct irq_data *d) +{ + return d->state_use_accessors & IRQD_LEVEL; +} + /** * struct irq_chip - hardware interrupt chip descriptor * |