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author | Jamie Lenehan <lenehan@twibble.org> | 2006-12-06 12:05:02 +0900 |
---|---|---|
committer | Paul Mundt <lethal@linux-sh.org> | 2006-12-06 12:05:02 +0900 |
commit | ea0f8feaa041f3ccec3d6b8ee51325b177daef06 (patch) | |
tree | 261c7d75e5caccbaface63370bae029ecd81b98a /include/asm-sh | |
parent | fe9687dec0400c6de7187ab5efa91facd958ca84 (diff) | |
download | linux-3.10-ea0f8feaa041f3ccec3d6b8ee51325b177daef06.tar.gz linux-3.10-ea0f8feaa041f3ccec3d6b8ee51325b177daef06.tar.bz2 linux-3.10-ea0f8feaa041f3ccec3d6b8ee51325b177daef06.zip |
sh: sh775x/titan fixes for irq header changes.
The following moves the creation of IPR interupts into setup-7750.c
and updates a few other things to make it all work after the "Drop
CPU subtype IRQ headers" commit. It boots and runs fine on my titan
board.
- adds an ipr_idx to the ipr_data and uses a function in the subtype
code to calculate the address of the IPR registers
- adds a function to enable individual interrupt mode for externals
in the subtype code and calls that from the titan board code
instead of doing it directly.
- I changed the shift in the ipr_data to be the actual # of bits to
shift, instead of the numnber / 4 - made it easier to match with
the manual.
Signed-off-by: Jamie Lenehan <lenehan@twibble.org>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'include/asm-sh')
-rw-r--r-- | include/asm-sh/irq.h | 32 | ||||
-rw-r--r-- | include/asm-sh/titan.h | 32 |
2 files changed, 31 insertions, 33 deletions
diff --git a/include/asm-sh/irq.h b/include/asm-sh/irq.h index f10cfc10227..fd576088e47 100644 --- a/include/asm-sh/irq.h +++ b/include/asm-sh/irq.h @@ -93,6 +93,12 @@ #define NR_IRQS (ONCHIP_NR_IRQS + PINT_NR_IRQS + OFFCHIP_NR_IRQS) /* + * Convert back and forth between INTEVT and IRQ values. + */ +#define evt2irq(evt) (((evt) >> 5) - 16) +#define irq2evt(irq) (((irq) + 16) << 5) + +/* * Simple Mask Register Support */ extern void make_maskreg_irq(unsigned int irq); @@ -103,18 +109,36 @@ extern unsigned short *irq_mask_register; */ void init_IRQ_pint(void); +/* + * The shift value is now the number of bits to shift, not the number of + * bits/4. This is to make it easier to read the value directly from the + * datasheets. The IPR address, addr, will be set from ipr_idx via the + * map_ipridx_to_addr function. + */ struct ipr_data { unsigned int irq; - unsigned int addr; /* Address of Interrupt Priority Register */ - int shift; /* Shifts of the 16-bit data */ + int ipr_idx; /* Index for the IPR registered */ + int shift; /* Number of bits to shift the data */ int priority; /* The priority */ + unsigned int addr; /* Address of Interrupt Priority Register */ }; /* + * Given an IPR IDX, map the value to an IPR register address. + */ +unsigned int map_ipridx_to_addr(int idx); + +/* + * Enable individual interrupt mode for external IPR IRQs. + */ +void ipr_irq_enable_irlm(void); + +/* * Function for "on chip support modules". */ -extern void make_ipr_irq(struct ipr_data *table, unsigned int nr_irqs); -extern void make_imask_irq(unsigned int irq); +void make_ipr_irq(struct ipr_data *table, unsigned int nr_irqs); +void make_imask_irq(unsigned int irq); +void init_IRQ_ipr(void); struct intc2_data { unsigned short irq; diff --git a/include/asm-sh/titan.h b/include/asm-sh/titan.h index 270a4f4bc8a..03f3583c891 100644 --- a/include/asm-sh/titan.h +++ b/include/asm-sh/titan.h @@ -1,9 +1,8 @@ /* * Platform defintions for Titan */ - -#ifndef _ASM_SH_TITAN_TITAN_H -#define _ASM_SH_TITAN_TITAN_H +#ifndef _ASM_SH_TITAN_H +#define _ASM_SH_TITAN_H #define __IO_PREFIX titan #include <asm/io_generic.h> @@ -15,29 +14,4 @@ #define TITAN_IRQ_MPCIB 11 /* mPCI B */ #define TITAN_IRQ_USB 11 /* USB */ -/* - * The external interrupt lines, these take up ints 0 - 15 inclusive - * depending on the priority for the interrupt. In fact the priority - * is the interrupt :-) - */ -#define IRL0_IRQ 0 -#define IRL0_IPR_ADDR INTC_IPRD -#define IRL0_IPR_POS 3 -#define IRL0_PRIORITY 8 - -#define IRL1_IRQ 1 -#define IRL1_IPR_ADDR INTC_IPRD -#define IRL1_IPR_POS 2 -#define IRL1_PRIORITY 8 - -#define IRL2_IRQ 2 -#define IRL2_IPR_ADDR INTC_IPRD -#define IRL2_IPR_POS 1 -#define IRL2_PRIORITY 8 - -#define IRL3_IRQ 3 -#define IRL3_IPR_ADDR INTC_IPRD -#define IRL3_IPR_POS 0 -#define IRL3_PRIORITY 8 - -#endif +#endif /* __ASM_SH_TITAN_H */ |