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| author | Christoph Lameter <clameter@sgi.com> | 2007-12-18 16:22:46 -0800 |
|---|---|---|
| committer | Tony Luck <tony.luck@intel.com> | 2007-12-18 16:22:46 -0800 |
| commit | a3ebdb6c423dff420168a3faf25c76e9e5f59258 (patch) | |
| tree | 397317fda83da7f745d802d5ba87735f163bf1c9 /include/asm-ia64 | |
| parent | c63a1190368771b8207d86c4217ae4afdf1cbd5e (diff) | |
| download | linux-3.10-a3ebdb6c423dff420168a3faf25c76e9e5f59258.tar.gz linux-3.10-a3ebdb6c423dff420168a3faf25c76e9e5f59258.tar.bz2 linux-3.10-a3ebdb6c423dff420168a3faf25c76e9e5f59258.zip | |
IA64: Slim down __clear_bit_unlock
__clear_bit_unlock does not need to perform atomic operations on the
variable. Avoid a cmpxchg and simply do a store with release semantics.
Add a barrier to be safe that the compiler does not do funky things.
Tony: Use intrinsic rather than inline assembler
Signed-off-by: Christoph Lameter <clameter@sgi.com>
Acked-by: Nick Piggin <nickpiggin@yahoo.com.au>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Tony Luck <tony.luck@intel.com>
Diffstat (limited to 'include/asm-ia64')
| -rw-r--r-- | include/asm-ia64/bitops.h | 17 | ||||
| -rw-r--r-- | include/asm-ia64/gcc_intrin.h | 5 | ||||
| -rw-r--r-- | include/asm-ia64/intel_intrin.h | 3 |
3 files changed, 22 insertions, 3 deletions
diff --git a/include/asm-ia64/bitops.h b/include/asm-ia64/bitops.h index a977affaebe..a1b9719f5fb 100644 --- a/include/asm-ia64/bitops.h +++ b/include/asm-ia64/bitops.h @@ -124,10 +124,21 @@ clear_bit_unlock (int nr, volatile void *addr) /** * __clear_bit_unlock - Non-atomically clear a bit with release * - * This is like clear_bit_unlock, but the implementation may use a non-atomic - * store (this one uses an atomic, however). + * This is like clear_bit_unlock, but the implementation uses a store + * with release semantics. See also __raw_spin_unlock(). */ -#define __clear_bit_unlock clear_bit_unlock +static __inline__ void +__clear_bit_unlock(int nr, volatile void *addr) +{ + __u32 mask, new; + volatile __u32 *m; + + m = (volatile __u32 *)addr + (nr >> 5); + mask = ~(1 << (nr & 31)); + new = *m & mask; + barrier(); + ia64_st4_rel_nta(m, new); +} /** * __clear_bit - Clears a bit in memory (non-atomic version) diff --git a/include/asm-ia64/gcc_intrin.h b/include/asm-ia64/gcc_intrin.h index 4fb4e439b05..e58d3298fa1 100644 --- a/include/asm-ia64/gcc_intrin.h +++ b/include/asm-ia64/gcc_intrin.h @@ -191,6 +191,11 @@ register unsigned long ia64_r13 asm ("r13") __attribute_used__; asm volatile ("ldf.fill %0=[%1]" :"=f"(__f__): "r"(x)); \ }) +#define ia64_st4_rel_nta(m, val) \ +({ \ + asm volatile ("st4.rel.nta [%0] = %1\n\t" :: "r"(m), "r"(val)); \ +}) + #define ia64_stfs(x, regnum) \ ({ \ register double __f__ asm ("f"#regnum); \ diff --git a/include/asm-ia64/intel_intrin.h b/include/asm-ia64/intel_intrin.h index d069b6acddc..a520d103d80 100644 --- a/include/asm-ia64/intel_intrin.h +++ b/include/asm-ia64/intel_intrin.h @@ -110,6 +110,9 @@ #define ia64_st4_rel __st4_rel #define ia64_st8_rel __st8_rel +/* FIXME: need st4.rel.nta intrinsic */ +#define ia64_st4_rel_nta __st4_rel + #define ia64_ld1_acq __ld1_acq #define ia64_ld2_acq __ld2_acq #define ia64_ld4_acq __ld4_acq |