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| author | Andi Kleen <ak@suse.de> | 2007-08-10 22:31:07 +0200 |
|---|---|---|
| committer | Linus Torvalds <torvalds@woody.linux-foundation.org> | 2007-08-11 15:58:13 -0700 |
| commit | d3f7eae182b04997be19343a23f7009170f4f7a5 (patch) | |
| tree | 162fc610811c762b322eedaae909847ab4465da1 /include/asm-i386 | |
| parent | d2d0251f6faa2cf341500a44310bbaa815a8a972 (diff) | |
| download | linux-3.10-d3f7eae182b04997be19343a23f7009170f4f7a5.tar.gz linux-3.10-d3f7eae182b04997be19343a23f7009170f4f7a5.tar.bz2 linux-3.10-d3f7eae182b04997be19343a23f7009170f4f7a5.zip | |
i386: Use global flag to disable broken local apic timer on AMD CPUs.
The Averatec 2370 and some other Turion laptop BIOS seems to program the
ENABLE_C1E MSR inconsistently between cores. This confuses the lapic
use heuristics because when C1E is enabled anywhere it seems to affect
the complete chip.
Use a global flag instead of a per cpu flag to handle this.
If any CPU has C1E enabled disabled lapic use.
Thanks to Cal Peake for debugging.
Cc: tglx@linutronix.de
Signed-off-by: Andi Kleen <ak@suse.de>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Diffstat (limited to 'include/asm-i386')
| -rw-r--r-- | include/asm-i386/apic.h | 2 | ||||
| -rw-r--r-- | include/asm-i386/cpufeature.h | 2 |
2 files changed, 3 insertions, 1 deletions
diff --git a/include/asm-i386/apic.h b/include/asm-i386/apic.h index 1e8f6f252dd..4091b33dcb1 100644 --- a/include/asm-i386/apic.h +++ b/include/asm-i386/apic.h @@ -116,6 +116,8 @@ extern void enable_NMI_through_LVT0 (void * dummy); extern int timer_over_8254; extern int local_apic_timer_c2_ok; +extern int local_apic_timer_disabled; + #else /* !CONFIG_X86_LOCAL_APIC */ static inline void lapic_shutdown(void) { } diff --git a/include/asm-i386/cpufeature.h b/include/asm-i386/cpufeature.h index c961c03cf1e..7b3aa28ebc6 100644 --- a/include/asm-i386/cpufeature.h +++ b/include/asm-i386/cpufeature.h @@ -79,7 +79,7 @@ #define X86_FEATURE_ARCH_PERFMON (3*32+11) /* Intel Architectural PerfMon */ #define X86_FEATURE_PEBS (3*32+12) /* Precise-Event Based Sampling */ #define X86_FEATURE_BTS (3*32+13) /* Branch Trace Store */ -#define X86_FEATURE_LAPIC_TIMER_BROKEN (3*32+ 14) /* lapic timer broken in C1 */ +/* 14 free */ #define X86_FEATURE_SYNC_RDTSC (3*32+15) /* RDTSC synchronizes the CPU */ #define X86_FEATURE_REP_GOOD (3*32+16) /* rep microcode works well on this CPU */ |